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    • 2. 发明授权
      US5350698A Multilayer polysilicon gate self-align process for VLSI CMOS device 失效
    • Multilayer polysilicon gate self-align process for VLSI CMOS device
    • 用于VLSI CMOS器件的多层多晶硅栅极自对准工艺
    • US5350698A
    • 1994-09-27
    • US55567
    • 1993-05-03
    • Heng-Sheng Huang , Kun-Luh Chen , Gary Hong
    • Heng-Sheng Huang , Kun-Luh Chen , Gary Hong
    • H01L21/28 , H01L21/336 , H01L29/49 , H01L29/78 , H01L21/265 , B05D3/06 , C23C16/00
    • H01L29/6659 , H01L21/28035 , H01L29/4925 , H01L29/4933 , H01L29/7833
    • A new method of forming a self-aligning polysilicon gate is described. A gate silicon oxide is formed over a silicon substrate. A polysilicon layer is formed over the gate oxide. A native silicon oxide layer is formed over the polysilicon layer. A second polysilicon layer is formed over the native silicon oxide layer. Additional alternating layers of polysilicon and native silicon oxide are formed as desired. The wafer is annealed at between about 800.degree. to 1000.degree. C. This causes, it is believed, the silicon oxide gas from the multiple native silicon oxide layers to be exhausted resulting in the removal of all silicon oxide layers. A polycide layer is formed overlying the multiple polysilicon layers, if desired. Conventional lithography and etching techniques are used to form a gate. Ions are implanted into the substrate to form source/drain regions, using the multilayer gate as a mask. Rapid thermal annealing activates the impurities. A dielectric layer is deposited followed by conventional metallization techniques to complete construction of the integrated circuit.
    • 描述形成自对准多晶硅栅极的新方法。 在硅衬底上形成栅氧化硅。 在栅极氧化物上形成多晶硅层。 在多晶硅层上形成天然硅氧化物层。 在天然氧化硅层上形成第二多晶硅层。 根据需要形成多晶硅和天然氧化硅的附加交替层。 晶片在约800℃至1000℃之间退火。据信，来自多个天然氧化硅层的氧化硅气体被排出，导致所有氧化硅层的去除。 如果需要，多晶硅层形成在多个多晶硅层上。 常规的光刻和蚀刻技术被用于形成栅极。 使用多层栅极作为掩模将离子注入到衬底中以形成源极/漏极区域。 快速热退火激活杂质。 沉积介电层，然后通过常规金属化技术来完成集成电路的构造。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 3. 发明授权
      US6015746A Method of fabricating semiconductor device with a gate-side air-gap structure 失效
    • Method of fabricating semiconductor device with a gate-side air-gap structure
    • 制造具有栅极侧气隙结构的半导体器件的方法
    • US6015746A
    • 2000-01-18
    • US056530
    • 1998-04-07
    • Wen-Kuan Yeh , Tony Lin , Heng-Sheng Huang
    • Wen-Kuan Yeh , Tony Lin , Heng-Sheng Huang
    • H01L21/336 , H01L29/423 , H01L29/49 , H01L21/3205 , H01L21/4763
    • H01L29/66583 , H01L29/4983 , H01L29/4991 , H01L29/42376 , H01L29/4238 , H01L29/665
    • A method of fabricating a semiconductor device. On a semiconductor substrate comprising a device isolation structure and an active region isolated by the device isolation region, an oxide layer is formed and etched on the active region to form an opening, so that the active within the opening is exposed. A first spacer is formed on a side wall of the opening. A gate oxide layer is formed on the active region within the opening. A conductive layer is formed on the gate oxide layer, so that the opening is filled thereby. The oxide layer is removed. The exposed active region is lightly doped to form a lightly doped region by using the conductive layer and the first spacer as a mask. A second spacer is formed on a side wall of the first spacer and leaves a portion of the first spacer to be exposed. The exposed active region is heavily doped to form a source/drain region by using the conductive layer, the first spacer, and the second spacer as a mask. The first spacer is removed to define a gate, so that an air gap between the gate and the second spacer is formed.
    • 一种制造半导体器件的方法。 在包括器件隔离结构和由器件隔离区隔离的有源区的半导体衬底上，在有源区上形成氧化层并蚀刻以形成开口，从而露出开口内的活性物质。 第一间隔件形成在开口的侧壁上。 栅极氧化层形成在开口内的有源区上。 在栅极氧化物层上形成导电层，从而填充开口。 去除氧化物层。 通过使用导电层和第一间隔物作为掩模，暴露的有源区域被轻掺杂以形成轻掺杂区域。 第二间隔件形成在第一间隔件的侧壁上并且留下待暴露的第一间隔件的一部分。 通过使用导电层，第一间隔件和第二间隔件作为掩模，暴露的有源区域被重掺杂以形成源极/漏极区域。 去除第一间隔物以限定栅极，从而形成栅极和第二间隔物之间​​的气隙。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 4. 发明授权
      US5659511A Method for measuring the current leakage of a dynamic random access memory capacitive junction 失效
    • Method for measuring the current leakage of a dynamic random access memory capacitive junction
    • 用于测量动态随机存取存储器电容结的电流泄漏的方法
    • US5659511A
    • 1997-08-19
    • US643363
    • 1996-05-06
    • Heng-Sheng Huang
    • Heng-Sheng Huang
    • G01R31/30 , G11C29/50 , G11C7/00
    • G01R31/3004 , G11C29/50 , G11C11/401 , G11C2029/5006
    • A method of measuring the leakage current of a DRAM capacitive junction involves the of following steps: A DRAM memory is formed on a semiconductor substrate. The DRAM memory comprises a plurality of RAM memory cells and a measuring memory cell. Each of the RAM memory cells and the measuring memory cell includes a transistor and a capacitor serially connected. The contact area of a bottom plate of the capacitor of the measuring memory cell is much larger than that of the RAM memory cells. A first junction leakage current value is measured while the transistor of the measuring memory cell is turned off. A second junction leakage current value is measured while the transistor of the measuring memory cell is turned on. The first junction leakage current value then is subtracted from the second junction leakage current value. By dividing the difference by the contact are of the bottom plate of the capacitor of the measuring memory cell, the capacitive junction leakage current value per unit area of the DRAM is obtained.
    • 测量DRAM电容结的泄漏电流的方法包括以下步骤：在半导体衬底上形成DRAM存储器。 DRAM存储器包括多个RAM存储器单元和测量存储单元。 每个RAM存储器单元和测量存储单元包括串联连接的晶体管和电容器。 测量存储单元的电容器的底板的接触面积比RAM存储单元的接触面积大得多。 在测量存储单元的晶体管截止时测量第一结漏电流值。 在测量存储单元的晶体管导通时测量第二结漏电流值。 然后从第二结漏电流值中减去第一结漏电流值。 通过将差除以测量存储单元的电容器的底板的接触面积，获得DRAM的每单位面积的电容结漏电流值。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 6. 发明授权
      US06197642B1 Method for manufacturing gate terminal 失效
    • Method for manufacturing gate terminal
    • 栅极端子制造方法
    • US06197642B1
    • 2001-03-06
    • US09028521
    • 1998-02-24
    • Wen-Kuan Yeh , Heng-Sheng Huang
    • Wen-Kuan Yeh , Heng-Sheng Huang
    • H01L21336
    • H01L29/66583 , H01L21/28079 , H01L29/495
    • A method for manufacturing a gate terminal comprising the steps of providing a substrate, then forming and patterning an oxide layer to form a gate region. Next, a gate oxide layer and a crystalline silicon layer are formed in the gate region. This is followed by depositing a tungsten layer in the gate region, and then polishing the tungsten layer to form a final tungsten layer functioning as the gate electrode. Finally, the oxide layer is removed. The method of this invention is able to control the dimensions of the gate terminal produced. Moreover, the formation of a thin crystalline silicon layer over the gate oxide layer helps to increase the bonding strength with the metallic layer, and that the gate electrode can be formed at a lower processing temperature. Therefore, the gate so formed has a higher quality and the processing of the semiconductor is much easier. Furthermore, the silicon nitride layer can serve as an etching stop layer during the etching operation of the oxide layer. Consequently, over-exposing the upper trench corner locations of a shallow trench isolation structure can be prevented, thereby avoiding current leakage problems.
    • 一种用于制造栅极端子的方法，包括以下步骤：提供衬底，然后形成和图案化氧化物层以形成栅极区域。 接下来，在栅极区域形成栅氧化层和晶体硅层。 然后在栅极区域中沉积钨层，然后抛光钨层以形成用作栅电极的最终钨层。 最后，去除氧化物层。 本发明的方法能够控制所制造的栅极端子的尺寸。 此外，在栅极氧化物层上形成薄的晶体硅层有助于增加与金属层的结合强度，并且可以在较低的处理温度下形成栅电极。 因此，如此形成的栅极具有更高的质量，并且半导体的处理容易得多。 此外，在氧化物层的蚀刻操作期间，氮化硅层可以用作蚀刻停止层。 因此，可以防止浅沟槽隔离结构的上沟槽角部位的过度曝光，从而避免电流泄漏问题。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 7. 发明授权
      US5920783A Method of fabricating a self-aligned silicide MOSFET 失效
    • Method of fabricating a self-aligned silicide MOSFET
    • 制造自对准硅化物MOSFET的方法
    • US5920783A
    • 1999-07-06
    • US55692
    • 1998-04-06
    • H. C. Tseng , Kun-Cho Chen , Heng-Sheng Huang
    • H. C. Tseng , Kun-Cho Chen , Heng-Sheng Huang
    • H01L21/28 , H01L21/285 , H01L21/336 , H01L21/60 , H01L21/3205 , H01L21/4763
    • H01L29/66507 , H01L21/28052 , H01L21/28518 , H01L29/665 , H01L29/6656 , H01L29/6659 , Y10S257/90
    • A method of fabricating a MOSFET device in accordance with the present invention can protect the device from the short channel effect and decrease the resistance of a gate of the device. The fabricating method includes the following steps. A device including a substrate, an oxide layer, a gate and a lightly doped region is provided, wherein the oxide layer is formed on the substrate and the gate is formed on the oxide layer. A conducting layer is formed on the oxide layer, and the conducting layer is etched to form a first spacer. Then, the device is implanted to form a heavily doped region. A dielectric layer is deposited on the device, and the dielectric layer is etched to form a second spacer. The oxide layer is etched to expose part of the side walls of the gate. Then, a self-aligned silicide is further processed to complete the fabricating processes. As a result, the MOSFET device has an ultra-shallow junction under the first spacer to reduce the source/drain resistance and increase the operating rate of the device.
    • 根据本发明的制造MOSFET器件的方法可以保护器件免于短沟道效应并降低器件栅极的电阻。 制造方法包括以下步骤。 提供了包括衬底，氧化物层，栅极和轻掺杂区域的器件，其中氧化物层形成在衬底上，并且栅极形成在氧化物层上。 在氧化物层上形成导电层，蚀刻导电层以形成第一间隔物。 然后，将器件植入以形成重掺杂区域。 在器件上沉积介电层，蚀刻电介质层以形成第二间隔物。 蚀刻氧化物层以暴露栅极的一部分侧壁。 然后，进一步处理自对准的硅化物以完成制造工艺。 结果，MOSFET器件在第一间隔物下方具有超浅结，以减少源/漏电阻并增加器件的工作速率。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 8. 发明授权
      US5637896A High coupling ratio flash memory cell 失效
    • High coupling ratio flash memory cell
    • 高耦合比闪存单元
    • US5637896A
    • 1997-06-10
    • US537103
    • 1995-09-29
    • Heng-Sheng Huang
    • Heng-Sheng Huang
    • H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/76
    • H01L27/11521 , H01L27/115
    • A process of fabricating an array of floating gate memory devices on a substrate comprises forming elongated spaced apart parallel ion implanted field implant regions in the substrate, forming elongated spaced apart parallel buried bit lines in the substrate orthogonally directed relative to the field implant regions, forming field oxide regions over the buried bit lines and field implant regions, and growing a silicon dioxide gate oxide layer having a thickness of from approximately 80 .ANG. to approximately 300 .ANG. between the field oxide regions, forming a plurality of first gate members from a first layer of polysilicon, the first gate members being disposed over the gate oxide layer, forming a layer of interpolysilicon dielectric over the first gate members having a thickness of approximately 150 .ANG., forming elongated second gate members from a second layer of polysilicon over the layer of interpolysilicon dielectric and over the first gate members, the second gate members extending generally perpendicular to buried bit lines.
    • 在衬底上制造浮动栅极存储器器件阵列的工艺包括在衬底中形成细长的间隔开的平行离子注入场注入区域，在衬底中相对于场注入区域正交地形成细长间隔开的并行埋入位线，形成 在掩埋位线和场注入区域之上的场氧化物区域，并且在场氧化物区域之间生长厚度大约为80至大约300的二氧化硅栅极氧化物层，从第一层形成多个第一栅极部件 的多晶硅，所述第一栅极部件设置在所述栅极氧化物层的上方，在所述第一栅极部件上形成厚度约为150的多晶硅介质层，在所述多晶硅层上形成从第二多晶硅层延伸的第二栅极部件 电介质和第一栅极部件上的第二栅极 构件大致垂直于掩埋位线延伸。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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