会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 1. 发明公开
    • 펄스 진폭 변조에서 전압 마진을 증가시키는 방법 및 장치
    • 改进PAM电压补偿的方法和装置
    • KR1020090001356A
    • 2009-01-08
    • KR1020070065656
    • 2007-06-29
    • 삼성전자주식회사
    • 신성철최훈대
    • H03K7/02
    • H03K7/02H03C1/62H03K19/00384
    • The method and apparatus for improving the voltage margin of PAM is provided to increase the voltage margin in the comparison process of the signal transmitted with the reference voltage by changing the common-mode level. The input data driving part(110) comprises the zero bit processing unit(MN1 and MN2) and first bit processing unit (MN3 and MN4), and the first current generator (MN5) and the second current source(MN6). The current applied in the first current generator is supplied to the first load (R1) or the second rod(R2) by the zero bit processing unit. The common-mode permutation(120) comprises the third load(R3), the fourth load(R4), and the third current circle(MN11) and common-mode controller. The common-mode controller comprises first output common-mode controller(MN7 and MN8) and second output common-mode controller (MN9 and MN10).
    • 提供了用于提高PAM的电压裕度的方法和装置,以通过改变共模电平来增加与参考电压发送的信号的比较处理中的电压余量。 输入数据驱动部分(110)包括零位处理单元(MN1和MN2)和第一位处理单元(MN3和MN4)以及第一电流发生器(MN5)和第二电流源(MN6)。 施加在第一电流发生器中的电流由零位处理单元提供给第一负载(R1)或第二杆(R2)。 共模置换(120)包括第三负载(R3),第四负载(R4)和第三电流圆(MN11)和共模控制器。 共模控制器包括第一输出共模控制器(MN7和MN8)和第二输出共模控制器(MN9和MN10)。
    • 4. 发明公开
    • 반도체 장치의 데이터 샘플링 회로
    • 半导体器件的数据采集电路
    • KR1020110002330A
    • 2011-01-07
    • KR1020090059866
    • 2009-07-01
    • 에스케이하이닉스 주식회사
    • 이지왕김용주한성우송희웅오익수김형수황태진최해랑장재민박창근
    • H03K7/02G11C27/02
    • H03K3/356139G06F5/06H03K3/0375
    • PURPOSE: A data sampling circuit of a semiconductor device is provided to perform a sampling operation by extending a pulse width of the inputted digital signal. CONSTITUTION: A first input unit(300) performs a sampling operation based on a clock signal by receiving a data signal. A second input unit(320) performs a sampling operation based on a clock signal by receiving a signal which is delayed corresponding to a data signal. An output unit outputs a sampling data signal by combining an output signal of the first input unit and the second input unit. The first input unit changes the logic level of the output signal in response to the logic level of the data. The first input unit changes the logic level of the output signal in response to the logic level of the data signal detected at a first edge of a clock signal. The first input unit prevents the change of the logic level of the output signal regardless of the logic level of the data signal detected at a second edge of the clock signal.
    • 目的:提供半导体器件的数据采样电路,通过扩展输入的数字信号的脉冲宽度来执行采样操作。 构成:第一输入单元(300)通过接收数据信号基于时钟信号执行采样操作。 第二输入单元(320)通过接收对应于数据信号延迟的信号,基于时钟信号执行采样操作。 输出单元通过组合第一输入单元和第二输入单元的输出信号来输出采样数据信号。 第一输入单元响应于数据的逻辑电平改变输出信号的逻辑电平。 第一输入单元响应于在时钟信号的第一个边沿处检测到的数据信号的逻辑电平来改变输出信号的逻辑电平。 无论在时钟信号的第二个边缘处检测到的数据信号的逻辑电平如何,第一输入单元防止输出信号的逻辑电平的改变。