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1. 发明公开

KR1020160123968A 고 분해능 시간-디지털 컨버터 审中-实审
标题翻译： - 高分辨率时间 - 数字转换器
公开(公告)号：KR1020160123968A
公开(公告)日：2016-10-26
申请号：KR1020150167888
申请日：2015-11-27
申请人： 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드
发明人： 초란초우 , 조우츈푸 , 쿠오펭웨이 , 첸후안넹
IPC分类号： G04F10/00 , H03M1/12 , H03L7/08
CPC分类号： G04F10/005 , H03K5/131 , H03K5/135 , H03K5/1534 , H03K5/24 , H03K2005/00058 , H03K2005/00071
摘要： 본발명에서는입력클록신호및 기준클록신호를수신하도록, 그리고델타펄스신호및 기준펄스신호를발생시키도록구성된시간델타검출기를포함하는회로가제공된다. 비교회로가델타펄스신호및 기준펄스신호를수신하도록구성된다. 그비교회로는입력클록신호와기준클록신호사이의시간차이의비트를나타내는출력을발생시킨다. 제어회로가그 비교회로로부터의출력을수신하도록구성된다. 그제어회로는입력클록신호와기준클록신호사이의시간차이의카운트를유지한다.
摘要翻译：一种电路包括时间差检测器，其被配置为接收输入时钟信号和参考时钟信号，并产生增量脉冲信号和参考脉冲信号。比较电路被配置为接收增量脉冲信号和参考脉冲信号。比较电路产生表示输入时钟信号和参考时钟信号之间的时间差的位的输出。控制电路被配置为接收来自比较电路的输出。控制电路维持输入时钟信号和参考时钟信号之间的时间差的计数。

2. 发明公开

KR1020090126596A 반도체 소자 失效
标题翻译：半导体器件
公开(公告)号：KR1020090126596A
公开(公告)日：2009-12-09
申请号：KR1020080052753
申请日：2008-06-04
申请人： 에스케이하이닉스 주식회사
发明人： 이지왕 , 박근우 , 김용주 , 송희웅 , 오익수 , 김형수 , 황태진 , 최해랑
IPC分类号： G11C7/10 , G11C8/00
CPC分类号： H04B3/32 , H03K5/131 , H03K5/135 , H03K5/1534 , H03K2005/00071 , H04L25/0272 , H04L25/0286 , H04L25/029
摘要： PURPOSE: A semiconductor device is provided to remove a skew, caused by crosstalk, efficiently by directly considering a cause of generation of the skew. CONSTITUTION: First and second transmission lines(4A,4B) are used to exchange signals. First and second signal transition detecting units(400,410) detects a transition form and a transition state corresponding to time of transmission signals loaded on the first and second transmission lines. A signal mode determining unit(420) determines a signal transmission mode formed between the neighboring first and second transmission lines in response to an output signal of the first and second signal transition detecting units. First and second delay units(430,440) are connected to each transmission line. The first and second delay units control transmission delay of the transmission signal according to an output signal of the signal mode determining unit.
摘要翻译：目的：提供半导体器件，通过直接考虑产生偏斜的原因，有效地消除由串扰引起的偏斜。构成：第一和第二传输线（4A，4B）用于交换信号。第一和第二信号转换检测单元（400,410）检测与加载在第一和第二传输线路上的传输信号的时间相对应的转换形式和转变状态。信号模式确定单元（420）响应于第一和第二信号转换检测单元的输出信号确定形成在相邻的第一和第二传输线之间的信号传输模式。第一和第二延迟单元（430,440）连接到每个传输线。第一和第二延迟单元根据信号模式确定单元的输出信号控制发送信号的发送延迟。

3. 发明公开

KR1020050055228A 컬럼 어드레스 선택 신호의 펄스 폭 제어 회로 有权
标题翻译：列地址选择信号的脉宽控制电路
公开(公告)号：KR1020050055228A
公开(公告)日：2005-06-13
申请号：KR1020030088283
申请日：2003-12-05
申请人： 에스케이하이닉스 주식회사
发明人： 박문필
IPC分类号： G11C11/40 , H03K5/04
CPC分类号： G11C7/222 , G11C7/1048 , G11C7/1072 , G11C2207/002 , H03K5/05 , H03K5/156 , H03K2005/00071
摘要： 본 발명은 펄스 폭 제어 회로에 관한 것으로, 외부 클럭을 입력하여 상기 외부 클럭을 서로 다른 시간으로 지연시킨 후 상기 외부 클럭의 주파수와 상기 서로 다른 시간으로 지연된 외부 클럭의 주파수를 각각 비교하여 동작 주파수 대역을 추출하고 그에 따른 다수의 모드 신호를 출력하기 위한 주파수 검출 회로와, 상기 주파수 검출 회로로부터 입력된 상기 다수의 모드 신호에 따른 지연 시간을 이용하여 동작 주파수에 따라 가변적인 폭을 갖는 펄스를 생성하기 위한 펄스 생성 회로로 구성되어 다양한 동작 주파수를 지원하는 고속 동작 그래픽용 DRAM 이외에 고속화되는 DDR2나 DDR3 차세대 범용 DRAM에서 적용할 수 있는 펄스 폭 제어 회로가 제시된다.

4. 发明授权

KR100405020B1 클럭 제어 방법 및 회로 失效
标题翻译： 클럭제어방법및회로
公开(公告)号：KR100405020B1
公开(公告)日：2003-11-07
申请号：KR1020010070349
申请日：2001-11-13
申请人： 르네사스 일렉트로닉스 가부시키가이샤
发明人： 사에끼다까노리
IPC分类号： H03K7/08
CPC分类号： H03K5/13 , G06F1/10 , G06F7/68 , H03K5/082 , H03K5/1504 , H03K2005/00065 , H03K2005/00071 , H03L7/00
摘要： A novel clock control circuit and method in which phase synchronization with respect to an external clock can be realized without recourse to the external clocks. A clock controlling circuit includes a delay circuit sequence comprised of N stages of units each made up of a first delay circuit 10 and a first interior division circuit 11 for delaying the output signal of the first delay circuit, and a phase difference detection circuit 14 for detecting the clock period and the delay time difference of the delay circuit sequence from the input clock IN and a clock END output by the delay circuit sequence as a phase difference of the two signals. A plural number of second interior division circuits 12, fed with an output signal of the first delay circuit, delays a transition edge of an output signal of the first delay circuit by t2-nxT/N to output the delayed signal. The second interior division circuit outputs a signal which makes transition at a timing delayed nxtCK/N as from the start time point of the clock cycle. A synthesis circuit 13 generates a frequency multiplied clock signal which is obtained on equal division of the clock period tCK of the input clock from the input clock IN and the number 1 to numberN-1 third delays circuit.
摘要翻译：一种新颖的时钟控制电路和方法，其中可以实现相对于外部时钟的相位同步，而不依靠外部时钟。时钟控制电路包括由N级单元组成的延迟电路序列，每个单元由第一延迟电路10和用于延迟第一延迟电路的输出信号的第一内部分频电路11组成，以及相位差检测电路14，用于从输入时钟IN检测延迟电路序列的时钟周期和延迟时间差以及由延迟电路序列输出的时钟END作为两个信号的相位差。被馈送第一延迟电路的输出信号的多个第二内部分割电路12将第一延迟电路的输出信号的转变边缘延迟t2-n×T / N以输出延迟的信号。第二内部分频电路从时钟周期的开始时间点输出一个信号，该信号在延迟nxtCK / N的定时处进行转换。合成电路13产生倍频时钟信号，该倍频时钟信号是在输入时钟的时钟周期tCK从输入时钟IN和数量1到数量N-1的第三延迟电路等分后获得的。

5. 发明公开

KR1020020037441A 클럭 제어 방법 및 회로 失效
标题翻译：时钟控制方法和时钟控制电路
公开(公告)号：KR1020020037441A
公开(公告)日：2002-05-21
申请号：KR1020010070349
申请日：2001-11-13
申请人： 르네사스 일렉트로닉스 가부시키가이샤
发明人： 사에끼다까노리
IPC分类号： H03K7/08
CPC分类号： H03K5/13 , G06F1/10 , G06F7/68 , H03K5/082 , H03K5/1504 , H03K2005/00065 , H03K2005/00071 , H03L7/00
摘要： PURPOSE: A clock controlling method and a clock control circuit are provided to generate multi-phase clocks phase-synchronized to an external clock and a frequency multiplied clock signal without recourse to a feedback system. CONSTITUTION: A clock control circuit includes a delay circuit sequence provided with a plurality number of cascaded stages of delay circuit units, each made up of a first circuit(101-10N) receiving an input signal to output the input signal with a first delay time and a second circuit receiving an output signal from the first circuit(101-10N) to output the signal with a second delay time, a phase difference detection circuit(14) receiving an input clock fed to the delay circuit sequence and an output clock output from the delay circuit sequence to detect a time difference between a clock period of the input clock and a delay time of the delay circuit sequence as a phase difference of the received two clocks and a plurality of third circuits(121-12N-1), each receiving an output signal of the first circuit(101-10N) of each of the delay circuit units to delay and output transition edge of the output signal of the first circuit(101-10N) with respective different delay time, depending on a stage number of the delay circuit unit to which belongs the first circuit(101-10N) in the delay circuit sequence, in terms of time obtained on equally dividing the phase difference by the number of the delay circuit units in the delay circuit sequence, as a unit, wherein the third circuits(121-12N-1) output a plurality of output signals which make transition at a time interval corresponding to equal division of the clock period of the input clock by the number of the delay circuit units in the delay circuit sequence.
摘要翻译：目的：提供时钟控制方法和时钟控制电路，以产生与外部时钟相位同步的多相时钟和频率相乘的时钟信号，而无需求助于反馈系统。构成：时钟控制电路包括具有多个级联级延迟电路单元的延迟电路序列，每个延迟电路单元由接收输入信号的第一电路（101-10N）构成，以输出具有第一延迟时间的输入信号以及第二电路，接收来自所述第一电路（101-10N）的输出信号以输出具有第二延迟时间的信号;相位差检测电路（14），接收馈送到所述延迟电路序列的输入时钟和输出时钟输出从所述延迟电路序列检测所述输入时钟的时钟周期与所述延迟电路序列的延迟时间之间的时间差作为所接收的两个时钟的相位差和多个第三电路（121-12N-1），每个接收每个延迟电路单元的第一电路（101-10N）的输出信号，以相应的不同的延迟时间来延迟和输出第一电路（101-10N）的输出信号的转移边沿，取决于在延迟电路序列中属于第一电路（101-10N）的延迟电路单元的级数，就延迟电路序列中的相位差乘以延迟电路单元数而获得的时间而言，为一个单元，其中所述第三电路（121-12N-1）输出多个输出信号，所述多个输出信号在与所述输入时钟的所述时钟周期的等分时间相对应的时间间隔内延迟所述延迟电路单元的数量电路顺序。

6. 发明公开

KR1020020011342A 지연 회로, 전압 제어 지연 회로, 전압 제어 발진회로, 지연 조정 회로, ＤＬＬ 회로 및 ＰＬＬ 회로 有权
标题翻译：延迟电路，电压控制延迟电路，电压控制振荡电路，延迟调节电路，DLL电路和PLL电路
公开(公告)号：KR1020020011342A
公开(公告)日：2002-02-08
申请号：KR1020010046297
申请日：2001-07-31
申请人： 소니 주식회사
发明人： 다치모리히로시
IPC分类号： H03L7/099
CPC分类号： H03K3/013 , H03K3/0315 , H03K5/133 , H03K2005/00039 , H03K2005/00065 , H03K2005/00071 , H03K2005/00195 , H03K2005/00202 , H03L7/0812 , H03L7/0893 , H03L7/0995
摘要： PURPOSE: To achieve an inverter type delay circuit, a voltage controlled oscillation circuit and a voltage controlled delay circuit with simple circuit configuration which can reduce the effect of power noise and jitter. CONSTITUTION: These circuits are so constituted that a driving current is controlled according to a bias voltage or a controlling voltage, that dependence of delay time of each delay stage on source voltage is suppressed by connecting a plurality of delay stages whose delay time is determined by the driving current, by adding the change in source voltage to the bias voltage or the controlling voltage at a predetermined ratio, and by supplying the result of the addition to each of the delay stage, and that a plurality of delay stages each of which has a different dependence on the source voltage, for example, the dependence whose delay time runs counter to each other, are connected at a prescribed ratio. Thus, the delay circuit, the voltage controlled delay circuit and the voltage controlled oscillation circuit which can suppress the dependence of the delay time of the whole delay circuit on source voltage can be achieved.
摘要翻译：目的：实现逆变器类型延迟电路，电压控制振荡电路和具有简单电路配置的电压控制延迟电路，可以降低功耗噪声和抖动的影响。构成：这些电路构成为根据偏置电压或控制电压来控制驱动电流，通过连接延迟时间由多个延迟时间确定的多个延迟级来抑制每个延迟级对源极电压的依赖性驱动电流，通过将源极电压的变化与预定比例的偏置电压或控制电压相加，并且通过将延迟结果提供给每个延迟级，并且多个延迟级分别具有与源极电压的不同依赖性，例如，延迟时间相互延迟的依赖关系以规定的比例连接。因此，可以实现可以抑制整个延迟电路的延迟时间对源电压的依赖性的延迟电路，电压控制延迟电路和压控振荡电路。

7. 发明公开

KR1020010063196A 씨모스 알씨 지연 회로 失效
标题翻译： CMOS RC延迟电路
公开(公告)号：KR1020010063196A
公开(公告)日：2001-07-09
申请号：KR1019990060186
申请日：1999-12-22
申请人： 에스케이하이닉스 주식회사
发明人： 홍병일
IPC分类号： H03K5/14
CPC分类号： H03K5/133 , H03K2005/00071
摘要： PURPOSE: A CMOS RC delay circuit is provided to minimize the number and capacitance of a capacitor in a circuit requiring many delays by performing RC delay using an inverter inverts an output signal from a resistive inverter and feedbacks to an input terminal. CONSTITUTION: A resistive inverter(RINV) has a resistive component, and inverts and outputs an input signal(VIN) to invert. An end of a capacitor(C1) is linked with a ground while the other end is linked with an output terminal of the resistive inverter(RINV). An inverter(INV1) inverts the output signal of the resistive inverter(RINV) and outputs to an input terminal of the resistive inverter(RINV). An inverter(INV2) inverts the output signal of the resistive inverter(RINV) and outputs an output signal(VOUT). Here, the resistive inverter(RINV) is linked with an inverter(INV3) and a resistor(R) in serial, respectively.
摘要翻译：目的：提供CMOS RC延迟电路，通过使用反相器执行RC延迟来反转来自电阻逆变器的输出信号并反馈到输入端子，从而最小化需要许多延迟的电路中的电容器的数量和电容。构成：电阻性反相器（RINV）具有电阻分量，并将输入信号（VIN）反相输出为反相。电容器（C1）的端部与接地连接，而另一端与电阻性逆变器（RINV）的输出端连接。逆变器（INV1）将电阻性逆变器（RINV）的输出信号反相，并输出到电阻性逆变器（RINV）的输入端子。反相器（INV2）使电阻性反相器（RINV）的输出信号反相，并输出输出信号（VOUT）。这里，电阻性逆变器（RINV）分别与逆变器（INV3）和电阻器（R）串联连接。

8. 发明公开

KR1020010048992A 전류 조절 인버터 딜레이 회로 无效
标题翻译：电流控制逆变器延迟电路
公开(公告)号：KR1020010048992A
公开(公告)日：2001-06-15
申请号：KR1019990053899
申请日：1999-11-30
申请人： 에스케이하이닉스 주식회사
发明人： 구철희
IPC分类号： H03K5/134
CPC分类号： G11C11/4076 , H03K5/133 , H03K2005/00071
摘要： PURPOSE: A current control inverter delay circuit is provided which connects a plurality of transistors to the first and second inverters to control current flowing the inverters, thereby adjusting a delay of output voltage and reducing layout area. CONSTITUTION: A current control inverter delay circuit includes the first inverter(100) for inverting an input signal, the second inverter(200) for inverting a signal from the first node of the first inverter that is an output port, and a controller(300) connected to the first and second inverters to control currents of the first and second inverters according to the input signal to adjust an output signal. The first inverter is configured of a CMOS transistor constructed in a manner that a PMOS(P101) transistor and an NMOS(N101) transistor are serially connected. The second inverter is configured of a CMOS transistor constructed in a manner that a PMOS(P201) transistor and an NMOS(P201) transistor are serially connected. The controller is configured of a delay for increasing the delay of output signal at the rising edge of the input signal.
摘要翻译：目的：提供一种电流控制逆变器延迟电路，其将多个晶体管连接到第一和第二逆变器，以控制流过逆变器的电流，从而调节输出电压的延迟并减少布局面积。电流控制逆变器延迟电路包括用于反转输入信号的第一反相器（100），用于反转来自作为输出端口的第一反相器的第一节点的信号的第二反相器（200）和控制器（300 ）连接到第一和第二逆变器以根据输入信号控制第一和第二反相器的电流以调整输出信号。第一反相器由以PMOS（P101）晶体管和NMOS（N101）晶体管串联连接的方式构成的CMOS晶体管构成。第二反相器由以PMOS（P201）晶体管和NMOS（P201）晶体管串联连接的方式构成的CMOS晶体管构成。该控制器被配置为在输入信号的上升沿增加输出信号的延迟的延迟。

9. 发明公开

KR1020000062161A 지연 디바이스, 반도체 시험장치, 반도체 디바이스, 및오실로스코프 失效
标题翻译：延迟器件半导体测试器件半导体器件和OSCILLOSCOPE
公开(公告)号：KR1020000062161A
公开(公告)日：2000-10-25
申请号：KR1019990050611
申请日：1999-11-15
申请人： 가부시키가이샤 아드반테스트
发明人： 오카야스도시유키 , 스다마사카쓰
IPC分类号： H03K5/14
CPC分类号： H03K5/13 , G01R31/31922 , H03K5/133 , H03K5/14 , H03K2005/00071
摘要： 본발명은입력된전송신호를지연하는지연디바이스에관한것으로, 2개의전원전압 V및 V(V>V)에의해구동되며입력된상기전송신호를지연하며직렬로접속된복수의지연소자, 및복수의지연소자의출력에대해전원전압 V보다크고전원전압 V보다작은소정의전압을출력하고지연소자의각 출력에대해각각접속한복수의부가회로를구비하며, 지연소자는입력된전압에대응하여 2치의출력전압중 어느하나를출력하는디지털회로를가지고, 부가회로가디지털회로의출력이 2치의출력전압중 한쪽에서다른쪽으로반전하는스레시홀드전압에거의일치하는전압을출력하는지연디바이스를제공한다.

10. 发明公开

KR1019990078357A 결정 문턱값을 제어함으로써 유도적으로 결합된 출력 신호 전이에 의해 발생되는 입력 신호 노이즈로부터의 보호를 위한 전자회로 및 그 방법 失效
标题翻译：通过控制决策阈值引起的感应耦合输出信号转换引起的信号噪声保护的电子电路及其方法
公开(公告)号：KR1019990078357A
公开(公告)日：1999-10-25
申请号：KR1019990010767
申请日：1999-03-29
申请人： 닛뽕덴끼 가부시끼가이샤
发明人： 미야노가즈따까
IPC分类号： H03K17/16
CPC分类号： H03K5/13 , H03K5/082 , H03K2005/00071 , H03M1/0827
摘要： 노이즈-면역 (noise-immune) 전자회로는입력전송라인을통하여입력신호를수신하며상기입력신호를결정문턱값과비교하여상기입력신호및 상기결정문턱값의상대적인크기에기초한 1개의소정이산레벨을가지는전자회로의입력데이터를발생시키는입력회로와상기전자회로의출력데이터를수신하며그로부터출력신호를발생시키며출력전송라인상으로상기출력신호를전송하는출력회로를포함한다. 상기입력및 출력전송라인은유도적으로함께결합되어상기전송된출력신호에전압전이가발생하는경우, 상기수신된입력신호에노이즈가도입된다. 상기입력회로의결정에러를방지하기위하여, 노이즈보호회로가제공되어, 상기입력신호에발생되는노이즈와일치하는시점에서상기결정문턱값을제어하는상기전자회로의출력데이터의전압전이에반응하여상기노이즈가존재하여도상기입력회로는결정에러를발생시키지않는다.

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