专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明公开

KR1020070057053A 반도체장치 有权
标题翻译：半导体器件
公开(公告)号：KR1020070057053A
公开(公告)日：2007-06-04
申请号：KR1020060119984
申请日：2006-11-30
申请人： 르네사스 일렉트로닉스 가부시키가이샤
发明人： 하야시타카히로 , 도요시마슌수케 , 사카모토카즈오 , 모리노나오즈미 , 다나카카즈오
IPC分类号： H01L23/48
CPC分类号： H01L23/49844 , H01L23/49811 , H01L23/50 , H01L23/5226 , H01L23/5286 , H01L23/53228 , H01L23/585 , H01L24/05 , H01L24/06 , H01L24/49 , H01L27/0255 , H01L27/092 , H01L2224/02166 , H01L2224/05025 , H01L2224/05093 , H01L2224/05095 , H01L2224/05124 , H01L2224/05624 , H01L2224/06102 , H01L2224/06133 , H01L2224/06143 , H01L2224/06153 , H01L2224/06163 , H01L2224/49105 , H01L2224/85399 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/12036 , H01L2924/1306 , H01L2924/14 , H01L2924/00 , H01L2224/05599 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： A semiconductor device is provided to improve the degree of integration without the increase of the size of the semiconductor device itself. A multiple metal line structure composed of a first power source line, a second power source line and a first metal line is formed on a semiconductor substrate(30). A bonding pad is formed on the first and the second power source lines. A first conductor layer is electrically connected to the bonding pad on the first and the second power source lines. A protection element is electrically connected with the bonding pad on the substrate. The first and the second power source lines cross over the protection element. The first line is electrically connected with the protection element to form a withdraw region(24) of the first metal line between the first and the second power source lines. The first metal line is withdrawn from a predetermined portion over the first and the second power source lines in the withdraw region.
摘要翻译：提供半导体器件以提高集成度而不增加半导体器件本身的尺寸。在半导体衬底（30）上形成由第一电源线，第二电源线和第一金属线构成的多重金属线结构。在第一和第二电源线上形成接合焊盘。第一导体层电连接到第一和第二电源线上的接合焊盘。保护元件与衬底上的接合焊盘电连接。第一和第二电源线跨过保护元件。第一线与保护元件电连接以在第一和第二电源线之间形成第一金属线的退避区域（24）。第一金属线从退出区域中的第一和第二电源线上的预定部分退出。

2. 发明公开

KR1020150112937A 반도체 집적 회로 审中-实审
标题翻译：半导体集成电路
公开(公告)号：KR1020150112937A
公开(公告)日：2015-10-07
申请号：KR1020157016900
申请日：2013-11-21
申请人： 소니 주식회사
发明人： 다나르도노드위안토노 , 사토마사히로
IPC分类号： H01L23/498 , H01L23/00 , H01L27/118
CPC分类号： H01L27/11898 , H01L22/32 , H01L23/49838 , H01L24/06 , H01L2224/05553 , H01L2224/06163 , H01L2224/48091 , H01L2224/49113 , H01L2224/49171 , H01L2924/00014
摘要： 반도체집적회로에서전압강하의증대를억제한다. 반도체집적회로는, 복수의제1의입출력셀과, 복수의제2의입출력셀과, 전위공급부를갖는다. 복수의제1의입출력셀은, 반도체집적회로기판상에배열된다. 복수의제2의입출력셀은, 복수의제1의입출력셀에따라반도체집적회로기판상에배열된다. 전위공급부는, 반도체패키지기판의표면내에서일부가돌출하여반도체패키지기판상에형성되고, 복수의제1의입출력셀의어느하나인대상셀과복수의제2의입출력셀 중대상셀의부근의셀에대해돌출한일부를포함하는영역을통하여소정의전위를공급한다.
摘要翻译：提供一种半导体集成电路，包括：布置在半导体集成电路基板上的多个第一输入/输出单元; 沿着所述多个第一输入/输出单元布置在所述半导体集成电路基板上的多个第二输入/输出单元; 以及形成在半导体封装基板上的电位供给部，所述电位供给部的一部分在所述半导体封装基板的表面突出，并且被配置为向作为所述多个第一输入/ 输出单元和与多个第二输入/输出单元之间的目标单元相邻的单元通过包括突出部分的区域。

3. 发明授权

KR101336355B1 반도체장치 有权
标题翻译：半导体器件
公开(公告)号：KR101336355B1
公开(公告)日：2013-12-04
申请号：KR1020060119984
申请日：2006-11-30
申请人： 르네사스 일렉트로닉스 가부시키가이샤
发明人： 하야시타카히로 , 도요시마슌수케 , 사카모토카즈오 , 모리노나오즈미 , 다나카카즈오
IPC分类号： H01L23/48
CPC分类号： H01L23/49844 , H01L23/49811 , H01L23/50 , H01L23/5226 , H01L23/5286 , H01L23/53228 , H01L23/585 , H01L24/05 , H01L24/06 , H01L24/49 , H01L27/0255 , H01L27/092 , H01L2224/02166 , H01L2224/05025 , H01L2224/05093 , H01L2224/05095 , H01L2224/05124 , H01L2224/05624 , H01L2224/06102 , H01L2224/06133 , H01L2224/06143 , H01L2224/06153 , H01L2224/06163 , H01L2224/49105 , H01L2224/85399 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/12036 , H01L2924/1306 , H01L2924/14 , H01L2924/00 , H01L2224/05599 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： [과제]반도체장치의 평면치수를 축소한다.
[해결수단]반도체기판(30)상에, 입출력회로(11)가 형성되며, 그 상부를 접지배선(7) 및 전원배선(8)이 지나고, 그 위에 본딩패드(4)용의 도체층(51)이 형성되어 있다.
입출력회로(11)는, n MISFET 형성영역(21) 및 p MISFET 형성영역(27)의 MISFET소자와, 보호소자로서 기능하는 저항소자 형성영역(22, 26)의 저항소자 및 다이오드 소자 형성영역(23, 25)의 다이오드 소자와에 의해 형성되어 있다. 이러한 보호소자에 접속된, 접지배선(7) 및 전원배선(8)보다 하층의 배선(53)은, n MISFET 형성영역(21)과 p MISFET 형성영역(27)의 사이이며 접지배선(7)과 전원배선(8) 사이의 인출영역(24)에서 인출되어 도체층(51)에 접속되어 있다.
본딩패드, 입출력소자

4. 发明授权

KR101106412B1 최적 와이어 접합 배치를 구비하는 반도체 패키지 有权
标题翻译：具有优化线束定位的半导体封装
公开(公告)号：KR101106412B1
公开(公告)日：2012-01-17
申请号：KR1020057023529
申请日：2004-06-07
申请人： 엔엑스피 유에스에이, 인코포레이티드
发明人： 웬젤,로버트,제이. , 하퍼,피터,알.
IPC分类号： H01L21/60
CPC分类号： H01L24/06 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/50 , H01L23/66 , H01L24/05 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2223/6611 , H01L2223/6616 , H01L2224/0401 , H01L2224/04042 , H01L2224/05001 , H01L2224/05082 , H01L2224/05554 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/06136 , H01L2224/0616 , H01L2224/06163 , H01L2224/32145 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45155 , H01L2224/4554 , H01L2224/4809 , H01L2224/48091 , H01L2224/48092 , H01L2224/48095 , H01L2224/4813 , H01L2224/48137 , H01L2224/48145 , H01L2224/48195 , H01L2224/48227 , H01L2224/48229 , H01L2224/48233 , H01L2224/48235 , H01L2224/4824 , H01L2224/48247 , H01L2224/48455 , H01L2224/48465 , H01L2224/48601 , H01L2224/48624 , H01L2224/48644 , H01L2224/48647 , H01L2224/48655 , H01L2224/48701 , H01L2224/48724 , H01L2224/48744 , H01L2224/48747 , H01L2224/48755 , H01L2224/48801 , H01L2224/48824 , H01L2224/48844 , H01L2224/48847 , H01L2224/48855 , H01L2224/4903 , H01L2224/49051 , H01L2224/49052 , H01L2224/49096 , H01L2224/49097 , H01L2224/4912 , H01L2224/4917 , H01L2224/49171 , H01L2224/49174 , H01L2224/49175 , H01L2224/49179 , H01L2224/49431 , H01L2224/854 , H01L2224/85401 , H01L2224/85424 , H01L2224/85444 , H01L2224/85447 , H01L2224/85455 , H01L2924/01013 , H01L2924/01015 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01047 , H01L2924/01079 , H01L2924/014 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/15313 , H01L2924/1532 , H01L2924/181 , H01L2924/19107 , H01L2924/30107 , H01L2924/3011 , H01L2924/00014 , H01L2924/00 , H01L2924/00012 , H01L2924/013 , H01L2924/00013
摘要： Closely-spaced bonding wires may be used in a variety of different packaging applications to achieve improved electrical performance. In one embodiment, two adjacent bonding wires within a wire grouping are closely-spaced if a separation distance D between the two adjacent wires is met for at least 50 percent of the length of the shorter of the two adjacent wires. In one embodiment, the separation distance D is at most two times a diameter of the wire having the larger diameter of the two adjacent wires. In another embodiment, the separation distance D is at most three times a wire-to-wire pitch between the two adjacent wires. Each wire grouping may include two of more closely-spaced wires. Wire groupings of closely-spaced bonding wires may be used to form, for example, power-signal-ground triplets, signal-ground pairs, signal-power pairs, or differential signal pairs or triplets.
摘要翻译：紧密间隔的接合线可用于各种不同的包装应用中，以实现改进的电气性能。在一个实施例中，如果两条相邻导线之间的间隔距离D达到两条相邻导线中较短的长度的至少50％，则导线组内的两个相邻接合线是紧密间隔的。在一个实施例中，分离距离D为具有两个相邻线的较大直径的线的直径的至多两倍。在另一个实施例中，分离距离D至少为两条相邻线之间的线对线间距的三倍。每个线分组可以包括两个更紧密间隔的导线。紧密间隔的接合线的电线组可以用于形成例如功率 - 信号 - 接地三联体，信号 - 接地对，信号 - 功率对或差分信号对或三元组。

5. 发明公开

KR20180029168A 표시 장치 审中-公开
标题翻译：显示设备
公开(公告)号：KR20180029168A
公开(公告)日：2018-03-20
申请号：KR20160116732
申请日：2016-09-09
IPC分类号： H01L27/32 , H01L51/52 , H05K1/11
CPC分类号： H01L27/1244 , H01L24/06 , H01L2224/06051 , H01L2224/06163 , H01L2224/06165 , H01L2224/06515
摘要： 본발명의일 실시예에따른표시장치는, 화상을표시하는표시영역및 상기표시영역의주변에위치하는패드영역을포함하는기판및 상기패드영역위에위치하며, 제1 방향을따라서로나란하게배열되는복수의제1 패드단자를포함하는제1 패드부를포함하며, 상기복수의제1 패드단자각각은, 상기제1 방향과제1 경사각도를이루는제1 열을따라배열되는복수의제1 연결패드단자, 상기복수의제1 연결패드단자와이격되며, 상기제1 방향과제2 경사각도를이루는제2 열을따라배열되는복수의제2 연결패드단자및 상기제1 열을따라상기복수의제1 연결패드단자중 인접한한 쌍의제1 연결패드단자사이에배치되며, 상기복수의제1 연결패드단자와다른층에배치되는제1 더미패드단자를포함할수 있다.
摘要翻译：显示装置包括基板和第一垫。基板包括显示图像的显示区域和显示区域外的焊盘区域。第一焊盘位于焊盘区域中，并且包括在第一方向上彼此平行延伸的第一焊盘端子。第一焊盘端子包括：第一连接焊盘端子，沿着与第一方向形成第一倾斜角的第一列布置; 第二连接焊盘端子，所述第二连接焊盘端子与所述第一连接焊盘端子间隔开并沿着与所述第一方向形成第二倾斜角的第二列布置; 以及沿第一列的第一连接焊盘端子中的一对相邻的第一连接焊盘端子之间的第一虚拟焊盘端子。第一虚拟焊盘端子和第一连接焊盘端子彼此处于不同的层中。

6. 发明公开

KR1020060020662A 최적 와이어 접합 배치를 구비하는 반도체 패키지 有权
标题翻译：具有优化线束定位的半导体封装
公开(公告)号：KR1020060020662A
公开(公告)日：2006-03-06
申请号：KR1020057023529
申请日：2004-06-07
申请人： 엔엑스피 유에스에이, 인코포레이티드
发明人： 웬젤,로버트,제이. , 하퍼,피터,알.
IPC分类号： H01L21/60
CPC分类号： H01L24/06 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/50 , H01L23/66 , H01L24/05 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2223/6611 , H01L2223/6616 , H01L2224/0401 , H01L2224/04042 , H01L2224/05001 , H01L2224/05082 , H01L2224/05554 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/06136 , H01L2224/0616 , H01L2224/06163 , H01L2224/32145 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45155 , H01L2224/4554 , H01L2224/4809 , H01L2224/48091 , H01L2224/48092 , H01L2224/48095 , H01L2224/4813 , H01L2224/48137 , H01L2224/48145 , H01L2224/48195 , H01L2224/48227 , H01L2224/48229 , H01L2224/48233 , H01L2224/48235 , H01L2224/4824 , H01L2224/48247 , H01L2224/48455 , H01L2224/48465 , H01L2224/48601 , H01L2224/48624 , H01L2224/48644 , H01L2224/48647 , H01L2224/48655 , H01L2224/48701 , H01L2224/48724 , H01L2224/48744 , H01L2224/48747 , H01L2224/48755 , H01L2224/48801 , H01L2224/48824 , H01L2224/48844 , H01L2224/48847 , H01L2224/48855 , H01L2224/4903 , H01L2224/49051 , H01L2224/49052 , H01L2224/49096 , H01L2224/49097 , H01L2224/4912 , H01L2224/4917 , H01L2224/49171 , H01L2224/49174 , H01L2224/49175 , H01L2224/49179 , H01L2224/49431 , H01L2224/854 , H01L2224/85401 , H01L2224/85424 , H01L2224/85444 , H01L2224/85447 , H01L2224/85455 , H01L2924/01013 , H01L2924/01015 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01047 , H01L2924/01079 , H01L2924/014 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/15313 , H01L2924/1532 , H01L2924/181 , H01L2924/19107 , H01L2924/30107 , H01L2924/3011 , H01L2924/00014 , H01L2924/00 , H01L2924/00012 , H01L2924/013 , H01L2924/00013
摘要： Closely-spaced bonding wires may be used in a variety of different packaging applications to achieve improved electrical performance. In one embodiment, two adjacent bonding wires within a wire grouping are closely-spaced if a separation distance D between the two adjacent wires is met for at least 50 percent of the length of the shorter of the two adjacent wires. In one embodiment, the separation distance D is at most two times a diameter of the wire having the larger diameter of the two adjacent wires. In another embodiment, the separation distance D is at most three times a wire-to-wire pitch between the two adjacent wires. Each wire grouping may include two of more closely-spaced wires. Wire groupings of closely-spaced bonding wires may be used to form, for example, power-signal-ground triplets, signal-ground pairs, signal-power pairs, or differential signal pairs or triplets.
摘要翻译：紧密间隔的接合线可用于各种不同的包装应用中，以实现改进的电气性能。在一个实施例中，如果两条相邻导线之间的间隔距离D达到两条相邻导线中较短的长度的至少50％，则导线组内的两个相邻接合线是紧密间隔的。在一个实施例中，分离距离D为具有两个相邻线的较大直径的线的直径的至多两倍。在另一个实施例中，分离距离D至少为两条相邻线之间的线对线间距的三倍。每个线分组可以包括两个更紧密间隔的导线。紧密间隔的接合线的电线组可以用于形成例如功率 - 信号 - 接地三联体，信号 - 接地对，信号 - 功率对或差分信号对或三元组。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式