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1. 发明授权

KR101336355B1 반도체장치 有权
标题翻译：半导体器件
公开(公告)号：KR101336355B1
公开(公告)日：2013-12-04
申请号：KR1020060119984
申请日：2006-11-30
申请人： 르네사스 일렉트로닉스 가부시키가이샤
发明人： 하야시타카히로 , 도요시마슌수케 , 사카모토카즈오 , 모리노나오즈미 , 다나카카즈오
IPC分类号： H01L23/48
CPC分类号： H01L23/49844 , H01L23/49811 , H01L23/50 , H01L23/5226 , H01L23/5286 , H01L23/53228 , H01L23/585 , H01L24/05 , H01L24/06 , H01L24/49 , H01L27/0255 , H01L27/092 , H01L2224/02166 , H01L2224/05025 , H01L2224/05093 , H01L2224/05095 , H01L2224/05124 , H01L2224/05624 , H01L2224/06102 , H01L2224/06133 , H01L2224/06143 , H01L2224/06153 , H01L2224/06163 , H01L2224/49105 , H01L2224/85399 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/12036 , H01L2924/1306 , H01L2924/14 , H01L2924/00 , H01L2224/05599 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： [과제]반도체장치의 평면치수를 축소한다.
[해결수단]반도체기판(30)상에, 입출력회로(11)가 형성되며, 그 상부를 접지배선(7) 및 전원배선(8)이 지나고, 그 위에 본딩패드(4)용의 도체층(51)이 형성되어 있다.
입출력회로(11)는, n MISFET 형성영역(21) 및 p MISFET 형성영역(27)의 MISFET소자와, 보호소자로서 기능하는 저항소자 형성영역(22, 26)의 저항소자 및 다이오드 소자 형성영역(23, 25)의 다이오드 소자와에 의해 형성되어 있다. 이러한 보호소자에 접속된, 접지배선(7) 및 전원배선(8)보다 하층의 배선(53)은, n MISFET 형성영역(21)과 p MISFET 형성영역(27)의 사이이며 접지배선(7)과 전원배선(8) 사이의 인출영역(24)에서 인출되어 도체층(51)에 접속되어 있다.
본딩패드, 입출력소자

2. 发明授权

KR101003118B1 Pad Structure of Semiconductor integrated circuit apparatus 无效
标题翻译：半导体集成电路设备的焊盘结构
公开(公告)号：KR101003118B1
公开(公告)日：2010-12-21
申请号：KR20080099558
申请日：2008-10-10
IPC分类号： H01L21/60
CPC分类号： H01L24/05 , H01L23/5226 , H01L23/585 , H01L24/45 , H01L24/48 , H01L2224/04042 , H01L2224/05093 , H01L2224/05095 , H01L2224/05556 , H01L2224/05599 , H01L2224/451 , H01L2224/48463 , H01L2224/85399 , H01L2924/00014 , H01L2924/01006 , H01L2924/01023 , H01L2924/01033 , H01L2924/01047 , H01L2924/14 , H01L2224/45099 , H01L2924/00
摘要： A pad structure of a semiconductor integrated circuit apparatus includes a semiconductor substrate upon which circuit patterns forming a device are disposed, a pad disposed on an uppermost part of the semiconductor substrate, and a plurality of fixing parts, each disposed along opposing edge portions of the pad to fix the pad and the semiconductor substrate to each other.

3. 发明公开

KR1020080029659A 반도체 소자의 패드 및 이의 제조 방법 无效
标题翻译：半导体器件的制造方法及其制造方法
公开(公告)号：KR1020080029659A
公开(公告)日：2008-04-03
申请号：KR1020060096534
申请日：2006-09-29
申请人： 에스케이하이닉스 주식회사
发明人： 이효석 , 구자춘 , 김찬배
IPC分类号： H01L21/60
CPC分类号： H01L24/05 , H01L24/03 , H01L2224/04042 , H01L2224/05093 , H01L2224/05095 , H01L2224/451 , H01L2224/48 , H01L2224/48463 , H01L2924/01006 , H01L2924/01014 , H01L2924/01019 , H01L2924/01033 , H01L2924/01082 , H01L2924/19041 , H01L2924/00014 , H01L2224/05556 , H01L2924/00 , H01L2924/00012
摘要： A pad of a semiconductor device and a manufacturing method thereof are provided to improve operation reliability of a wire bonding process by suppressing a peel-off phenomenon of a pad structure. A pad of a semiconductor device includes a semiconductor substrate, a first metal line(110), a first insulation film(130), a second metal line(150), a second insulation film(170), a metal plug(210), and a third metal line(220). The first metal line is formed on the semiconductor substrate. A planarization is performed on the first insulation film, which covers the first metal line. The second metal line is formed in a line shape on the first insulation film. The planarized second insulation film is formed on the first insulation film to cover the second metal line. The metal plug is formed to be contacted with the second metal line in the second insulation film. The third metal line is formed on the second insulation film, which contains the metal plug, and has a pad-like shape.
摘要翻译：提供一种半导体器件的焊盘及其制造方法，以通过抑制焊盘结构的剥离现象来提高引线接合工艺的操作可靠性。半导体器件的焊盘包括半导体衬底，第一金属线（110），第一绝缘膜（130），第二金属线（150），第二绝缘膜（170），金属插塞（210）和第三金属线（220）。第一金属线形成在半导体衬底上。在覆盖第一金属线的第一绝缘膜上进行平坦化。第二金属线在第一绝缘膜上形成为线状。平面化的第二绝缘膜形成在第一绝缘膜上以覆盖第二金属线。金属插塞形成为与第二绝缘膜中的第二金属线接触。第三金属线形成在包含金属插塞的第二绝缘膜上，并且具有垫状形状。

4. 发明公开

KR20070098405A SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：KR20070098405A
公开(公告)日：2007-10-05
申请号：KR20060071347
申请日：2006-07-28
申请人： FUJITSU LTD
发明人： SAITOU NOBUKATSU , UNO TADASHI , KANO MASASHI , MATSUOKA YOSHIHIRO
IPC分类号： H01L21/60
CPC分类号： H01L24/05 , H01L23/293 , H01L23/3192 , H01L24/03 , H01L24/13 , H01L2224/02166 , H01L2224/0345 , H01L2224/03912 , H01L2224/0401 , H01L2224/05012 , H01L2224/05086 , H01L2224/05095 , H01L2224/05124 , H01L2224/05571 , H01L2224/05573 , H01L2224/05666 , H01L2224/1146 , H01L2224/1147 , H01L2224/11849 , H01L2224/131 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/15787 , H01L2924/3025 , H01L2924/351 , H01L2924/00014 , H01L2924/01014 , H01L2224/05552 , H01L2924/00
摘要： A semiconductor device and a manufacturing method thereof are provided to improve the operation reliability of the semiconductor device by preventing a wiring layer or a conductive layer from being peeled off from a semiconductor substrate. A semiconductor device includes a semiconductor substrate, a wiring layer(14), a first conductive layer(15), an interlayer dielectric(16), and a second conductive layer(17). The wiring layer is formed on the semiconductor substrate. The first conductive layer is formed on the wiring layer. The interlayer dielectric is formed on the first conductive layer. The second conductive layer is formed on the interlayer dielectric such that the second conductive layer is connected to the first conductive layer. The first and second conductive layers are connected with each other through plural via-holes which are formed to penetrate the interlayer dielectric.
摘要翻译：提供半导体器件及其制造方法，以通过防止布线层或导电层从半导体衬底剥离来提高半导体器件的操作可靠性。半导体器件包括半导体衬底，布线层（14），第一导电层（15），层间电介质（16）和第二导电层（17）。布线层形成在半导体基板上。第一导电层形成在布线层上。层间电介质形成在第一导电层上。第二导电层形成在层间电介质上，使得第二导电层连接到第一导电层。第一和第二导电层通过形成为穿透层间电介质的多个通孔相互连接。

5. 发明授权

KR100741910B1 SEMICONDUCTOR CHIP INCLUDING AN ENHANCED STRUCTURAL STRENGTH OF CHIP PAD STRUCTURE 无效
标题翻译：半导体芯片，包括芯片结构的增强结构强度
公开(公告)号：KR100741910B1
公开(公告)日：2007-07-16
申请号：KR20060068719
申请日：2006-07-21
申请人： DONGBU ELECTRONICS CO LTD
发明人： KIM JIN HAN
IPC分类号： H01L23/48 , H01L21/60
CPC分类号： H01L24/05 , H01L21/76838 , H01L24/03 , H01L24/48 , H01L2224/04042 , H01L2224/05093 , H01L2224/05095 , H01L2224/05553 , H01L2224/05556 , H01L2224/05599 , H01L2224/48091 , H01L2224/48463 , H01L2224/85399 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01033 , H01L2924/01082 , H01L2924/12043 , H01L2924/13091 , H01L2924/19043 , H01L2224/45099 , H01L2924/00
摘要： A semiconductor chip having a chip pad structure with improved structural strength is provided to increase the structural strength of an interlayer dielectric with respect to the external weight applied to a conductive pad by forming a contact plug and a metal interconnection layer under a peripheral part of the conductive pad and by interconnecting a plurality of interlayer dielectrics through a center part of the pad. A semiconductor device is formed on a semiconductor substrate(Sub). The semiconductor device is electrically connected by a plurality of metal interconnection layers(M1,M2). A plurality of interlayer dielectrics are interposed between the semiconductor device and the metal interconnection layer and between the plurality of metal interconnection layers. A conductive pad is formed on the uppermost interlayer dielectric, electrically connected to an external circuit. The conductive pad is defined as a pad center part(220) and a pad peripheral part(240). At least one of the plurality of metal interconnection layers are formed under the conductive pad overlaps the lower part of the pad peripheral part except the pad center part. Two interlayer dielectrics formed in the upper and lower portions of the metal interconnection layer formed under the pad peripheral part are interconnected through the lower region of the pad center part. The metal interconnection layer formed in the pad peripheral part can be disposed in the uppermost layer of the plurality of metal interconnection layers.
摘要翻译：提供了具有改进的结构强度的芯片焊盘结构的半导体芯片，以通过在接触插塞和金属互连层的周边部分之下形成接触插塞和金属互连层来增加层间电介质相对于施加到导电焊盘的外部重量的结构强度并且通过将多个层间电介质通过焊盘的中心部分互连。半导体器件形成在半导体衬底（Sub）上。半导体器件通过多个金属互连层（M1，M2）电连接。在半导体器件和金属互连层之间以及多个金属互连层之间插入多个层间电介质。导电焊盘形成在最上层的层间电介质上，与外部电路电连接。导电焊盘被定义为焊盘中心部分（220）和焊盘周边部分（240）。多个金属互连层中的至少一个形成在导电垫之下，与衬垫中心部分以外的垫周边部分的下部重叠。形成在焊盘周边部分下方的金属互连层的上部和下部形成的两个层间电介质通过焊盘中心部分的下部区域相互连接。形成在焊盘周边部分中的金属互连层可以设置在多个金属互连层的最上层中。

6. 发明公开

KR1020030022017A 반도체 장치 및 그 제조 방법 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：KR1020030022017A
公开(公告)日：2003-03-15
申请号：KR1020020037597
申请日：2002-06-29
申请人： 후지쯔 가부시끼가이샤
发明人： 와따나베겐이찌
IPC分类号： H01L21/3205
CPC分类号： H01L24/03 , H01L21/76801 , H01L21/76802 , H01L21/76808 , H01L24/05 , H01L24/48 , H01L24/85 , H01L2224/02126 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05006 , H01L2224/05073 , H01L2224/05093 , H01L2224/05095 , H01L2224/05187 , H01L2224/05546 , H01L2224/05624 , H01L2224/05647 , H01L2224/48453 , H01L2224/48463 , H01L2224/85 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01022 , H01L2924/01029 , H01L2924/01038 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/01013 , H01L2224/78 , H01L2224/45099 , H01L2924/00
摘要： PURPOSE: To provide a manufacturing method of a semiconductor device having pad structure by which excessive current concentration in a pad can be suppressed. CONSTITUTION: A layer insulation film composed of insulation material is formed on a semiconductor substrate. An in-layer insulation film composed of insulation material is formed on the layer insulation film. A recess part is formed at the in-layer insulation film. The recess part includes a pad part 27 and a wiring part 25 connected with the pad part, which is larger than the width of the wiring part. A plurality of projection parts 21a are left in the pad part. The projection parts are arranged so that the area ratio of the recess part in a region 27b overlapped with a region obtained by extending the wiring part into the pad part among a first frame-like region 27a with the outer periphery of the pad part as an outer periphery line is larger than the area ratio of the recess part in a second frame-like area 27c with the inner peripheral line of the first frame-like region as an outer peripheral line. In order to embed the inside of the recess part, a conductive film is formed on the semiconductor substrate. The upper layer part of the conductive film is removed to form a first pad composed of a first film remaining in the recess part.
摘要翻译：目的：提供具有衬垫结构的半导体器件的制造方法，通过该衬垫结构可以抑制焊盘中的过大的电流集中。构成：在半导体基板上形成由绝缘材料构成的层间绝缘膜。在绝缘膜上形成由绝缘材料构成的层间绝缘膜。在层间绝缘膜上形成凹部。凹部包括焊盘部分27和与焊盘部分连接的布线部分25，其大于布线部分的宽度。多个突起部21a留在垫部中。突出部被布置成使得区域27b中的凹部的面积比与第一框状区域27a中的布线部分延伸到焊盘部分中获得的区域重叠，其中焊盘部分的外周为外周线大于作为外周线的第一框状区域的内周线的第二框状区域27c中的凹部的面积比。为了嵌入凹部的内部，在半导体基板上形成导电膜。去除导电膜的上层部分以形成由残留在凹部中的第一膜组成的第一焊盘。

7. 发明公开

KR1020020063015A 반도체 소자의 본딩 패드 구조 및 그 제조방법 有权
标题翻译：半导体器件的结合焊盘结构及其制造方法
公开(公告)号：KR1020020063015A
公开(公告)日：2002-08-01
申请号：KR1020010003677
申请日：2001-01-26
申请人： 삼성전자주식회사
发明人： 김현철
IPC分类号： H01L21/60
CPC分类号： H01L24/03 , H01L24/05 , H01L24/11 , H01L2224/02166 , H01L2224/0401 , H01L2224/05095 , H01L2224/05558 , H01L2224/05559 , H01L2224/05624 , H01L2224/05647 , H01L2224/13099 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/19041 , H01L2924/19043 , H01L2924/00014
摘要： PURPOSE: A bonding pad structure is provided to increase a step coverage of the bonding pad without additional processes by respectively forming an insulating layer on a first metal pad and a P-poly pattern. CONSTITUTION: A bonding pad structure comprises a semiconductor substrate(100), a first interlayer dielectric(102) formed on the semiconductor substrate(100), a P-poly pattern(104) formed on a pad formation region on the first interlayer dielectric(102), a second interlayer dielectric(106) formed on the P-poly pattern(104) and the first interlayer dielectric(102), a first metal pad(108) having a smaller size than the P-poly pattern(104) formed on the second interlayer dielectric(106), a third interlayer dielectric(110) formed on the first metal pad(108) and the second interlayer dielectric(106), a second metal pad(112) formed on the resultant structure so as to be directly connected to the first metal pad(108) and the P-poly pattern(104) through via holes and a protection layer(114) for exposing a defined region of the second metal pad(112).
摘要翻译：目的：提供焊盘结构，以通过在第一金属焊盘和P-poly图案上分别形成绝缘层来增加焊盘的台阶覆盖，而无需附加工艺。构成：焊盘结构包括半导体衬底（100），形成在半导体衬底（100）上的第一层间电介质（102），形成在第一层间电介质上的焊盘形成区域上的P多晶型（104） 102），形成在P多晶型（104）和第一层间电介质（102）上的第二层间电介质（106），具有比形成的P多晶型（104）小的尺寸的第一金属焊盘（108）在第二层间电介质（106）上形成在第一金属焊盘（108）和第二层间电介质（106）上的第三层间电介质（110），形成在所得结构上的第二金属焊盘（112）通过通孔和用于暴露第二金属焊盘（112）的限定区域的保护层（114）直接连接到第一金属焊盘（108）和P多晶型（104）。

8. 发明授权

KR100329407B1 반도체 소자의 전극 구조 失效
标题翻译：半导体元件的电极结构
公开(公告)号：KR100329407B1
公开(公告)日：2002-03-25
申请号：KR1019990056541
申请日：1999-12-10
申请人： 닛뽕덴끼 가부시끼가이샤
发明人： 기다쓰요시 , 오야찌겐지
IPC分类号： H01L21/60 , H01L21/28
CPC分类号： H01L24/48 , H01L24/03 , H01L24/05 , H01L24/45 , H01L24/78 , H01L2224/02166 , H01L2224/04042 , H01L2224/05093 , H01L2224/05095 , H01L2224/05096 , H01L2224/05553 , H01L2224/05624 , H01L2224/45015 , H01L2224/45144 , H01L2224/45147 , H01L2224/48463 , H01L2224/48624 , H01L2224/48824 , H01L2224/78301 , H01L2224/85205 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01029 , H01L2924/01039 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/00014 , H01L2924/00 , H01L2924/00015
摘要： 본발명은반도체소자의전극구조에관한것으로, 반도체칩의일주표면상에형성되는배선 (14), 배선 (14) 상에형성되는절연막 (15), 절연막 (15) 상에소정위치에설치되는 1 개이상의패드 (3) 및절연막 (15) 내에형성되는비어-홀 (16) 을포함하는반도체소자의전극구조를제공한다. 비어-홀 (16) 은배선 (14) 을패드 (3) 에전기적으로접속시키기위하여금속물질로채워지며비어-홀 (16) 과패드 (3) 간의접촉면적은비어-홀 (16) 측의패드 (3) 표면적의 3 (%) 이상이다. 그러한구조에의해, 본딩배선 (18) 이패드 (3) 에접속되는시간동안에, 절연막 (15) 의파단및 균열의발생을방지하는것이가능하게되므로, 제조수율을향상하게된다.
摘要翻译：半导体元件的电极结构包括形成在半导体芯片的一个主表面上的布线14，形成在布线14上的绝缘膜15，位于绝缘膜15上的预定位置的至少一个焊盘3，形成在绝缘膜15中的孔16.通孔16填充有用于将布线14电连接到焊盘3的金属材料，并且通孔16和焊盘3之间的接触面积为3％以上通孔16一侧的焊盘3的表面积。利用这种结构，可以在将接合线18连接到绝缘膜15的时间期间限制绝缘膜15的断裂和/或裂纹的发生垫3，从而提高制造成品率。

9. 发明授权

KR100926406B1 반도체 장치 失效
公开(公告)号：KR100926406B1
公开(公告)日：2009-11-12
申请号：KR1020080095983
申请日：2008-09-30
申请人： 세이코 엡슨 가부시키가이샤
发明人： 신도아끼노리 , 다가끼마사또시 , 구리따히데아끼
IPC分类号： H01L21/60
CPC分类号： H01L24/05 , H01L2224/05093 , H01L2224/05095 , H01L2224/05624 , H01L2224/05647 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/13091 , H01L2924/19043 , H01L2924/00014 , H01L2924/00
摘要： 패드의 하방에 반도체 소자를 형성할 수 있어, 신뢰성이 높은 반도체 장치를 제공한다. 본 발명의 반도체 장치는, 소자 형성 영역(10A)과 그 소자 형성 영역(10A)의 주위에 형성된 소자 분리 영역(20)을 갖는 반도체층(10)과, 상기 소자 형성 영역(10A) 내에 형성된 소자(30)와, 상기 반도체층(10)의 상방에 형성된 층간 절연층(60)과, 상기 층간 절연층(60)의 상방에 형성되고, 평면 형상이 짧은 변과 긴 변을 갖는 직사각형인 전극 패드(62)로서, 상기 소자(30)와 평면에서 보아 적어도 일부가 중복되는 상기 전극 패드(62)를 포함하고，상기 반도체층(10)에서，상기 전극 패드(62)의 상기 짧은 변의 연직 하방으로부터 외측에 위치하는 소정의 범위는, 소자 금지 영역(12)이다.
전극 패드, 소자, 패시베이션층, 트랜지스터

10. 发明授权

KR100916721B1 반도체 장치 失效
标题翻译：半导体器件
公开(公告)号：KR100916721B1
公开(公告)日：2009-09-14
申请号：KR1020070108698
申请日：2007-10-29
申请人： 세이코 엡슨 가부시키가이샤
发明人： 신도아끼노리 , 다가끼마사또시 , 구리따히데아끼
IPC分类号： H01L21/60
CPC分类号： H01L24/05 , H01L2224/05093 , H01L2224/05095 , H01L2224/05624 , H01L2224/05647 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/13091 , H01L2924/19043 , H01L2924/00014 , H01L2924/00
摘要： 패드의 하방에 반도체 소자를 형성할 수 있어, 신뢰성이 높은 반도체 장치를 제공한다. 본 발명의 반도체 장치는, 소자 형성 영역(10A)과 그 소자 형성 영역(10A)의 주위에 형성된 소자 분리 영역(20)을 갖는 반도체층(10)과, 상기 소자 형성 영역(10A) 내에 형성된 소자(30)와, 상기 반도체층(10)의 상방에 형성된 층간 절연층(60)과, 상기 층간 절연층(60)의 상방에 형성되고, 평면 형상이 짧은 변과 긴 변을 갖는 직사각형인 전극 패드(62)로서, 상기 소자(30)와 평면에서 보아 적어도 일부가 중복되는 상기 전극 패드(62)를 포함하고，상기 반도체층(10)에서，상기 전극 패드(62)의 상기 짧은 변의 연직 하방으로부터 외측에 위치하는 소정의 범위는, 소자 금지 영역(12)이다.
전극 패드, 소자, 패시베이션층, 트랜지스터
摘要翻译：可以在焊盘下方形成半导体器件，由此提供高度可靠的半导体器件。根据本发明的半导体器件包括：半导体层10，其具有形成在元件形成区域10A周围的元件形成区域10A和元件隔离区域20; 30，在层间绝缘层60，边和长边与平板状的短的上方形成具有层间绝缘的半导体层10的上方形成层60为长方形的电极焊盘（62），其在平面图中包括与所述元件（30）重叠的所述电极焊盘（62）的至少一部分，其中在所述半导体层（10）中，位于外侧的预定范围是器件禁止区域12。

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