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1. 发明授权

KR1019900003026B1 접합단락형 반도체 프로그래머블 리드온리 메모리 失效
标题翻译： JUNCTION SHORT TYPE SEMICONDUCTOR可编程只读存储器
公开(公告)号：KR1019900003026B1
公开(公告)日：1990-05-04
申请号：KR1019860009897
申请日：1986-11-24
申请人： 후지쯔 가부시끼가이샤
发明人： 후꾸시마도시다까
IPC分类号： G11C17/00
CPC分类号： G11C17/06 , H01L21/743 , H01L21/76224 , H01L21/8229 , H01L27/1026
摘要： The junction-shorting type PROM, includes transistors with a highly doped region of the same conductivity type as the base provided between a pair of memory cells. The region is a base contact which commonly connects paired bases at a surface terminal connected to a word line. The base contact region also extends into the substrate, which is a collector, and prevents any influence of minority carries in each of the paired bases from diffusing into an adjacent base. The base contact region is isolated from emitter regions by a narrow groove filled with insulation material. The narrow groove is deeper than the emitter regions but shallower than the substrate. A memory cell block formed from the paired cells and the base contact narrow isolation grooves and the elimination of a buried base layer reduce stray capacitance and increase the current amplification.
摘要翻译：结短路型PROM包括具有与设置在一对存储单元之间的基极相同导电类型的高掺杂区域的晶体管。该区域是在连接到字线的表面端子处共同连接成对的基底的基部接触件。基极接触区域也延伸到作为集电极的衬底中，并且防止每个成对碱基中的少数载体的任何影响扩散到相邻的基底中。基极接触区域通过填充有绝缘材料的窄沟槽与发射极区域隔离。窄槽比发射极区域深，但比衬底浅。由成对电池形成的存储单元块和基极接触窄隔离槽以及消除埋入的基极层降低杂散电容并增加电流放大。

2. 发明公开

KR1020130078135A 반도체 메모리 소자의 베리어막 패턴 제조방법 및 그 구조 无效
标题翻译：半导体存储器件的阻挡层图案制造方法及其结构
公开(公告)号：KR1020130078135A
公开(公告)日：2013-07-10
申请号：KR1020110146912
申请日：2011-12-30
申请人： 에스케이하이닉스 주식회사
发明人： 정하창
IPC分类号： H01L21/027 , H01L21/8229 , H01L27/10
CPC分类号： H01L21/32139 , H01L21/31122 , H01L21/31138 , H01L21/0274 , G03F1/38 , H01L21/0337 , H01L21/8229 , H01L27/101
摘要： PURPOSE: A method for manufacturing a barrier layer pattern of a semiconductor memory device and a structure thereof are provided to easily form a micro pattern by forming an upper area which is larger than a lower area. CONSTITUTION: A material layer (102) is deposited on the upper part of a semiconductor substrate. The material layer is etched to form a micro pattern. A barrier layer (104) is deposited on the upper part of the material layer. A photoresist pattern (108) is formed on the upper part of the barrier layer. An etching process is performed on the semiconductor substrate.
摘要翻译：目的：提供一种用于制造半导体存储器件的阻挡层图案的方法及其结构，以通过形成大于下部区域的上部区域来容易地形成微图案。构成：材料层（102）沉积在半导体衬底的上部。蚀刻材料层以形成微图案。阻挡层（104）沉积在材料层的上部。在阻挡层的上部形成有光致抗蚀剂图案（108）。在半导体衬底上进行蚀刻处理。

3. 发明公开

KR1020120068338A 반도체 장치 및 그 제조 방법 无效
标题翻译：半导体器件及其制造方法
公开(公告)号：KR1020120068338A
公开(公告)日：2012-06-27
申请号：KR1020100129924
申请日：2010-12-17
申请人： 에스케이하이닉스 주식회사
发明人： 오기준
IPC分类号： H01L21/8229 , H01L21/336 , H01L29/78
CPC分类号： H01L27/10894 , H01L21/8229 , H01L27/10823 , H01L29/4236
摘要： PURPOSE: A semiconductor device and a manufacturing method thereof are provided to prevent the deformation of a contact hole by reducing interface resistance between a landing plug and a contact. CONSTITUTION: A landing plug(142) covering a certain region between second gate patterns is formed on a substrate in a cell region. A first gate pattern is formed on another substrate in a peripheral circuit region. A first insulating layer(170) is formed on an outcome on which the first and the second gate patterns and the landing plug are formed. The first insulating layer is removed from the cell region. A second insulating layer(190) having a lower wet etching rate than the first insulating layer is formed on a space from which the first insulating layer is removed. A contact hole to expose the landing plug is formed by selectively etching the second insulating layer.
摘要翻译：目的：提供半导体器件及其制造方法，以通过降低着陆插头和触点之间的界面电阻来防止接触孔的变形。构成：在单元区域中的基板上形成覆盖第二栅极图案之间的特定区域的着陆塞（142）。在外围电路区域的另一基板上形成第一栅极图案。第一绝缘层（170）形成在其上形成有第一和第二栅极图案和着陆塞的结果上。第一绝缘层从电池区域移除。在除去第一绝缘层的空间上形成具有比第一绝缘层低的湿蚀刻速率的第二绝缘层（190）。通过选择性地蚀刻第二绝缘层来形成用于暴露着陆塞的接触孔。

4. 发明公开

KR1020160038145A 메모리 장치 및 그 제조 방법 审中-实审
标题翻译：存储器件及其制造方法
公开(公告)号：KR1020160038145A
公开(公告)日：2016-04-07
申请号：KR1020140130121
申请日：2014-09-29
申请人： 삼성전자주식회사
发明人： 윤태환 , 이준희 , 김지영
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L27/1157 , H01L21/8221 , H01L21/8229 , H01L27/11582 , H01L27/11521 , H01L27/11524
摘要： 본발명의실시형태에따른메모리장치는, 기판의상면에수직하는방향으로연장되는채널영역, 상기채널영역에인접하도록상기기판상에적층되어적어도하나의접지선택트랜지스터, 적어도하나의스트링선택트랜지스터, 및복수의메모리셀 트랜지스터를제공하는복수의게이트전극층, 상기기판의상면에수직하는방향으로연장되어상기복수의게이트전극층을복수의단위셀 영역으로분할하는복수의분리영역, 및각각의상기단위셀 영역내에서, 상기복수의게이트전극층중에서적어도하나의접지선택트랜지스터및 적어도하나의스트링선택트랜지스터를제공하는게이트전극층각각을복수개로분할하는적어도하나의분리절연막을포함한다.
摘要翻译：本发明涉及一种存储装置。根据本发明的实施例的存储器件包括：从衬底的上表面沿垂直方向延伸的沟道区; 多个栅极，提供堆叠在所述衬底上的与所述沟道区相邻的至少一个接地选择晶体管，至少一个串选择晶体管和多个存储单元晶体管; 多个分离区域从基板的上表面延伸并将栅电极层分离成多个单元区域; 以及至少一个分离绝缘膜，其将提供接地选择晶体管的栅极电极层和栅极电极层的串选择晶体管分成多个单位区域中的多层。

5. 发明公开

KR1020130140671A 평탄한 실리콘 함유막 审中-实审
标题翻译：含有薄膜的薄膜
公开(公告)号：KR1020130140671A
公开(公告)日：2013-12-24
申请号：KR1020137009445
申请日：2011-08-09
申请人： 노벨러스 시스템즈, 인코포레이티드
发明人： 폭스키스 , 니우동 , 워맥조 , 스리람만디암 , 안토넬리조지앤드류 , 판슈라벤디크바르트 , 올러프린제니퍼
IPC分类号： H01L21/205
CPC分类号： C23C16/505 , C23C16/24 , C23C16/345 , C23C16/402 , C23C16/4401 , C23C16/45523 , C23C16/509 , C23C16/54 , H01L21/02104 , H01L21/02123 , H01L21/02129 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/02211 , H01L21/02263 , H01L21/02274 , H01L21/0245 , H01L21/02507 , H01L21/02532 , H01L21/0254 , H01L21/6719 , H01L21/67201 , H01L21/67207 , H01L21/8229
摘要： 초평탄 실리콘 함유막들 및 막 스택들을 위한 방법들 및 하드웨어가 개시된다. 일 예에 있어서, 플라즈마 강화 화학기상증착 장치에서 기판 상에 실리콘 함유막을 성막하는 방법의 일 실시형태가 개시되며, 방법은 플라즈마 강화 화학기상증착 장치에 실리콘 함유 반응물을 공급하는 단계; 플라즈마 강화 화학기상증착 장치에 공반응물을 공급하는 단계; 플라즈마 강화 화학기상증착 장치의 프로세스 스테이션에 용량 결합형 플라즈마를 공급하는 단계로서, 플라즈마는 실리콘 함유 반응물로부터 발생된 실리콘 라디칼들 및 공반응물로부터 발생된 공반응물 라디칼들을 포함하는, 용량 결합형 플라즈마를 공급하는 단계; 및 기판 상에 실리콘 함유막을 성막하는 단계를 포함하고, 실리콘 함유막은 1.4 내지 2.1 의 굴절률을 가지며, 실리콘 함유막은 또한 실리콘 기판 상에서 측정될 때 4.5 이하의 절대 조도를 갖는다.

6. 发明公开

KR1020100083511A 유기 발광 소자, 그 구동 방법, 및 상기 유기 발광 소자를 포함하는 디스플레이 장치 有权
标题翻译：有机发光显示器及其操作方法及包括其的显示装置
公开(公告)号：KR1020100083511A
公开(公告)日：2010-07-22
申请号：KR1020090002929
申请日：2009-01-14
申请人： 단국대학교 산학협력단
发明人： 이준엽 , 전순옥 , 육경수 , 주철웅
IPC分类号： H05B33/22 , H01L51/50 , H01L51/54
CPC分类号： H01L51/5203 , H01L21/02601 , H01L21/8229 , H01L39/121 , H01L51/5012
摘要： PURPOSE: By using the memory layer included within the organic light-emitting device, the display device for including the organic light-emitting device, and the driving method and organic light-emitting device drives. The aperture ratio is improved since not including transistor. CONSTITUTION: The first electrode(2a) and the second electrode(2b) are prepared. The light-emitting layer(4) is formed between the first electrode and the second electrode. Organic films(3a, 3b) are in other words formed for the first electrode and light-emitting layer between the second electrode and light-emitting layer. The memory layer(5) is in other words formed for the first electrode and light-emitting layer between the second electrode and light-emitting layer.
摘要翻译：目的：通过使用包括在有机发光装置内的存储层，用于包括有机发光装置的显示装置以及驱动方法和有机发光装置驱动。孔径比得到改善，因为不包括晶体管。构成：准备第一电极（2a）和第二电极（2b）。发光层（4）形成在第一电极和第二电极之间。换句话说，为第一电极和第二电极和发光层之间的发光层形成有机膜（3a，3b）。换句话说，为第一电极和第二电极和发光层之间的发光层形成存储层（5）。

7. 发明授权

KR101863388B1 평탄한 실리콘 함유막 有权
公开(公告)号：KR101863388B1
公开(公告)日：2018-05-31
申请号：KR1020137009445
申请日：2011-08-09
申请人： 노벨러스 시스템즈, 인코포레이티드
发明人： 폭스키스 , 니우동 , 워맥조 , 스리람만디암 , 안토넬리조지앤드류 , 판슈라벤디크바르트 , 올러프린제니퍼
IPC分类号： H01L21/205
CPC分类号： C23C16/505 , C23C16/24 , C23C16/345 , C23C16/402 , C23C16/4401 , C23C16/45523 , C23C16/509 , C23C16/54 , H01L21/02104 , H01L21/02123 , H01L21/02129 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/02211 , H01L21/02263 , H01L21/02274 , H01L21/0245 , H01L21/02507 , H01L21/02532 , H01L21/0254 , H01L21/6719 , H01L21/67201 , H01L21/67207 , H01L21/8229
摘要： 초평탄실리콘함유막들및 막스택들을위한방법들및 하드웨어가개시된다. 일예에있어서, 플라즈마강화화학기상증착장치에서기판상에실리콘함유막을성막하는방법의일 실시형태가개시되며, 방법은플라즈마강화화학기상증착장치에실리콘함유반응물을공급하는단계; 플라즈마강화화학기상증착장치에공반응물을공급하는단계; 플라즈마강화화학기상증착장치의프로세스스테이션에용량결합형플라즈마를공급하는단계로서, 플라즈마는실리콘함유반응물로부터발생된실리콘라디칼들및 공반응물로부터발생된공반응물라디칼들을포함하는, 용량결합형플라즈마를공급하는단계; 및기판상에실리콘함유막을성막하는단계를포함하고, 실리콘함유막은 1.4 내지 2.1 의굴절률을가지며, 실리콘함유막은또한실리콘기판상에서측정될때 4.5 이하의절대조도를갖는다.

8. 发明公开

KR1020150137720A 반도체 장치의 제조 방법 审中-实审
标题翻译：半导体装置的制作方法
公开(公告)号：KR1020150137720A
公开(公告)日：2015-12-09
申请号：KR1020140066071
申请日：2014-05-30
申请人： 에스케이하이닉스 주식회사
发明人： 박해찬
IPC分类号： H01L21/335 , H01L29/786
CPC分类号： H01L21/845 , H01L21/0455 , H01L21/8229 , H01L27/2454 , H01L45/04 , H01L45/1233 , H01L45/1675
摘要： 본기술에따른반도체장치의제조방법은, 셀영역과페리영역이정의된반도체기판을제공하는단계와, 반도체기판상에확산방지막을형성하는단계와, 확산방지막이형성된반도체기판결과물에반도체막을형성하는단계와, 반도체막상에실리사이드막을형성하는단계와, 실리사이드막상에도전막을형성하는단계와, 페리영역과셀 영역의일부에위치한도전막, 실리사이드막, 반도체막을지정된높이로패터닝하여필라구조물의상부를한정하는단계와, 필라구조물의상부를제외한셀 영역의확산방지막과반도체기판을패터닝하여필라구조물의하부를한정하는단계및 패터닝된반도체기판의외측에배치되는게이트전극을형성하는단계를포함할수 있다.
摘要翻译：根据本发明的半导体器件的制造方法包括以下步骤：提供具有限定的单元面积和周边区域的半导体基板; 在所述半导体衬底上形成扩散阻挡层; 在半导体衬底上形成半导体层，形成扩散阻挡层; 在半导体层上形成硅化物层; 在硅化物层上形成导电层; 通过将位于周边区域和单元区域的一部分中的导电层，硅化物层和半导体层图案化到特定高度来限制柱结构的上部; 通过图案化除了柱结构的上部之外的单元区域和半导体基板的扩散阻挡层来限制柱结构的下部; 以及形成设置在图案化半导体衬底的外侧上的栅电极。

9. 发明公开

KR1020110129254A 3차원 반도체 메모리 장치 有权
标题翻译：三维半导体存储器件
公开(公告)号：KR1020110129254A
公开(公告)日：2011-12-01
申请号：KR1020100048793
申请日：2010-05-25
申请人： 삼성전자주식회사
发明人： 김기남 , 박용직 , 최시영 , 김형섭 , 장재훈
IPC分类号： H01L21/8239 , H01L21/8242 , H01L27/108 , G11C8/14
CPC分类号： G11C16/0466 , G11C16/0483 , H01L27/11578 , H01L27/11582 , H01L29/7926 , H01L21/8239 , G11C8/14 , H01L21/82 , H01L21/8229 , H01L27/108
摘要： PURPOSE: A three-dimensional semiconductor memory apparatus is provided to arrange memory cells and selection transistors in different levels from each other, thereby highly integrating the three-dimensional semiconductor memory apparatus. CONSTITUTION: A three-dimensional semiconductor memory apparatus comprises a memory structure and a control structure laminated on a substrate. The control structure is laminated on the substrate. The memory structure comprises a plurality of successively laminated word lines(WL1-WL6) and a semiconductor pattern. The semiconductor pattern faces sidewalls of the word lines while crossing the word lines. The control structure comprises a string which respectively touches both ends of the semiconductor pattern and ground-selection transistors(SST,GST). A detection amplifier(40) is integrated on the substrate and arranged between the substrate and memory structure.
摘要翻译：目的：提供一种三维半导体存储装置，用于将存储单元和选择晶体管彼此不同的级别布置，从而高度集成三维半导体存储装置。构成：三维半导体存储装置包括层叠在基板上的存储结构和控制结构。控制结构层叠在基板上。存储器结构包括多个连续层叠的字线（WL1-WL6）和半导体图案。半导体图案在与字线交叉时面向字线的侧壁。控制结构包括分别接触半导体图案的两端的串和接地选择晶体管（SST，GST）。检测放大器（40）集成在基板上并且布置在基板和存储器结构之间。

10. 发明公开

KR1020070007308A 반도체장치의 제조방법, ＩＣ 카드, ＩＣ 태그, ＲＦＩＤ,트랜스폰더, 지폐, 유가증권, 여권, 전자 기기, 가방 및의류 有权
标题翻译：半导体器件的制造方法，IC卡，IC标签，RFID，TRANSPONDER，BILL，SECURITIES，PASSPORT，电子设备，袋子和服装
公开(公告)号：KR1020070007308A
公开(公告)日：2007-01-15
申请号：KR1020067018171
申请日：2005-02-15
申请人： 가부시키가이샤 한도오따이 에네루기 켄큐쇼
发明人： 고야마준
IPC分类号： H01L21/027 , H01L21/8229
CPC分类号： H01L27/1266 , H01L23/5227 , H01L27/1214 , H01L27/1288 , H01L27/13 , H01L2924/0002 , H01L2924/00 , H01L21/8229
摘要： The present invention provides a manufacturing method of a semiconductor device used as an ID chip, by which data can be written with improved throughput. According to the manufacturing method of a semiconductor device having a modulation circuit, a demodulation circuit, a logic circuit, a memory circuit, and an antenna circuit over an insulating substrate, the memory circuit is a nonvolatile memory circuit of which data is written in the manufacture of the semiconductor device, and elements in a data portion are formed by electron beam exposure or laser exposure while the other portions are formed by mirror projection exposure, step and repeat exposure, or step and scan exposure. ® KIPO & WIPO 2007
摘要翻译：本发明提供了一种用作ID芯片的半导体器件的制造方法，通过该方法能够以提高的生产量写入数据。根据在绝缘基板上具有调制电路，解调电路，逻辑电路，存储电路和天线电路的半导体器件的制造方法，存储电路是非易失性存储电路，其数据被写入半导体器件的制造和数据部分中的元件通过电子束曝光或激光曝光形成，而其它部分通过镜投影曝光，步进和重复曝光或步进和扫描曝光形成。 ®KIPO＆WIPO 2007

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