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1. 发明公开

KR20180065423A 리페어 가능한 휘발성 메모리를 포함하는 스토리지 장치 및 상기 스토리지 장치의 동작 방법 审中-公开
公开(公告)号：KR20180065423A
公开(公告)日：2018-06-18
申请号：KR20160166206
申请日：2016-12-07
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： KIM SANG HUN , SUNG JUN KI
IPC分类号： G11C29/26
CPC分类号： G11C29/38 , G11C29/36 , G11C29/44 , G11C29/783 , G11C2029/0409 , G11C2029/4402
摘要： 리페어가능한휘발성메모리를포함하는스토리지장치및 상기스토리지장치의동작방법이개시된다. 본개시의기술적사상에따른스토리지장치는, 유저데이터를저장하는비휘발성메모리, 상기유저데이터를버퍼링하고, 상기스토리지장치의유휴시간에휘발성셀 어레이에대하여결함셀 검출을위한테스트를수행하는휘발성메모리, 및상기유휴시간에상기휘발성메모리가상기테스트를수행하도록제어하고, 테스트결과또는테스트이력(history)을포함하는테스트정보를상기비휘발성메모리에저장하는컨트롤러를포함할수 있다.

2. 发明公开

KR1020160119586A 반도체 메모리 장치 및 그 동작방법 审中-实审
标题翻译：半导体存储器件及其操作方法
公开(公告)号：KR1020160119586A
公开(公告)日：2016-10-14
申请号：KR1020150048455
申请日：2015-04-06
申请人： 에스케이하이닉스 주식회사
发明人： 김성호
IPC分类号： G11C29/00 , G11C29/02 , G11C11/406 , G11C11/4093 , G11C11/4096 , G11C11/408 , G11C11/4091
CPC分类号： G11C29/783 , G11C11/406 , G11C11/40603 , G11C11/40611 , G11C11/40618 , G11C11/4072 , G11C11/4091 , G11C11/4096 , G11C17/16 , G11C17/18 , G11C29/76 , G11C2029/4402
摘要： 본기술은다수의퓨즈를사용하는반도체메모리장치에관한것으로서, 하나의트랜지스터및 커패시터를각각포함하는다수의제1 메모리셀과다수의제2 메모리셀 및다수의제3 메모리셀과, 다수의제1 메모리셀 중불량으로판정된셀을다수의제2 메모리셀로리페어하기위한리페어정보를럽쳐하는다수의퓨즈와, 부트업 구간에서리페어정보를다수의퓨즈에서리드하여다수의제3 메모리셀에라이트하고, 노말구간에서리페어정보를다수의제3 메모리셀에서리드하거나설정된제1 주기마다다수의제3 메모리셀을리프레쉬하는리페어동작부, 및노말구간에서리페어동작부를통해리드된리페어정보를기준으로, 다수의제1 또는제2 메모리셀로부터데이터를리드/라이트하거나설정된제2 주기마다다수의제1 또는제2 메모리셀을리프레쉬하는노말동작부를포함한다.

3. 发明公开

KR1020150105048A 반도체 메모리 장치 审中-实审
标题翻译：半导体存储器件
公开(公告)号：KR1020150105048A
公开(公告)日：2015-09-16
申请号：KR1020140027220
申请日：2014-03-07
申请人： 에스케이하이닉스 주식회사
发明人： 송청기
IPC分类号： G11C29/04 , G11C11/4063
CPC分类号： G11C17/16 , G06F13/1636 , G11C11/40611 , G11C17/18 , G11C29/78 , G11C29/783
摘要： 퓨즈 어레이 회로를 구비하는 반도체 메모리 장치에 관한 것으로, 활성화 제어 신호에 응답하여 입력 동작이 제어되며, 커멘드 신호를 입력받아 버퍼링하기 위한 커맨드 버퍼링부, 상기 커맨드 신호에 응답하여 예정된 데이터가 프로그래밍되는 퓨즈 어레이, 및 상기 퓨즈 어레이의 프로그래밍 동작 구간에서 상기 활성화 제어 신호의 활성화 동작을 제어하기 위한 활성화 제어부를 구비하는 반도체 메모리 장치가 제공된다.
摘要翻译：本发明涉及一种包括熔丝阵列电路的半导体存储器件。半导体存储器件包括：命令缓冲单元，用于响应于激活控制信号控制输入操作，以及接收和缓冲命令信号; 用于响应于所述命令信号编程调度数据的熔丝阵列; 以及激活控制单元，用于控制用于所述熔丝阵列的编程操作周期的所述激活控制信号的激活操作。

4. 发明公开

KR1020140080295A 코어 회로, 메모리 및 이를 포함하는 메모리 시스템 审中-实审
标题翻译：核心电路，存储器和存储器系统
公开(公告)号：KR1020140080295A
公开(公告)日：2014-06-30
申请号：KR1020120149944
申请日：2012-12-20
申请人： 에스케이하이닉스 주식회사
发明人： 송청기
IPC分类号： G11C29/00 , G11C7/12 , G11C8/14
CPC分类号： G11C29/783 , G11C7/12 , G11C8/08 , G11C29/808
摘要： The present technology stores information of counting the number of activations of each word line at memory cells connected to each word line and counts the number of the activations of each word line while repairing defects in the memory cells which store the number of the activations of the word line if the defects occur. A memory according to the present invention comprises: a first cell array including a plurality of first memory cells connected to each of a first to an N^th word line; a bit line selecting part for selecting one or more among a first to an M^th bit line in response to repair information; a second cell array including a plurality of second memory cells connected to each of the first to the N^the word line, connected to each of the first and the M^th bit line and storing the number of activations of a word line connected to itself among the first to N^th word line in a case that a bit line connected to itself is selected; and a part for updating the number of activations for updating a value stored at the second memory cell connected to one or more bit lines selected among the second memory cells connected to an activated word line among the first to the N^th word line.
摘要翻译：本技术存储对连接到每个字线的存储器单元的每个字线的激活次数进行计数的信息，并且在修复存储单元中的缺陷的同时对每个字线的激活次数进行计数，如果出现缺陷，则为字线。根据本发明的存储器包括：第一单元阵列，包括连接到第一至第N字线中的每一个的多个第一存储单元; 用于响应于修复信息在第一至第M位线中选择一个或多个位线选择部分; 第二单元阵列，包括连接到第一至第N字线中的每一个的多个第二存储单元，连接到第一和第M位线中的每一个，并存储连接到第一和第M位线的字线的激活次数在选择连接到其自身的位线的情况下，本身在第一至第N字线之间; 以及更新用于更新存储在连接到从第一至第N字线连接到激活的字线的第二存储器单元中选择的一个或多个位线的第二存储器单元存储的值的激活的部分。

5. 发明公开

KR1020140011147A 패스트 어레이 영역을 갖는 반도체 메모리 셀 어레이 및 그것을 포함하는 반도체 메모리 审中-实审
标题翻译：具有快速阵列区域的半导体存储器单元阵列和包括其的半导体存储器
公开(公告)号：KR1020140011147A
公开(公告)日：2014-01-28
申请号：KR1020120077969
申请日：2012-07-17
申请人： 삼성전자주식회사
发明人： 유학수 , 김대현 , 강욱성 , 박철우 , 최주선 , 최효진
IPC分类号： G11C8/00 , G11C11/408 , G11C11/413
CPC分类号： G11C7/1072 , G06F12/0207 , G06F12/0223 , G06F12/0638 , G11C11/005 , G11C11/403 , G11C11/40622 , G11C29/783 , G11C2029/4402
摘要： In the embodiment according to the concept of the present invention, disclosed is a semiconductor memory cell array. The semiconductor memory cell array includes a first memory cell array area with first group memory cells with preset first operation speeds which are arranged on a chip in a matrix of a row and a column. Also, the semiconductor memory cell array includes a second memory cell array area with second group memory cells with second operation speeds faster than the first operation speeds which are arranged on the chip in the matrix of the row and the column by interposing an input and output sense amplifier. Thereby, the operation performance of a memory chip is improved and low power consumption is obtained.
摘要翻译：在根据本发明的概念的实施例中，公开了半导体存储单元阵列。半导体存储单元阵列包括具有第一组存储器单元的第一存储单元阵列区，其具有预定的第一操作速度，其布置在行和列的矩阵中的芯片上。此外，半导体存储单元阵列包括具有第二组存储单元的第二存储单元阵列区域，第二组存储单元的第二操作速度比通过插入输入和输出的布置在行和列的矩阵中的芯片上的第一操作速度更快感测放大器。由此，能够提高存储芯片的动作性能，能够获得低功耗。

6. 发明公开

KR20120057381A Test circuit 审中-公开
标题翻译：测试电路
公开(公告)号：KR20120057381A
公开(公告)日：2012-06-05
申请号：KR20100119083
申请日：2010-11-26
申请人： SK HYNIX INC
发明人： HWANG SUN YOUNG
IPC分类号： G11C29/02 , G11C29/18 , G11C29/50
CPC分类号： G11C29/783 , G11C29/02 , G11C29/18 , G11C29/46 , G11C29/842
摘要： PURPOSE: A test circuit is provided to stop a refresh operation of a redundant cell if an address for a normal cell is inputted. CONSTITUTION: A test signal generating unit(1) generates an enabled test signal when an address for a redundant cell is inputted and a disabled test signal when an address for a normal cell is inputted. A redundant cell refresh unit(2) refreshes the redundant cell by receiving a test signal. A delay unit(11) delays an enabled reset signal with a preset period. A logic unit(12) generates a test signal by receiving an idle signal and an output signal of the delay unit.
摘要翻译：目的：如果输入正常单元的地址，则提供测试电路来停止冗余单元的刷新操作。构成：当输入冗余单元的地址时，测试信号生成单元（1）产生使能的测试信号，当输入正常单元的地址时，产生禁用的测试信号。冗余单元刷新单元（2）通过接收测试信号来刷新冗余单元。延迟单元（11）以预设周期延迟使能复位信号。逻辑单元（12）通过接收空闲信号和延迟单元的输出信号来产生测试信号。

7. 发明公开

KR1020090075497A 반도체 메모리 장치 失效
标题翻译：半导体存储器件
公开(公告)号：KR1020090075497A
公开(公告)日：2009-07-08
申请号：KR1020080001374
申请日：2008-01-04
申请人： 에스케이하이닉스 주식회사
发明人： 최현승
IPC分类号： G11C29/00
CPC分类号： G11C29/787 , G11C29/783 , G11C29/808
摘要： A semiconductor memory device is provided to increase the number of net dies of chip by reducing the number of redundancy word lines and fuse boxes. A semiconductor memory device comprises a redundancy cell, a redundancy word line(RWL2) and a plurality of fuse boxes(200). The redundancy cell comprises a plurality of even numbered cell mats and a plurality of odd numbered cell mats. The redundancy word line is connected to one of the even numbered cell mat and the odd numbered cell mat. The fuse box is connected to the redundancy word line with one to one. In case the fail is generated in the normal cell connected to the even numbered cell mat or the odd numbered cell mat, the address of the normal cell is stored in the fuse box. If the low address coincides with the address stored in the fuse box, the normal cell is replaced by the redundancy cell connected to the redundancy word line.
摘要翻译：提供一种半导体存储器件，通过减少冗余字线和熔丝盒的数量来增加芯片的净模数。半导体存储器件包括冗余单元，冗余字线（RWL2）和多个保险丝盒（200）。冗余单元包括多个偶数编号的单元格单元和多个奇数编号的单元格单元。冗余字线连接到偶数号单元格和奇数单元格中的一个。保险丝盒与冗余字线连接一对一。在连接到偶数号单元格或奇数单元格的正常单元中产生故障的情况下，正常单元的地址被存储在保险丝盒中。如果低地址与存储在保险丝盒中的地址一致，则正常单元被连接到冗余字线的冗余单元替换。

8. 发明公开

KR1020080060316A 반도체 메모리 소자의 리프레쉬 제어장치 失效
标题翻译：半导体存储器件中的刷新控制器
公开(公告)号：KR1020080060316A
公开(公告)日：2008-07-02
申请号：KR1020060134264
申请日：2006-12-27
申请人： 에스케이하이닉스 주식회사
发明人： 최돈현
IPC分类号： G11C11/401 , G11C11/406 , G11C29/00 , G11C11/407
CPC分类号： G11C11/406 , G11C7/22 , G11C8/08 , G11C11/4076 , G11C11/4085 , G11C29/02 , G11C29/783
摘要： A refresh controller in a semiconductor memory device is provided to prevent operation error in the refresh controller of the semiconductor memory device due to input timing of a bank active signal during test mode operation. A bank(330) comprises a number of normal word lines and redundancy word lines. An internal command signal generation unit(300) generates a refresh signal and a bank active signal in response to an external command. A refresh control unit(310) outputs an external address or an internal counting address as a row address signal in response to the refresh signal, and outputs a redundancy word line refresh start signal in a word line refresh test mode. A delay control unit(340) delays the bank active signal selectively in response to a delay control test signal in the word line refresh test mode. A word line driving unit(320) drives a normal word line and a redundancy word line corresponding to the row address signal in response to an output signal of the delay control unit and the redundancy word line refresh start signal.
摘要翻译：提供半导体存储器件中的刷新控制器，以在测试模式操作期间由于存储体活动信号的输入定时而防止半导体存储器件的刷新控制器中的操作错误。存储体（330）包括多个正常字线和冗余字线。内部命令信号生成单元（300）响应于外部命令产生刷新信号和存储体活动信号。刷新控制单元（310）响应于刷新信号输出外部地址或内部计数地址作为行地址信号，并且在字线刷新测试模式下输出冗余字线刷新开始信号。延迟控制单元（340）响应于字线刷新测试模式中的延迟控制测试信号选择性地延迟存储体有效信号。字线驱动单元（320）响应延迟控制单元的输出信号和冗余字线刷新开始信号，驱动对应于行地址信号的正常字线和冗余字线。

9. 发明授权

KR100805699B1 반도체 메모리 장치 및 그의 구동방법 失效
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：KR100805699B1
公开(公告)日：2008-02-21
申请号：KR1020060083742
申请日：2006-08-31
申请人： 에스케이하이닉스 주식회사
发明人： 한희현
IPC分类号： G11C11/401 , G11C29/00
CPC分类号： G11C11/406 , G11C11/4076 , G11C29/12 , G11C29/783
摘要： A semiconductor memory device and a driving method thereof are provided to judge start and end timing of refresh operation of a normal region and a refresh region easily. A first enable sensing part(10) generates a first pulse corresponding to enable timing of a reference signal enabled according as refresh operation of a refresh region starts and disabled according as the refresh operation ends. A second enable sensing part(20) generates a second pulse corresponding to disable timing of the reference signal. A first selection part(40) outputs an enable sensing signal by selecting one of the first pulse and the second pulse in response to a test signal. A source signal transfer part(50) transfers an access signal corresponding to access operation of the normal region in response to the enable sensing signal. A phase comparison part(70) outputs a test result signal by comparing phase of a redundancy refresh signal controlling refresh operation of redundancy region with phase of an access signal transferred from the source signal transfer part.
摘要翻译：提供一种半导体存储器件及其驱动方法，用于容易地判断正常区域和刷新区域的刷新操作的开始和结束时刻。第一使能检测部件（10）根据刷新操作结束，根据刷新区域的刷新操作启动和禁用，产生对应于启用的参考信号的使能定时的第一脉冲。第二使能感测部件（20）产生对应于参考信号的禁止定时的第二脉冲。第一选择部件（40）响应于测试信号，通过选择第一脉冲和第二脉冲中的一个来输出使能感测信号。源信号传送部件（50）响应于使能感测信号传送与正常区域的访问操作相对应的访问信号。相位比较部分70通过比较控制冗余区域的刷新操作的冗余刷新信号与从源信号传送部分传送的存取信号的相位的相位来输出测试结果信号。

10. 发明授权

KR100448429B1 반도체 메모리 장치 및 그 테스트 방법 有权
标题翻译： 반도체메모리장치및그테스트방법
公开(公告)号：KR100448429B1
公开(公告)日：2004-09-13
申请号：KR1020010063196
申请日：2001-10-13
申请人： 엘피다 메모리, 아이엔씨.
发明人： 미네고지
IPC分类号： G11C29/00
CPC分类号： G11C29/783 , G11C11/401 , G11C11/406 , G11C29/02 , G11C29/24 , G11C29/50 , G11C29/50016 , G11C29/72 , G11C2029/0403
摘要： A semiconductor memory device and method for its test is disclosed including a CBR (CAS before RAS) refresh test achieved by inputting a CBR command for every redundant word line to be selected. In this way, redundant word lines may be selected without repetition until all of the redundant word lines have been selected. By doing so, an accurate determination of the refresh period may be obtained. A CBR refresh counter (15) may be activated every time a control signal is received when a refresh test on redundant memory cells (RC) is performed. Redundant counter signals (RCNT0 to RCNT5) may be applied to a X address buffer (2A). X address buffer (2A) may select the redundant counter signals (RCNT0 to RCNT5) to sequentially select the redundant word lines (RWL0 to RWL63) when a redundant refresh test is performed.
摘要翻译：公开了一种半导体存储器件及其测试方法，包括通过为将要选择的每个冗余字线输入CBR命令而实现的CBR（RAS之前的CAS）刷新测试。这样，直到所有的冗余字线都被选中，冗余字线才可以被选择而不重复。通过这样做，可以获得刷新周期的准确确定。每当执行冗余存储单元（RC）的刷新测试时接收到控制信号时，CBR刷新计数器（15）可以被激活。冗余计数器信号（RCNT0至RCNT5）可以应用于X地址缓冲区（2A）。当进行冗余刷新测试时，X地址缓冲器（2A）可以选择冗余计数器信号（RCNT0至RCNT5）以顺序地选择冗余字线（RWL0至RWL63）。

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