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1. 发明授权

KR101891429B1 임계 전압 분석 有权
公开(公告)号：KR101891429B1
公开(公告)日：2018-09-28
申请号：KR1020167035949
申请日：2015-05-19
申请人： 마이크론 테크놀로지, 인크
发明人： 필리피악,윌리엄씨. , 모스치아노,비올란테
IPC分类号： G11C29/50 , G11C29/42 , G11C16/04 , G11C11/56
CPC分类号： G11C11/5642 , G11C7/1063 , G11C11/5628 , G11C11/5635 , G11C16/0483 , G11C16/10 , G11C16/14 , G11C16/26 , G11C29/021 , G11C29/028 , G11C29/20 , G11C29/42 , G11C29/50004 , G11C29/56004
摘要： 임계전압분석을위한장치들및 방법들이설명된다. 임계전압분석을위한하나이상의방법들은메모리셀들의그룹에대응하는예상상태표시자들을저장하는단계, 제1 감지전압을메모리셀들의그룹이결합되는선택된액세스라인에인가하는단계, 그룹의메모리셀들중 적어도하나가제1 감지전압에응답하여전도하는지를감지하는단계, 메모리셀들중 적어도하나에대한방전표시자가제1 감지전압의인가에응답하여변하였는지를결정하는단계, 및제1 감지전압이메모리셀들중 적어도하나의특정한프로그램상태에대한임계전압임을결정하는단계를포함한다.

2. 发明公开

KR1020160004585A 반도체 메모리 장치 및 그 동작 방법 审中-实审
标题翻译：半导体存储器件及其工作方法
公开(公告)号：KR1020160004585A
公开(公告)日：2016-01-13
申请号：KR1020140083071
申请日：2014-07-03
申请人： 에스케이하이닉스 주식회사
发明人： 김상희
IPC分类号： G11C29/04 , G11C11/4063
CPC分类号： G11C29/00 , G11C17/16 , G11C29/18 , G11C29/20 , G11C29/24 , G11C29/44 , G11C29/78 , G11C2029/1202 , G11C2029/4402
摘要： 리페어대상어드레스를저장하고노말동작시이를사용하여리페어동작을수행하는반도체메모리장치에관한것으로, 다수의워드라인을포함하는메모리셀 어레이, 리페어대상어드레스가프로그래밍되는리페어퓨즈부, 테스트동작시상기리페어퓨즈부의프로그래밍된정보에응답하여상기다수의워드라인에대응하는테스트어드레스를생성하기위한어드레스생성부, 및상기테스트어드레스에응답하여상기다수의워드라인의액티브여부를제어하기위한워드라인제어부를구비하는반도체메모리장치가제공된다.
摘要翻译：本发明涉及一种半导体存储器件，其存储维修对象地址，并且在正常操作中使用修复对象地址进行维修操作。半导体存储器件包括：包括字线的存储单元阵列，用于对修复对象地址进行编程的修复熔丝部分，在测试操作中对修复熔丝部件的编程信息进行响应的地址生成部分，并生成相应的测试地址到字线，以及字线控制部分，其响应测试地址并控制字线的激活。

3. 发明公开

KR1020130046767A 테스트회로를 포함하는 반도체장치 및 번인테스트 방법 无效
标题翻译：包含测试电路的半导体器件和用于测试的方法
公开(公告)号：KR1020130046767A
公开(公告)日：2013-05-08
申请号：KR1020110111330
申请日：2011-10-28
申请人： 에스케이하이닉스 주식회사
发明人： 조진희
IPC分类号： G11C29/06
CPC分类号： G11C29/06 , G11C29/20 , G11C29/46 , G11C2029/1202
摘要： PURPOSE: A semiconductor device including a test circuit and a burn-in testing method are provided to improve test efficiency by omitting an additional burn-in test in a package state. CONSTITUTION: A test circuit(3) generates a buffer control signal in response to data inputted to a data pad and generates a test mode signal and a counting enable signal for counting a row address and a column address by decoding a test command inputted in response to the buffer control signal. A data input and output circuit(2) generates the test command by buffering an external command in response to the buffer control signal and performs a burn-in test in response to the test mode signal. The data input and output circuit reads a memory cell corresponding to the row address and the column address. [Reference numerals] (21) Input buffer; (22) Command decoder; (23) Control unit; (31) Buffer control signal generator; (32) Test command decoder; (33) Address counter
摘要翻译：目的：提供包括测试电路和老化测试方法的半导体器件，通过在封装状态下省略额外的老化测试来提高测试效率。构成：测试电路（3）响应于输入到数据焊盘的数据产生缓冲器控制信号，并通过解码响应中输入的测试命令产生测试模式信号和计数使能信号，用于对行地址和列地址进行计数到缓冲器控制信号。数据输入和输出电路（2）通过响应于缓冲器控制信号缓冲外部命令产生测试命令，并根据测试模式信号进行老化测试。数据输入和输出电路读取与行地址和列地址对应的存储单元。（附图标记）（21）输入缓冲器; （22）命令解码器; （23）控制单元; （31）缓冲控制信号发生器; （32）测试命令解码器; （33）地址柜台

4. 发明公开

KR1020120122568A 집적 회로와 그를 이용하는 반도체 메모리 장치 无效
标题翻译：集成电路和使用相同的半导体存储器件
公开(公告)号：KR1020120122568A
公开(公告)日：2012-11-07
申请号：KR1020110040802
申请日：2011-04-29
申请人： 에스케이하이닉스 주식회사
发明人： 최대일
IPC分类号： G11C8/18 , G11C7/22
CPC分类号： G06F12/0207 , G11C8/04 , G11C29/18 , G11C29/20
摘要： PURPOSE: An integrated circuit and a semiconductor memory device using the same are provided to improve an operation speed of the semiconductor memory device by randomizing data using a first random address and a second random address. CONSTITUTION: A random address generating unit(210) generates a first random address for randomizing data. An address converting unit(220) generates a second random address by converting the first random address. A synchronization output unit(230) synchronizes the first and second random addresses with a preset clock signal and successively outputs the synchronized result. A signal mixing unit(240) mixes the first and second random addresses with the data. [Reference numerals] (210) Random address generating unit; (220) Address converting unit; (230) Synchronization output unit; (240) Signal mixing unit; (250) Data inputting unit; (260) Signal mixing unit; (270) Memory cell array; (280) Signal mixing unit
摘要翻译：目的：提供使用其的集成电路和半导体存储器件，以通过使用第一随机地址和第二随机地址随机化数据来提高半导体存储器件的操作速度。构成：随机地址生成单元（210）生成用于随机化数据的第一随机地址。地址转换单元（220）通过转换第一随机地址来生成第二随机地址。同步输出单元（230）使第一和第二随机地址与预设的时钟信号同步，并且连续输出同步结果。信号混合单元（240）将第一和第二随机地址与数据进行混合。（附图标记）（210）随机地址生成单元; （220）地址转换单元; （230）同步输出单元; （240）信号混合单元; （250）数据输入单元; （260）信号混合单元; （270）存储单元阵列; （280）信号混合单元

5. 发明公开

KR1020090096154A 병렬 비트 테스트를 수행하는 테스트 시스템 无效
标题翻译：用于执行并行位测试的测试系统
公开(公告)号：KR1020090096154A
公开(公告)日：2009-09-10
申请号：KR1020080021566
申请日：2008-03-07
申请人： 삼성전자주식회사
发明人： 김병술 , 이성희 , 이정국 , 최희주
IPC分类号： G11C29/00
CPC分类号： G11C29/26 , G11C5/04 , G11C2029/2602 , G11C29/10 , G11C29/20 , G11C2029/3602
摘要： A test system capable of performing a parallel bit test is provided to reduce probability of error generation in a parallel bit test about a plurality of memory modules. A plurality of counters(330,340) counts the number of output signals having the same logic state among output signals of each memory module, and outputs a count signal. The counter outputs a count signal having a different logic state according to odd number or even number of the output signals having the same logic state. A comparing part(350) compares the count signal outputted in each counter, and outputs a comparing signal corresponding to a defect of the memory module. A control part(360) controls an enable state of the memory module in response to the comparing signal. The control part controls application of a DQS signal in a pad in response to the comparing signal.
摘要翻译：提供能够执行并行比特测试的测试系统，以减少关于多个存储器模块的并行比特测试中的错误产生的概率。多个计数器（330,340）对每个存储器模块的输出信号中具有相同逻辑状态的输出信号的数量进行计数，并输出计数信号。计数器根据具有相同逻辑状态的输出信号的奇数或偶数输出具有不同逻辑状态的计数信号。比较部分（350）比较在每个计数器中输出的计数信号，并输出与存储器模块的缺陷相对应的比较信号。控制部分（360）响应于比较信号控制存储器模块的使能状态。控制部分响应于比较信号来控制在焊盘中的DQS信号的应用。

6. 发明公开

KR1020080089015A 테스트 코드롬을 구비한 반도체 메모리 장치 无效
标题翻译：具有测试代码ROM的半导体存储器件
公开(公告)号：KR1020080089015A
公开(公告)日：2008-10-06
申请号：KR1020070031971
申请日：2007-03-30
申请人： 에스케이하이닉스 주식회사
发明人： 김동균
IPC分类号： G11C29/00
CPC分类号： G11C29/20 , G11C2029/3602 , G11C29/1201 , G11C29/10
摘要： A semiconductor memory device with a test code ROM is provided to minimize the number of signals inputted from the outside. A semiconductor memory device comprises a memory core region, a data transmission circuit(180), a data code storage unit(500) and a data selection part(600). The data transmission circuit receives data from the outside, and provides the data to the memory core region. The data code storage unit, such as a ROM, stores test data. The data selection part provides one of the test data outputted from the data code storage unit and the data provided from the data transmission circuit to the memory core region.
摘要翻译：提供具有测试代码ROM的半导体存储器件以使从外部输入的信号的数量最小化。半导体存储器件包括存储器核心区域，数据传输电路（180），数据代码存储单元（500）和数据选择部分（600）。数据发送电路从外部接收数据，并将数据提供给存储器核心区域。诸如ROM的数据代码存储单元存储测试数据。数据选择部分提供从数据代码存储单元输出的测试数据和从数据传输电路提供给存储器核心区域的数据之一。

7. 发明公开

KR1020070116892A 집적 회로 디바이스 내에서의 테스트를 위한 패턴을내부적으로 생성하는 시스템 및 방법 有权
标题翻译：用于在集成电路设备中测试的内部生成模式
公开(公告)号：KR1020070116892A
公开(公告)日：2007-12-11
申请号：KR1020077023925
申请日：2006-03-16
申请人： 램버스 인코포레이티드
发明人： 오엔지아드리안이.
IPC分类号： G11C7/00
CPC分类号： G11C29/20 , G01R31/31813 , G11C2029/3602 , H01L24/06 , H01L2224/05554 , H01L2224/48091 , H01L2224/48137 , H01L2224/49109 , H01L2224/49175 , H01L2924/01021 , H01L2924/01055 , H01L2924/14 , H01L2924/00014 , H01L2924/00
摘要： In a first integrated circuit chip contained in a single package along with a second integrated circuit chip, a system includes circuitry on the first integrated circuit chip for receiving address signals from the second integrated circuit chip during normal operation. Circuitry on the first integrated circuit chip generates address signals for use in testing the first integrated chip in a test mode.
摘要翻译：在与第二集成电路芯片一起包含在单个封装中的第一集成电路芯片中，系统包括在第一集成电路芯片上的电路，用于在正常操作期间从第二集成电路芯片接收地址信号。第一集成电路芯片上的电路产生用于在测试模式下测试第一集成芯片的地址信号。

8. 发明公开

KR1020000041750A 플래쉬 메모리 장치의 테스트 회로 및 테스트 방법 失效
标题翻译：用于测试闪存存储器件的电路和方法
公开(公告)号：KR1020000041750A
公开(公告)日：2000-07-15
申请号：KR1019980057718
申请日：1998-12-23
申请人： 에스케이하이닉스 주식회사
发明人： 강혁
IPC分类号： G11C16/00
CPC分类号： G11C29/50 , G11C16/04 , G11C16/344 , G11C29/20
摘要： PURPOSE: A circuit for testing a flash memory device is provided to reduce the time needed to develop a new product, test time and manufacturing cost, by having a program and an erase operation automatically connected by designing the circuit, taking account of a test in a product design step, and by completing a test mode together with a fail flag, when a fail about a chip is found within a specific cycle. CONSTITUTION: A circuit for testing a flash memory device comprises a byte programming element(500), a chip erasing element(600), a sector address increasing element(800), a first element(100), a second element(200) and an address/sector decoder(400). The byte programming performs a byte program according to a byte program enable signal and a cell address signal, and outputs a last address signal of a sector, a program fail signal and an address signal of a fail cell. The chip erasing element performs a chip erasion according to a chip erase enable signal and the sector address signal, and outputs an erase fail signal and an address signal of a fail sector. The sector address-increasing element increases a sector address according to the sector address signal, and outputs a last sector address signal. The first element generates a test signal according to a test enable signal, the last sector address signal, a test erase enable signal, the program fail signal and the erase fail signal. The second element generates a test program enable signal or a test erase enable signal according to a last sector address signal and a test signal, and supplies the generated signal to the byte programming element or the chip erasing element. The address/sector decoder decodes an address from an address pad to a cell address and a sector address, and supplies the decoded address to the byte programming element and the chip-erasing element.
摘要翻译：目的：提供一种用于测试闪存设备的电路，以便通过设计电路自动连接程序和擦除操作来减少开发新产品所需的时间，测试时间和制造成本，同时考虑到测试产品设计步骤，并且在特定周期内发现芯片故障时，通过完成测试模式以及失败标志。构成：用于测试闪速存储器件的电路包括字节编程元件（500），芯片擦除元件（600），扇区地址增加元件（800），第一元件（100），第二元件（200）和地址/扇区解码器（400）。字节编程根据字节编程使能信号和单元地址信号执行字节程序，并输出扇区的最后地址信号，程序失败信号和故障单元的地址信号。芯片擦除元件根据芯片擦除使能信号和扇区地址信号进行芯片擦除，并输出故障扇区的擦除失败信号和地址信号。扇区寻址增加元素根据扇区地址信号增加扇区地址，并输出最后的扇区地址信号。第一个元件根据测试使能信号，最后一个扇区地址信号，测试擦除使能信号，程序故障信号和擦除故障信号产生测试信号。第二元件根据最后的扇区地址信号和测试信号产生测试程序使能信号或测试擦除使能信号，并将产生的信号提供给字节编程元件或芯片擦除元件。地址/扇区解码器将地址从地址块解码为单元地址和扇区地址，并将解码的地址提供给字节编程元件和擦除元件。

9. 发明公开

KR1020000029368A 시스템 온-칩에서의 내장 코아를 테스트하기 위한 방법 및 구조 失效
标题翻译：基于嵌入式系统的片上系统芯片测试方法与结构
公开(公告)号：KR1020000029368A
公开(公告)日：2000-05-25
申请号：KR1019990047027
申请日：1999-10-28
申请人： 어드밴테스트 코포레이션
发明人： 레지슈맨로취트 , 야모또히로아끼
IPC分类号： G01R31/28
CPC分类号： G06F11/2236 , G01R31/318385 , G11C29/20
摘要： PURPOSE: A method and a structure for testing SoC IC(system-on-chip IC) based on embedded cores are provided to test the embedded cores without increasing hardwares substantially within the SoC IC. CONSTITUTION: Embedded cores of SoC IC have a micro processor core(10), memory core(3), and other functional cores(5, 6, 7). A plurality of register are provided to test the micro processor. The micro processor is tested by performing a demand of the micro processor with pseudo random data several times and evaluating the results by means of comparing with simulation results. A test program is applied to the micro processor to generate memory test pattern in the micro processor core(10). The memory test pattern is applied to the memory core(3) and respondence from the memory core(3) is evaluated in the micro processor. A function specific test program is applied to the other functional cores(5, 6, 7) and the other functional cores(5, 6, 7) are evaluated by evaluating the output signal of the other functional cores(5, 6, 7) in the micro processor.
摘要翻译：目的：提供一种基于嵌入式核心的SoC IC（片上系统集成电路）测试方法和结构，可以在不增加SoC IC内部硬件的情况下对嵌入式内核进行测试。构成：SoC IC的嵌入式内核具有微处理器核心（10），内存核心（3）和其他功能核心（5,6,7）。提供多个寄存器来测试微处理器。微处理器通过几次伪随机数据执行微处理器的需求进行测试，并通过与仿真结果进行比较来评估结果。将测试程序应用于微处理器以在微处理器核心（10）中产生存储器测试模式。存储器测试图案被应用于存储器核心（3），并且在微处理器中评估来自存储器核心（3）的响应。通过评估其他功能核心（5,6,7）的输出信号，对功能核心（5,6,7）应用功能特定测试程序，并且评估其它功能核心（5,6,7）在微处理器中。

10. 发明授权

KR1019960006486B1 메모리 시험장치 失效
标题翻译：记忆测试仪
公开(公告)号：KR1019960006486B1
公开(公告)日：1996-05-16
申请号：KR1019930702827
申请日：1993-02-02
申请人： 가부시키가이샤 아드반테스트
发明人： 후지사키겐이치
IPC分类号： G06F12/16
CPC分类号： G11C29/56 , G11C8/16 , G11C29/003 , G11C29/20 , G11C29/44
摘要： PCT No. PCT/JP93/00118 Sec. 371 Date Dec. 30, 1993 Sec. 102(e) Date Dec. 30, 1993 PCT Filed Feb. 2, 1993 PCT Pub. No. WO93/15462 PCT Pub. Date Aug. 5, 1993.A failure analysis memory (7) having main and sub failure analysis memories (7a, 7b) has two counters (C1, C2), a multiplexer (MUX), two registers (RG1, RG2)and a comparator 14. A value corresponding to the size of a column address of a memory under test (2) is set in the register (RG1) and a stop address is set in the register (RG2). Each time a SAM part (2b) of the memory under test sequentially outputs data in an address area specified by a transfer row address and a start address, one of the counters is incremented on a one-by-one basis from a start address set therein, and its count value is selected by the multiplexer (MUX) and output as a sub address signal (SA'). During this time, the other counter in the non-counting state loads therein a main address specifying data that a RAM part 2a transfers next. When the memory under test operates in a simple read/transfer mode or a split read/transfer mode, a column address in the output from the multiplexer (MUX) is compared by the comparator (14) with the value set in the register (RG1). When the memory under test operates in a stop control split read/transfer mode the column address is compared with the value set in the register (RG2). When coincidence is detected by the comparator (14), a controller (12) switches the counting and non-counting states of the counters (C1, C2).

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