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1. 发明公开

KR1020110137524A 반도체 칩 失效
标题翻译：半导体芯片
公开(公告)号：KR1020110137524A
公开(公告)日：2011-12-23
申请号：KR1020100057512
申请日：2010-06-17
申请人： 에스케이하이닉스 주식회사
发明人： 김종훈 , 서민석 , 한권환 , 서민석 , 양승택
IPC分类号： H01L21/60 , H01L21/66
CPC分类号： H01L25/0657 , H01L22/32 , H01L23/481 , H01L2224/16145 , H01L2225/06513 , H01L2225/06544 , H01L2225/06596
摘要： PURPOSE: A semiconductor chip is provided to test whether a penetrating electrode and a circuit layer are electrically connected or not by arranging a test pad part which is connected to the penetrating electrode and the circuit layer on the other side of a semiconductor substrate. CONSTITUTION: A semiconductor chip body comprises a semiconductor substrate and a circuit layer(114). The semiconductor substrate has one side and the other side which faces to the one side. The circuit layer is formed on the one side of the semiconductor substrate. A penetrating electrode is formed in order to pass through the one side from the other side of the semiconductor substrate. A test pad part tests whether the circuit layer is normally operated or not and whether the penetrating electrode and the circuit layer are electrically connected or not.
摘要翻译：目的：提供一种半导体芯片，用于通过布置连接到半导体衬底的另一侧上的穿透电极和电路层的测试焊盘部分来测试穿透电极和电路层是否电连接。构成：半导体芯片主体包括半导体衬底和电路层（114）。半导体衬底具有一侧，另一侧面向一侧。电路层形成在半导体衬底的一侧上。形成穿透电极以从半导体衬底的另一侧穿过一侧。测试焊盘部分测试电路层是否正常工作，以及穿透电极和电路层是否电连接。

2. 发明授权

KR101078722B1 스택 패키지 및 그의 제조방법 失效
标题翻译：堆叠包装及其制造方法
公开(公告)号：KR101078722B1
公开(公告)日：2011-11-01
申请号：KR1020080023243
申请日：2008-03-13
申请人： 에스케이하이닉스 주식회사
发明人： 이하나 , 박창준 , 한권환 , 김성철 , 김성민 , 최형석
IPC分类号： H01L23/12 , H01L23/28
CPC分类号： H01L25/0657 , H01L24/80 , H01L24/95 , H01L25/50 , H01L2224/0401 , H01L2224/08146 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/80143 , H01L2224/95143 , H01L2225/06541 , H01L2225/06565 , H01L2225/06593 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00
摘要： 본발명에따른스택패키지및 그의제조방법은, 기판과, 상기기판상에스택되며, 내부에관통전극을갖는적어도둘 이상의반도체칩과, 상기스택된반도체칩들사이에개재되어상기반도체칩들간을상호접착시킴과아울러, 자기정렬(Self Alginment)시키는친수성용제(Flux) 패턴과, 상기반도체칩을포함한기판의일면을밀봉하는봉지제를포함한다.

3. 发明授权

KR101013556B1 스택 패키지의 제조방법 失效
标题翻译：堆叠封装方法
公开(公告)号：KR101013556B1
公开(公告)日：2011-02-14
申请号：KR1020080103086
申请日：2008-10-21
申请人： 에스케이하이닉스 주식회사
发明人： 한권환 , 박창준 , 김성철 , 김성민 , 최형석 , 이하나
IPC分类号： H01L25/065 , H01L23/48 , H01L21/78
CPC分类号： H01L2224/16145 , H01L2224/32145 , H01L2224/73204 , H01L2924/01075 , H01L2924/014 , H01L2924/00
摘要： 본 발명은 수율 저하 및 열피로에 의한 반도체 칩의 열화를 방지할 수 있는 스택 패키지의 제조방법을 개시한다. 개시된 본 발명에 따른 스택 패키지의 제조방법은, 다수의 제1반도체 칩을 포함하는 웨이퍼의 후면을 백-그라인딩하는 단계; 상기 백-그라인딩된 웨이퍼의 후면에 지지대를 부착하는 단계; 상기 백-그라인딩된 웨이퍼의 제1반도체 칩들 상에 각각 적어도 하나 이상의 제2반도체 칩을 스택하는 단계; 상기 스택된 제1반도체 칩 및 제2반도체 칩간을 전기적으로 상호 연결시키는 제1관통전극을 형성하는 단계; 상기 스택된 제2반도체 칩들 중 최상부의 제2반도체 칩 상에 상기 제1관통전극과 전기적으로 연결되는 제2관통전극 및 상기 제2관통전극과 연결된 재배선을 구비한 제3반도체 칩을 부착하는 단계; 상기 제3반도체 칩의 재배선 상에 외부접속단자를 부착하는 단계; 및 상기 제2 및 제3 반도체 칩이 각각 스택된 웨이퍼 레벨의 제1반도체 칩들을 칩 레벨로 쏘잉하는 단계;를 포함한다.

4. 发明公开

KR1020100111469A 반도체 패키지 제조방법 无效
标题翻译：制造半导体封装的方法
公开(公告)号：KR1020100111469A
公开(公告)日：2010-10-15
申请号：KR1020090029917
申请日：2009-04-07
申请人： 에스케이하이닉스 주식회사
发明人： 김성철 , 한권환
IPC分类号： H01L23/12 , H01L23/16
CPC分类号： H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/92125 , H01L2924/00
摘要： PURPOSE: A method for manufacturing a semiconductor package is provided so that the void generation can be controlled since the underfill resin can be smoothly carried through the penetration hole to the upper and lower. CONSTITUTION: A method for manufacturing a semiconductor package comprises the respective penetration hole is formed on a plurality of semiconductor chips(S101). Semiconductor chips are laminated in the top of the substrate(S102). The underfill resin is gap-filled and for substrate and semiconductor chip in the space between the semiconductor chip.
摘要翻译：目的：提供一种半导体封装的制造方法，由于可以将底部填充树脂平滑地通过贯通孔向上下移动，所以可以控制空隙生成。构成：半导体封装的制造方法包括在多个半导体芯片上形成各自的贯通孔（S101）。将半导体芯片层叠在基板的顶部（S102）。底部填充树脂是间隙填充的，并且用于半导体芯片之间的衬底和半导体芯片。

5. 发明公开

KR1020090098070A 반도체 패키지 无效
标题翻译：半导体封装
公开(公告)号：KR1020090098070A
公开(公告)日：2009-09-17
申请号：KR1020080023246
申请日：2008-03-13
申请人： 에스케이하이닉스 주식회사
发明人： 이하나 , 박창준 , 한권환 , 김성철 , 김성민 , 최형석
IPC分类号： H01L23/544 , H01L23/28
CPC分类号： H01L2224/02379 , H01L2224/18 , H01L23/544 , H01L23/522 , H01L24/28
摘要： A semiconductor package is provided to form a mark pattern in a semiconductor chip without a separate marking process by attaching a protective member in which the mark pattern is formed. A semiconductor chip(100) has a first surface(110), a second surface(120), and a bonding pad. The first surface is faced with the second surface. The bonding pad is arranged on the first surface. A protective member(200) is attached on the second surface. A mark pattern(220) including information of the semiconductor chip is formed in the protective member. A rewiring electrically connects the semiconductor chip to each bonding pad. An insulation film covers the first surface, and has an opening which exposes a part of the rewiring. A connection member is electrically connected to the rewiring through the opening. The protective member includes a bonding layer in order to be attached on the second surface.
摘要翻译：提供半导体封装以通过附加其中形成标记图案的保护构件而在半导体芯片中形成标记图案而不进行单独的标记处理。半导体芯片（100）具有第一表面（110），第二表面（120）和接合焊盘。第一表面面对第二表面。接合垫布置在第一表面上。保护构件（200）附接在第二表面上。在保护构件中形成包括半导体芯片的信息的标记图案（220）。重新布线将半导体芯片电连接到每个焊盘。绝缘膜覆盖第一表面，并且具有露出部分重新布线的开口。连接构件通过开口与重新布线电连接。保护构件包括粘合层以便附着在第二表面上。

6. 发明公开

KR1020090084645A 스택 패키지의 제조방법 失效
标题翻译：用于制作堆叠包的方法
公开(公告)号：KR1020090084645A
公开(公告)日：2009-08-05
申请号：KR1020080103086
申请日：2008-10-21
申请人： 에스케이하이닉스 주식회사
发明人： 한권환 , 박창준 , 김성철 , 김성민 , 최형석 , 이하나
IPC分类号： H01L25/065 , H01L23/48 , H01L21/78
CPC分类号： H01L2224/16145 , H01L2224/32145 , H01L2224/73204 , H01L2924/01075 , H01L2924/014 , H01L25/0657 , H01L21/78 , H01L23/481 , H01L2924/00
摘要： A manufacturing method of stacked package is provided to prevent the deterioration of semiconductor chip according to the soldering temperature by sawing the stacked semiconductor package to the chip level. The backplane of the wafer including a plurality of first semiconductor chips(102) is grinded. A support stand is adhered to the backplane of the wafer. At least one second semiconductor chip(112) is stacked on the first semiconductor chips of the wafer respectively. The first penetrating electrode which electrically and mutually connects the stacked first semiconductor chip and the second semiconductor chip liver is formed. The third semiconductor chip(132) equipped with the rerouting connected with the second penetrating electrode and the second penetrating electrode electrically connected are formed on the second semiconductor chip. The outer connector is adhered to a rerouting(146) of the third semiconductor chip.
摘要翻译：提供堆叠封装的制造方法，以通过将堆叠的半导体封装切割到芯片级来防止半导体芯片根据焊接温度的劣化。研磨包括多个第一半导体芯片（102）的晶片的背板。支撑架附着在晶片的背板上。至少一个第二半导体芯片（112）分别堆叠在晶片的第一半导体芯片上。形成第一贯穿电极，其电叠层连接第一半导体芯片和第二半导体芯片。在第二半导体芯片上形成配备有与第二穿透电极连接的重新布线的第三半导体芯片（132）和电连接的第二贯穿电极。外部连接器粘附到第三半导体芯片的重新布线（146）上。

7. 发明公开

KR1020090084403A 적층 반도체 패키지 无效
标题翻译：堆叠式半导体封装
公开(公告)号：KR1020090084403A
公开(公告)日：2009-08-05
申请号：KR1020080010580
申请日：2008-02-01
申请人： 에스케이하이닉스 주식회사
发明人： 김성민 , 박창준 , 한권환 , 김성철 , 최형석 , 이하나
IPC分类号： H01L23/12
CPC分类号： H01L2224/16145 , H01L2224/16225 , H01L2224/73257
摘要： A stacked semiconductor packages is provided to suppress the parasitic capacitance caused by the semiconductor chip and the rerouting by forming the rerouting on the backplane of the semiconductor package. A substrate(100) has the first and the second connection pads. The first semiconductor package(200) is arranged on the first side, and has the first semiconductor chip(210) including the first bonding pad bonded to the first connection pad(140), and a rerouting structure(220) which is arranged on the second side. The second semiconductor package(400) is arranged on the third side, and has the second semiconductor chip having the second bonding pad which is bonded with the rerouting structure. The rerouting structure and the second connection pad(150) are electrically connected by a conductive wire(300). The first connection pad and the first bonding pad are electrically connected to the first connection element.
摘要翻译：提供堆叠的半导体封装以通过在半导体封装的背板上形成重新布线来抑制由半导体芯片引起的寄生电容和重新布线。衬底（100）具有第一和第二连接焊盘。第一半导体封装（200）布置在第一侧上，并且具有包括接合到第一连接焊盘（140）的第一焊盘的第一半导体芯片（210）和布置在第一连接焊盘第二面。第二半导体封装（400）布置在第三侧上，并且具有第二半导体芯片，其具有与重新布线结构结合的第二焊盘。重路由结构和第二连接焊盘（150）通过导线（300）电连接。第一连接焊盘和第一接合焊盘电连接到第一连接元件。

8. 发明公开

KR1020090080700A 메모리 모듈 失效
标题翻译：记忆模块
公开(公告)号：KR1020090080700A
公开(公告)日：2009-07-27
申请号：KR1020080006604
申请日：2008-01-22
申请人： 에스케이하이닉스 주식회사
发明人： 박창준 , 한권환 , 김성철 , 김성민 , 최형석 , 이하나
IPC分类号： H01L21/60
CPC分类号： H01L2224/16225
摘要： A memory module is provided to shorten a signal transmission distance by reducing a dimension of an external circuit in which a memory module is mounted. A memory module includes a module substrate(100) and a semiconductor package(110). The module substrate includes a plurality of first connecting parts(120), a plurality of second connecting parts(130), a first contact pad(122), and a second contact pad(132). A plurality of first connecting parts is protruded on at least one surface among a top surface and a bottom surface, and is isolated. A plurality of second connecting parts is arranged between the first connecting parts. The semiconductor package is mounted on the first connecting parts and the second connecting parts. The first contact pad and the second contact pad are included on a top surface of the first connecting parts and the second connecting parts, and are electrically connected to the semiconductor package.
摘要翻译：提供存储器模块以通过减小其中安装存储器模块的外部电路的尺寸来缩短信号传输距离。存储器模块包括模块衬底（100）和半导体封装（110）。模块基板包括多个第一连接部分（120），多个第二连接部分（130），第一接触焊盘（122）和第二接触焊盘（132）。多个第一连接部分在顶表面和底表面中的至少一个表面上突出并被隔离。多个第二连接部件布置在第一连接部件之间。半导体封装安装在第一连接部分和第二连接部分上。第一接触焊盘和第二接触焊盘包括在第一连接部分和第二连接部分的顶表面上，并且电连接到半导体封装。

9. 发明公开

KR1020090074502A 스택 패키지 无效
标题翻译：堆叠包
公开(公告)号：KR1020090074502A
公开(公告)日：2009-07-07
申请号：KR1020080000311
申请日：2008-01-02
申请人： 에스케이하이닉스 주식회사
发明人： 이하나 , 박창준 , 한권환 , 김성철 , 김성민 , 최형석
IPC分类号： H01L23/12 , H01L23/48
CPC分类号： H01L2224/13 , H01L2224/16145
摘要： A stack package is provided to widen a junction area of stacked semiconductor chips using a reinforcing member, thereby improving junction reliability of the stack package. A stack package comprises at least two semiconductor chips(110), penetrating electrodes(130) and a reinforcing member(170). The penetrating electrodes are formed on the each semiconductor chip. The penetrating electrodes are protruded to the lower part of the semiconductor chip. The reinforcing member surrounds the protruded portions of the penetrating electrodes. The reinforcing member is formed on the side of the penetrating electrodes. The reinforcing member strengthens the junction between the penetrating electrodes of the semiconductor chip.
摘要翻译：提供堆叠封装，以使用加强构件来加宽层叠的半导体芯片的接合区域，从而提高堆叠封装的结可靠性。堆叠封装包括至少两个半导体芯片（110），穿透电极（130）和加强构件（170）。穿透电极形成在每个半导体芯片上。穿透电极突出到半导体芯片的下部。加强构件围绕穿透电极的突出部分。加强构件形成在穿透电极的一侧。加强构件加强半导体芯片的穿透电极之间的接合部。

10. 发明授权

KR100895813B1 반도체 패키지의 제조 방법 失效
标题翻译：半导体封装的制造方法
公开(公告)号：KR100895813B1
公开(公告)日：2009-05-06
申请号：KR1020070060263
申请日：2007-06-20
申请人： 에스케이하이닉스 주식회사
发明人： 한권환 , 박창준 , 서민석 , 김성철 , 김성민 , 양승택 , 이승현 , 김종훈 , 이하나
IPC分类号： H01L23/12 , H01L21/60 , H01L23/48
CPC分类号： H01L21/76898 , H01L25/0657 , H01L25/50 , H01L2224/04042 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/16145 , H01L2224/274 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/83191 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H01L2924/00014 , H01L2924/00 , H01L2924/013
摘要： 본 발명에 따른 반도체 패키지의 제조 방법은, 상면에 본딩 패드가 구비된 반도체 칩의 상기 본딩 패드 외측 부분에 홈을 형성하는 단계; 상기 홈 측벽에 절연막을 형성하는 단계; 상기 측벽에 절연막이 형성된 홈을 매립하도록 상기 반도체 칩 상에 금속막을 형성하는 단계; 상기 금속막을 식각하여 홈을 매립하는 관통 실리콘 비아 및 상기 관통 실리콘 비아와 본딩 패드를 연결하는 재배선을 동시에 형성하는 단계; 및 상기 관통 실리콘 비아의 저면이 반도체 칩으로부터 돌출되도록 상기 반도체 칩의 후면을 제거하는 단계를 포함한다.

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