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1. 发明授权

KR100417644B1 화학적 기계적 연마 장비 보존 방법 失效
公开(公告)号：KR100417644B1
公开(公告)日：2004-04-13
申请号：KR1019960075145
申请日：1996-12-28
申请人： 에스케이하이닉스 주식회사
发明人： 안기철
IPC分类号： H01L21/304
摘要： PURPOSE: A method for preserving a CMP(chemical mechanical polishing) apparatus is provided to improve restoring force of a polishing pad by keeping the polishing pad dry after the polishing pad is used, and by applying heat and drying the pad while the polishing pad is rotated before the polishing pad is used. CONSTITUTION: A polishing pad(1) is installed on a polishing table. A slurry supply pipe(2) supplies slurry in a polishing process, installed over the center of the polishing pad. A lamp(5) is installed over the polishing pad. A CMP apparatus is formed of a carrier(3) rotated by a rotation unit, installed over a polishing region(4) of the polishing pad. After a polishing process, the polishing pad keeps dry. Heat is applied to dry the polishing pad while the polishing pad is rotated.

2. 发明公开

KR1020030058035A 반도체소자의 제조방법 无效
标题翻译：制造半导体器件的方法
公开(公告)号：KR1020030058035A
公开(公告)日：2003-07-07
申请号：KR1020010088187
申请日：2001-12-29
申请人： 에스케이하이닉스 주식회사
发明人： 권판기 , 이상익 , 안기철
IPC分类号： H01L21/304
摘要： PURPOSE: A method for manufacturing a semiconductor device is provided to be capable of improving the surface roughness by partially removing the surface of a tungsten film using CMP(Chemical Mechanical Polishing). CONSTITUTION: An interlayer dielectric having a contact hole is formed on a semiconductor substrate. A TiN layer as a glue layer is formed on the resultant structure. A tungsten film is formed on the TiN layer. The surface roughness is improved by partially removing the surface of the tungsten film using CMP. The tungsten film is formed by chemical vapor deposition using mixed gases of WF6, SiH4 and H2.
摘要翻译：目的：提供一种制造半导体器件的方法，通过使用CMP（Chemical Mechanical Polishing）通过部分去除钨膜的表面来提高表面粗糙度。构成：在半导体衬底上形成具有接触孔的层间电介质。在所得结构上形成作为胶层的TiN层。在TiN层上形成钨膜。通过使用CMP部分去除钨膜的表面来改善表面粗糙度。通过使用WF6，SiH4和H2的混合气体的化学气相沉积形成钨膜。

3. 发明授权

KR100335770B1 반도체 소자의 제조 방법 失效
标题翻译：制造半导体器件的方法
公开(公告)号：KR100335770B1
公开(公告)日：2002-05-09
申请号：KR1019990024210
申请日：1999-06-25
申请人： 에스케이하이닉스 주식회사
发明人： 안기철
IPC分类号： H01L21/304
摘要： 본발명은반도체소자의제조방법에관한것으로, CMP 공정에의해평탄화를실현하는반도체소자의제조방법중감광제코팅후웨이퍼가장자리에서비정상적으로두껍게코팅된감광제를제거하면서생성되는 EBR(edge bead removal) 라인폭을마스크공정별로최적화하여후속 CMP 공정시이 부분에서의과도한연마를최소화하여하부패턴이노출되는현상을방지하고폴리실리콘막의결함발생을최소화한다.
摘要翻译：本发明涉及一种制造半导体器件的方法，（边缘珠粒去除）EBR产生而异常增厚除去涂覆感光材料在半导体器件晶片边缘的制造方法的光敏剂涂覆之后，实现了通过CMP工艺线平坦化优化的宽度对于每个掩模步骤，以防止通过最小化过度抛光eseoui施部分后续CMP工艺和下部图案曝光最小化了的多晶硅膜中的缺陷的现象。

4. 发明授权

KR100318455B1 반도체소자의커패시터형성방법 失效
公开(公告)号：KR100318455B1
公开(公告)日：2002-03-08
申请号：KR1019980042790
申请日：1998-10-13
申请人： 에스케이하이닉스 주식회사
发明人： 이상익 , 안기철
IPC分类号： H01L27/04
摘要： 본 발명은 반도체소자의 커패시터 형성방법에 관한 것으로, 반도체소자의 커패시터 형성방법에 있어서, 커패시터의 스토리지노드 콘택 플러그가 형성된 기판을 준비하는 제1단계; 상기 기판 전면에 제1절연막을 형성하고 상기 제1절연막을 선택적으로 식각하여 상기 플러그를 노출시키는 제2단계; 상기 제2단계가 완료된 기판 표면 단차를 따라 스토리지노드용 폴리실리콘막을 형성하는 제3단계; 상기 제3단계가 완료된 기판 전면에 갭-필용 제2절연막을 형성하는 제4단계; 및 상기 제1절연막이 드러날때까지 상기 제2절연막과 상기 폴리실리콘막을 화학적기계적연마하여 상기 폴리실리콘막으로 이루어진 스토리지노드를 형성하는 제5단계를 포함하여 이루어져, 폴리실리콘 잔유물이 남는 문제 및 커패시터의 스토리지노드 상단부에서 누설전류가 발생할 문제점을 해결할 수 있다.

5. 发明公开

KR1020010063719A 반도체 소자의 제조 방법 无效
标题翻译：制造半导体器件的方法
公开(公告)号：KR1020010063719A
公开(公告)日：2001-07-09
申请号：KR1019990061796
申请日：1999-12-24
申请人： 에스케이하이닉스 주식회사
发明人： 안기철
IPC分类号： H01L27/108
摘要： PURPOSE: A method for fabricating a semiconductor device is provided to improve the reliability of the device by preventing a bridge due to a polysilicon film. CONSTITUTION: A bit line(22) is formed on a selected region on a cell region of a semiconductor substrate(21), and an interlayer insulation film(23) and the first interlayer film(24) and the second interlayer film(25) are formed on the whole structure including the cell region and a peripheral circuit region. After forming a contact hole revealing a part of the substrate by etching the second and the first interlayer film and a part of the interlayer insulation film, a plug(26) is formed by forming a conductive layer to fill the contact hole. After forming an oxide(27), the plug on the cell region and the second interlayer film are revealed by etching a part of the oxide, and the first EBR(Edge Bead Removal) line(300) is formed on an edge part of the peripheral region. The second EBR line(400) is formed by patterning a polysilicon film(28) more inward the wafer than the first EBR line. And, a bottom electrode is formed by removing the oxide after revealing the oxide after polishing the polysilicon film by a CMP(Chemical Mechanical Polishing) method.
摘要翻译：目的：提供一种用于制造半导体器件的方法，以通过防止由于多晶硅膜引起的桥而提高器件的可靠性。构成：在半导体基板（21）的单元区域的选定区域上形成位线（22），层间绝缘膜（23）和第一中间膜（24）以及第二中间膜（25）形成在包括单元区域和外围电路区域的整个结构上。在通过蚀刻第二层和第一层间膜和一部分层间绝缘膜形成露出基板的一部分的接触孔之后，通过形成导电层以填充接触孔而形成插塞（26）。在形成氧化物（27）之后，通过蚀刻一部分氧化物来显示电池区域和第二层间膜上的插塞，并且在第一EBR（边缘除去线）（300）形成在周边地区。第二EBR线（400）通过使晶片上比第一EBR线更内侧的多晶硅膜（28）图案化而形成。并且，通过CMP（化学机械抛光）方法在研磨多晶硅膜后露出氧化物之后除去氧化物形成底部电极。

6. 发明公开

KR1020010063704A 반도체 소자 제조방법 失效
标题翻译：制造半导体器件的方法
公开(公告)号：KR1020010063704A
公开(公告)日：2001-07-09
申请号：KR1019990061780
申请日：1999-12-24
申请人： 에스케이하이닉스 주식회사
发明人： 안기철 , 김춘환
IPC分类号： H01L21/283
摘要： PURPOSE: A forming method of semiconductor device is provided to prevent short circuit of a bit line with a metal contact plug by restraining the bit line shift. CONSTITUTION: A number of gate electrodes(24) are formed on a semiconductor substrate(100). Each of the gate electrodes(24) includes the first polysilicon film(21), the first silicide film(22) and the first mask oxide film(23). Gate spacers(25) are formed at sides of the gate electrodes(24). The first interlayer insulation film(26) is formed on the whole upper surface including the gate electrodes and the gate spacers(25). An anti-shift film(27) is formed on the first interlayer insulation film(26). A number of bit lines(31) are formed on the whole surface, and bit line spacers(32) are formed at sides of the bit lines(31). Each of the bit lines(31) includes the second polysilicon film(28), the second silicide film(29) and the second mask oxide film(30).
摘要翻译：目的：提供半导体器件的形成方法，以通过限制位线移位来防止与金属接触插塞的位线短路。构成：在半导体衬底（100）上形成多个栅电极（24）。每个栅电极（24）包括第一多晶硅膜（21），第一硅化物膜（22）和第一掩模氧化物膜（23）。栅极间隔物（25）形成在栅电极（24）的侧面。第一层间绝缘膜（26）形成在包括栅极电极和栅极间隔物（25）的整个上表面上。在第一层间绝缘膜（26）上形成防反射膜（27）。在整个表面上形成多个位线（31），位线间隔件（32）形成在位线（31）的侧面。每个位线（31）包括第二多晶硅膜（28），第二硅化物膜（29）和第二掩模氧化物膜（30）。

7. 发明公开

KR1020010003775A 반도체 소자의 제조 방법 失效
标题翻译：制造半导体器件的方法
公开(公告)号：KR1020010003775A
公开(公告)日：2001-01-15
申请号：KR1019990024210
申请日：1999-06-25
申请人： 에스케이하이닉스 주식회사
发明人： 안기철
IPC分类号： H01L21/304
摘要： PURPOSE: A method for manufacturing a semiconductor device is provided to prevent a lower pattern from being exposed in an edge bead removal region in a chemical mechanical polishing process, by controlling a line width of the edge bead removal region when semiconductor devices are formed in a cell region and a peripheral circuit region. CONSTITUTION: A width of an edge bead removal line is generated in a mask process for forming semiconductor devices in a cell region and a peripheral circuit region. The width of the edge bead removal line is made smaller than an edge bead removal line manufactured in a prior process.
摘要翻译：目的：提供一种制造半导体器件的方法，用于通过在半导体器件形成时控制边缘珠去除区域的线宽度来防止在化学机械抛光工艺中在边缘珠去除区域中暴露下部图案单元区域和外围电路区域。构成：在用于在单元区域和外围电路区域中形成半导体器件的掩模工艺中产生边缘焊道移除线的宽度。边缘焊道移除线的宽度小于在先前工艺中制造的边缘焊道移除线。

8. 发明公开

KR1020000003985A 메모리와 논리소자가 혼재된 반도체소자 제조방법 无效
标题翻译：制造半导体器件嵌入式存储器和逻辑器件的方法
公开(公告)号：KR1020000003985A
公开(公告)日：2000-01-25
申请号：KR1019980025293
申请日：1998-06-30
申请人： 에스케이하이닉스 주식회사
发明人： 안기철
IPC分类号： H01L27/108
摘要： PURPOSE: A method of fabricating semiconductor device embedded memory and logic device is provided to be easy of depth measurement and simplify a process. CONSTITUTION: A method of fabricating semiconductor device embedded memory and logic device, said method comprising steps of; forming field oxide layer and gate at predetermined area of silicon substrate; forming etch stopping layer on overall substrate; selectively removing the etch stopping layer formed on memory area; forming capacitor in the memory area; forming oxide layer on overall substrate; removing selectively the oxide layer in logic device area; removing the etch stopping layer in the logic device area; and forming silicide layer on predetermined are of the logic device area.
摘要翻译：目的：提供一种制造半导体器件嵌入式存储器和逻辑器件的方法，以便于深度测量并简化工艺。构成：一种制造半导体器件嵌入式存储器和逻辑器件的方法，所述方法包括以下步骤：在硅衬底的预定区域形成场氧化物层和栅极; 在整个基板上形成蚀刻停止层; 选择性地去除在存储区域上形成的蚀刻停止层; 在存储区中形成电容器; 在整个基板上形成氧化物层; 在逻辑器件区域中选择性地去除氧化物层; 去除逻辑器件区域中的蚀刻停止层; 并且在预定的上形成硅化物层是逻辑器件区域。

9. 发明公开

KR1020000003232A 반도체메모리소자의캐패시터형성방법 失效
标题翻译：制造半导体器件的方法
公开(公告)号：KR1020000003232A
公开(公告)日：2000-01-15
申请号：KR1019980024427
申请日：1998-06-26
申请人： 에스케이하이닉스 주식회사
发明人： 안기철 , 이상익 , 소홍선
IPC分类号： H01L21/027
摘要： PURPOSE: The method can prevent that a polysilicon film remains on the bottom of a sacrificial film(27) formed to fill an open aperture and acts as a pollution source, in the process of forming a bottom electrode of a capacitor by forming the open aperture. CONSTITUTION: The method can solve the problem resulting from that a burying oxide film remains in a peripheral circuit region by omitting the process of forming the burying oxide film to bury an open aperture, by comprising the steps of: forming the open aperture to form a bottom electrode(28A) pattern of a capacitor in a cell region; forming a polysilicon film(28) for bottom electrode on the whole structure; removing the polysilicon film for bottom electrode formed on the peripheral circuit region by selective etching process; and forming the bottom electrode pattern by polishing the polysilicon film for bottom electrode on the cell region.
摘要翻译：目的：该方法可以防止在通过形成开孔来形成电容器的底电极的过程中，多晶硅膜保留在形成为填充开孔的牺牲膜（27）的底部并用作污染源。构成：该方法可以解决由于通过省略形成埋入氧化物膜以掩埋开口的过程而将掩埋氧化物膜残留在外围电路区域中的问题，包括以下步骤：形成开孔以形成电池区域中的电容器的底部电极（28A）图案; 在整个结构上形成用于底部电极的多晶硅膜（28）; 通过选择性蚀刻工艺除去形成在外围电路区域上的底部电极的多晶硅膜; 以及通过在单元区域上研磨用于底部电极的多晶硅膜来形成底部电极图案。

10. 发明授权

KR100212004B1 반도체 소자의 평탄화 방법 失效
标题翻译：半导体器件规划方法
公开(公告)号：KR100212004B1
公开(公告)日：1999-08-02
申请号：KR1019960009073
申请日：1996-03-29
申请人： 에스케이하이닉스 주식회사
发明人： 안기철 , 이승무
IPC分类号： H01L21/768
摘要： 본 발명은 금속층 패턴이 형성된 구조에 테트라 메칠 암모늄 하이드록사이드(TMAH) 알칼리 용액을 이용한 세정 공정을 실시하여 후속 공정인 오존 테오스계 산화막의 이상 증착 현상을 방지하므로써 소자의 평탄화를 개선시킬 수 있는 반도체 소자의 평탄화 방법이 개시된다.

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