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71. 发明授权

KR101160961B1 두 채널간에 증폭기 공유기법을 이용한 ＡＤＣ有权
标题翻译：双通道模拟数字转换器共享放大器
公开(公告)号：KR101160961B1
公开(公告)日：2012-06-29
申请号：KR1020110038934
申请日：2011-04-26
申请人： 서강대학교산학협력단
发明人： 이승훈 , 명성민 , 김효진
IPC分类号： H03M1/12
CPC分类号： H03M1/122 , H03M1/002 , H03M1/361 , H03M2201/2216 , H03M2201/62
摘要： PURPOSE: An ADC(Analog to Digital Converter) sharing amplifiers between two channels is provided to additionally reduce the number of pre-amplifiers by 50% by applying an interpolation method to flash ADCs. CONSTITUTION: An ADC(Analog to Digital Converter) includes a SHA(Sample-and-Hold Amplifier)(110), a MDAC1(Multiplying Digital to Analog Converter)(120), a MDAC2(130), a FLASH1(140), a FLASH2(150), and a FLASH3(160). The ADC includes an on-chip reference current and voltage generator(170), a digital correction circuit(180) including a divider, and a clock generator(190). Input terminals of the SHA, the MDAC1, and the MDAC2 are composed of two channels. Two channels share only one amplifier. The FLASH1, the FLASH2, and the FLASH3 are composed of a pre-amplifier and a latch. The FLASH1, the FLASH2, and the FLASH3 reduce the number of pre-amplifiers by 50% to consecutively process signals outputted from the SHA, the MDAC1, and the MDAC2 by sharing one pre-amplifier having a DDA(Differential Difference Amplifier) structure.
摘要翻译：目的：提供两个通道之间的ADC（模/数转换器）共享放大器，通过对闪存ADC应用内插方法，将前置放大器的数量额外减少50％。组件：ADC（模数转换器）包括一个SHA（采样保持放大器）（110），一个MDAC1（乘法数模转换器）（120），一个MDAC2（130），一个FLASH1（140） FLASH2（150）和FLASH3（160）。 ADC包括片上参考电流和电压发生器（170），包括分频器的数字校正电路（180）和时钟发生器（190）。 SHA，MDAC1和MDAC2的输入端子由两个通道组成。两个通道只共享一个放大器。 FLASH1，FLASH2和FLASH3由前置放大器和锁存器组成。 FLASH1，FLASH2和FLASH3通过共享一个具有DDA（差分放大器）结构的前置放大器，将前置放大器的数量减少了50％，以连续地处理从SHA，MDAC1和MDAC2输出的信号。

72. 发明公开

KR1020120024278A 레인지―스케일링 기법이 적용된 파이프라인 구조의 ＡＤＣ有权
标题翻译：使用范围调整方法的模拟数字转换器
公开(公告)号：KR1020120024278A
公开(公告)日：2012-03-14
申请号：KR1020100087100
申请日：2010-09-06
申请人： 서강대학교산학협력단
发明人： 이승훈
IPC分类号： H03M1/12
CPC分类号： H03M1/361 , H03M1/002 , H03M1/1205 , H03M1/18 , H03M2201/2216 , H03M2201/62
摘要： PURPOSE: An analog-to-digital converter using a range-scaling method is provided to reduce the number of a reference voltage driving circuit to the half without additional correction on reference voltage using the single reference voltage. CONSTITUTION: Range scaling on the input analog signal of an ADC(Analog-to-Digital Converter) of a pipeline structure is operated using only single reference voltage. An SHA(Sample-and-Hold Amplifier) of an input terminal of the ADC is removed from the input terminal of the ADC. The input analog signal is directly applied on the sampling capacitor of the FLASH1 ADC of input terminal and the MDAC1 of the input terminal. The sampling switch of the FLASH1 ADC and MDAC1 comprise a gate - bootstrapping circuit. The FLASH1 ADC is formed using only a plurality of latches.
摘要翻译：目的：提供使用范围缩放方法的模数转换器，以将参考电压驱动电路的数量减少到一半，而无需使用单个参考电压对参考电压进行附加校正。规定：管道结构的ADC（模数转换器）的输入模拟信号的范围缩放仅使用单个参考电压进行操作。 ADC的输入端子的SHA（采样保持放大器）从ADC的输入端子被去除。输入模拟信号直接施加在输入端子FLASH1 ADC的采样电容和输入端子的MDAC1上。 FLASH1 ADC和MDAC1的采样开关包括一个门自举电路。 FLASH1 ADC仅使用多个锁存器形成。

73. 发明授权

KR101111638B1 ＣＤＳ를 이용한 ＡＤＣ 및 이를 이용한 ＡＤ 변환방법 有权
标题翻译： ADC采用相关双采样及其转换方法
公开(公告)号：KR101111638B1
公开(公告)日：2012-02-14
申请号：KR1020110056421
申请日：2011-06-10
申请人： 동국대학교 산학협력단
发明人： 송민규 , 조규익 , 김대윤
IPC分类号： H03M1/12 , H04N5/3745
CPC分类号： H03M1/56 , H03M1/002 , H03M1/12 , H03M3/02 , H03M2201/2311 , H03M2201/62 , H04N5/3745
摘要： PURPOSE: An analog-to-digital converter using correlated double sampling and an analog-to-digital converting method using the same are provided to reduce switching noise and power consumption by satisfying the number of bits to count the dissemination of reset signals. CONSTITUTION: A CMOS image sensor comprises a pixel array(1), a comparator(2), a CDS processing unit(3), an N-bit counter(6), and a latch unit(7). The CMOS image sensor comprises a vertical scanning circuit(8), a horizontal scan circuit(9), a lamp signal generator(10), an output circuit(11), and a control signal generating unit(12). The CDS processing unit comprises a CDS counter(4) and an and-logic(5) The control signal generating unit creates signals to control a vertical scanning circuit, a horizontal scanning circuit, a CDS processing unit, an N bit counter.
摘要翻译：目的：提供使用相关双采样的模数转换器和使用其的模数转换方法，以通过满足计数复位信号传播的位数来减少开关噪声和功耗。构成：CMOS图像传感器包括像素阵列（1），比较器（2），CDS处理单元（3），N位计数器（6）和锁存单元（7）。 CMOS图像传感器包括垂直扫描电路（8），水平扫描电路（9），灯信号发生器（10），输出电路（11）和控制信号生成单元（12）。 CDS处理单元包括CDS计数器（4）和逻辑电路（5）。控制信号产生单元产生信号以控制垂直扫描电路，水平扫描电路，CDS处理单元，N位计数器。

74. 发明公开

KR1020110011532A 이득제어 기능을 갖는 능동형 ＲＣ 적분기 및 연속시간 시그마-델타 변조기 有权
标题翻译：主动RC积分器和具有增益控制功能的连续时间信号调制器
公开(公告)号：KR1020110011532A
公开(公告)日：2011-02-08
申请号：KR1020100056911
申请日：2010-06-16
申请人： 한국전자통신연구원
发明人： 김이경 , 조민형 , 권종기
IPC分类号： H03M3/02 , H03M1/66 , H03G3/20
CPC分类号： H03M3/32 , H03M3/39 , H03M2201/62 , H03M2201/932
摘要： PURPOSE: An active type RC integrator and a continuous time sigma-delta modulator are provided to improve the gain of an active type RC integrator by turning on a switch. CONSTITUTION: A first base resistor(RBASE1) is connected between a first input node and the positive input terminal of an amplifier. A second base resistor(RBASE2) is connected between a second input node and the negative input terminal of the amplifier. A first resistor part(1) is connected between the second input node and the positive input terminal of the amplifier. A second resistor part(2) is connected between the first input node and the negative input terminal of the amplifier. A first switch(SWDUM1) switches on and off the first base resistor. A second switch(SWDUM2) switches on and off the second base resistor. The gain of an input signal is controlled according to the input resistance varied by the first resistor part and the second resistor part.
摘要翻译：目的：提供有源型RC积分器和连续时间Σ-Δ调制器，通过开启开关来提高有源型RC积分器的增益。构成：第一个基极电阻（RBASE1）连接在放大器的第一个输入节点和正极输入端子之间。第二基极电阻（RBASE2）连接在放大器的第二输入节点和负输入端之间。第一电阻器部分（1）连接在第二输入节点和放大器的正输入端之间。第二电阻器部分（2）连接在放大器的第一输入节点和负输入端之间。第一开关（SWDUM1）打开和关闭第一个基极电阻。第二个开关（SWDUM2）打开和关闭第二个基极电阻。根据由第一电阻器部件和第二电阻器部件变化的输入电阻来控制输入信号的增益。

75. 发明公开

KR1020100123103A 디지털 아날로그 변환기 有权
标题翻译：数字到模拟转换器
公开(公告)号：KR1020100123103A
公开(公告)日：2010-11-24
申请号：KR1020090042136
申请日：2009-05-14
申请人： 주식회사 실리콘웍스
发明人： 김기덕 , 조규형 , 전용준 , 전진용 , 정승철 , 이성우
IPC分类号： H03M1/12 , H03M1/66
CPC分类号： H03M1/66 , H03M1/06 , H03M2201/3194 , H03M2201/61 , H03M2201/62 , H03M2201/814
摘要： PURPOSE: By it partials, medially eliminating error toward the input of digital data the digital to analog converter enhances the accuracy of the digital to analog converter. CONSTITUTION: It distributes to the before distribution class field of the plurality having the size of the reference current decision by discussion search the reference current which the electric current distribution part(20) is provided from the reference current route of supply source. According to the rotating exchange part is the control signal, the route of the before distribution class field having the route of being exchanged as described above is re-exchanged.
摘要翻译：目的：通过内部消除数字数据输入的错误，数模转换器提高了数模转换器的精度。构成：通过讨论从供应源的参考电流路径提供电流分配部（20）的参考电流，分配到具有参考电流决定大小的多个的前分发类场中。根据旋转交换部分是控制信号，重新交换具有如上所述交换路线的分配前场的路线。

76. 发明公开

KR1020100027278A 문턱 전압 변화를 이용한 아날로그 디지털 컨버터 无效
标题翻译：使用阈值电压变化的模拟数字转换器
公开(公告)号：KR1020100027278A
公开(公告)日：2010-03-11
申请号：KR1020080086126
申请日：2008-09-02
申请人： 충북대학교 산학협력단
发明人： 김남수 , 최지원
IPC分类号： H03M1/12 , H03M1/16
CPC分类号： H03M1/16 , H03M1/002 , H03M1/18 , H03M2201/62 , H03M2201/814
摘要： PURPOSE: An analog to digital converter using threshold voltage variation is provided to simplify a configuration of a circuit by performing a comparison operation with a simple structure. CONSTITUTION: A switching inverter array(120) is comprised of a plurality of CMOS inverters. The switching inverter array receives an analog input voltage as an input signal. An encoder(150) generates a digital signal by encoding the output signals of the CMOS inverters. Each CMOS inverter has a different switching threshold voltage. The CMOS inverters is comprised of a PMOS transistor and an NMOS transistor including a gate insulation layer. The PMOS transistor and the NMOS transistor have different thicknesses according to each CMOS inverter.
摘要翻译：目的：提供使用阈值电压变化的模数转换器，通过简单的结构执行比较操作来简化电路的配置。构成：开关逆变器阵列（120）由多个CMOS反相器构成。开关逆变器阵列接收模拟输入电压作为输入信号。编码器（150）通过对CMOS反相器的输出信号进行编码来产生数字信号。每个CMOS反相器具有不同的开关阈值电压。 CMOS反相器由PMOS晶体管和包括栅极绝缘层的NMOS晶体管组成。根据每个CMOS反相器，PMOS晶体管和NMOS晶体管具有不同的厚度。

77. 发明公开

KR1020090116942A 적은 수의 트랙 앤 홀드 회로들을 이용하는폴딩-인터폴레이팅 아날로그-디지털 변환기 无效
标题翻译：使用较少的跟踪和保持电路对数字转换器进行折叠插值模拟
公开(公告)号：KR1020090116942A
公开(公告)日：2009-11-12
申请号：KR1020080042774
申请日：2008-05-08
申请人： 연세대학교 산학협력단 , 동국대학교 산학협력단
发明人： 김재석 , 송민규 , 정민호 , 문준호 , 이두복
IPC分类号： H03M1/12
CPC分类号： H03M1/368 , H03M1/002 , H03M1/121 , H03M2201/2208 , H03M2201/62 , H03M2201/93
摘要： PURPOSE: A folding-interpolating analog to a digital converter using a less track-and-hold circuit is provided to reduce a circuit area and power consumption by connecting a track-and-hold circuit at the end of a folding block stage. CONSTITUTION: In a folding-interpolating analog to a digital converter using a less track-and-hold circuit, a preamplifier stage(210) amplifies an analog signal by using a plurality of reference voltages and produces a plurality of input signals. A folding block stage(230) folds the input signals according to a predetermined folding rate. The folding block stage produces a plurality of folding signals. The track-and-hold stage(250) is arranged at the backend of the folding block stage by receiving the outputs of the folding block stage. The track-and-hold stage track and holds the folding signals.
摘要翻译：目的：提供使用较少轨道和保持电路的数字转换器的折叠内插模拟，以通过在折叠块级结束时连接跟踪和保持电路来减少电路面积和功耗。构成：在使用较少轨道和保持电路的数字转换器的折叠内插模拟中，前置放大器级（210）通过使用多个参考电压来放大模拟信号并产生多个输入信号。折叠台阶（230）根据预定的折叠速率折叠输入信号。折叠台阶产生多个折叠信号。跟踪保持阶段（250）通过接收折叠块阶段的输出而被布置在折叠块阶段的后端。跟踪和保持阶段跟踪并保存折叠信号。

78. 发明公开

KR1020090109455A 잔류전압 증폭기 및 이를 이용한 아날로그/디지털 변환기 失效
标题翻译：使用放大器和模拟数字转换器
公开(公告)号：KR1020090109455A
公开(公告)日：2009-10-20
申请号：KR1020080056410
申请日：2008-06-16
申请人： 한국과학기술원
发明人： 류승탁 , 이창교 , 조상현
IPC分类号： H03M1/12
CPC分类号： H03M1/14 , H03M1/002 , H03M1/06 , H03M2201/2291 , H03M2201/6142 , H03M2201/62 , H03M2201/81
摘要： PURPOSE: A residue amplifier and an analog digital converter using the same are provided to improve dynamic range of input signal under the lowered source voltage condition. CONSTITUTION: A residual voltage amplifier(210) comprises an operational amplifier, and a capacitor circuit. The operational amplifier is connected to a first internal voltage. The capacitor circuit is connected to another input terminal of the operational amplifier. The capacitor circuit includes a first capacitor(C1), a second capacitor(C2), and a third capacitor. The first capacitor is connected to another input terminal of the operational amplifier. The second capacitor is connected to the common terminal of the first capacitor. The third capacitor is connected to the other input terminal of the operational amplifier. The third capacitor is connected to the output terminal of the operational amplifier.
摘要翻译：目的：提供残留放大器和使用其的模拟数字转换器，以改善在较低的源电压条件下的输入信号的动态范围。构成：残余电压放大器（210）包括运算放大器和电容器电路。运算放大器连接到第一内部电压。电容电路连接到运算放大器的另一输入端。电容器电路包括第一电容器（C1），第二电容器（C2）和第三电容器。第一电容器连接到运算放大器的另一个输入端。第二电容器连接到第一电容器的公共端。第三个电容连接到运算放大器的另一个输入端。第三电容器连接到运算放大器的输出端。

79. 发明公开

KR1020090072053A 단일 증폭기 아키텍처를 이용한 타임 인터리브 시그마-델타변조기 失效
标题翻译：使用单放大器架构的时间隔离的SIGMA-DELTA调制器
公开(公告)号：KR1020090072053A
公开(公告)日：2009-07-02
申请号：KR1020070140028
申请日：2007-12-28
申请人： 연세대학교 산학협력단
发明人： 채영철 , 이인희 , 권민호 , 한건희
IPC分类号： H03M3/02
CPC分类号： H03M3/392 , H03M3/32 , H03M2201/62 , H03M2201/71
摘要： A time-interleaved sigma-delta modulator using a single amplifier architecture is provided to implement the modulator with a high dynamic range by increasing an effective sampling frequency. A combiner(210) amplifies and adds a signal inputted from the outside, a fed back signal after quantization, and the fed back signal without the quantization. One or more integrating units delays the signal outputted from the combiner as much as the predetermined clock and multiplies the delayed signal by a constant coefficient. The integrating unit adds the inputted value to the signal and provides the added signal as the fed back signal without quantization to the combiner. A quantizer(220) quantizes the signal outputted from the combiner. A clock delay unit(225) delays the signal outputted from the quantizer and provides the delayed signal as the fed back signal after quantization.
摘要翻译：提供了使用单放大器架构的时间交错式Σ-Δ调制器，以通过增加有效采样频率来实现具有高动态范围的调制器。组合器（210）将从外部输入的信号，量化后的反馈信号和反馈信号放大并相加而不进行量化。一个或多个积分单元将从组合器输出的信号延迟到预定时钟，并将延迟的信号乘以恒定系数。积分单元将输入的值添加到信号中，并将相加的信号作为反馈信号提供给组合器而不进行量化。量化器（220）量化从组合器输出的信号。时钟延迟单元（225）延迟从量化器输出的信号，并且在量化之后提供延迟的信号作为反馈信号。

80. 发明公开

KR1020080091536A 부분 랜덤화를 통한 디지털 아날로그 변환 설계 방법 无效
标题翻译：具有局部随机动态元件匹配的10BIT 200MHZ DAC
公开(公告)号：KR1020080091536A
公开(公告)日：2008-10-14
申请号：KR1020070034492
申请日：2007-04-09
申请人： 인하대학교 산학협력단
发明人： 원태영 , 김영규 , 양승수 , 박순열
IPC分类号： H03M1/66
CPC分类号： H03M1/66 , H03M1/06 , H03M2201/62 , H03M2201/814 , H03M2201/932
摘要： A DAC using partial randomization is provided to increase an operation speed of the DAC by reducing glitch energy by randomly selecting a current source and a significant data signal line. A DAC(Digital to Analog Converter) includes plural decoding layers having respective current sources. When the current source is randomly selected, glitch energy is decreased. The number of layers is determined for a layout size of the DAC and the reduction of the glitch energy. The number of layers is optimized according to the bit number of the DAC, so that the linearity of the DAC is guaranteed. Random signals required for the respective layers are obtained from a linear feedback shift register(LFSR).
摘要翻译：提供使用部分随机化的DAC以通过随机选择电流源和有效数据信号线来减少毛刺能量来增加DAC的操作速度。 DAC（数模转换器）包括具有各自电流源的多个解码层。当电流源随机选择时，毛刺能量下降。针对DAC的布局尺寸和毛刺能量的减少确定层数。根据DAC的位数优化层数，从而保证DAC的线性度。从线性反馈移位寄存器（LFSR）获得各层所需的随机信号。

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