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1. 发明公开

KR1020130042910A 2-스텝 아날로그-디지털 변환 회로, 이의 동작 방법, 및 상기 2-스텝 아날로그-디지털 변환 회로를 포함하는 장치들 有权
标题翻译： 2步模拟数字转换电路，其操作方法和具有该步骤的器件
公开(公告)号：KR1020130042910A
公开(公告)日：2013-04-29
申请号：KR1020110107061
申请日：2011-10-19
申请人： 삼성전자주식회사
发明人： 박유진 , 유귀성 , 임승현
IPC分类号： H03M1/46
CPC分类号： H03M1/16 , H03M1/123 , H03M1/56 , H04N5/374 , H04N5/3742 , H04N5/378 , H03M1/462
摘要： PURPOSE: A 2- step analog to digital converter circuit, an operating method thereof, and devices including the 2- step analog to digital converter circuit are provided to improve processing speed at high bit resolution. CONSTITUTION: A comparator(220) outputs a comparison signal(COMP) comparing a ramp signal(RAMP) with an input signal(INPUT). An upper bit counter(240) outputs upper bit values(UB) corresponding to the first time interval of the first edge of a clock signal(CLK). A pulse residue conversion part(260) outputs lower bit values(LB) corresponding to the second time interval between the first edge and a state transition timing. The pulse residue conversion part comprises a voltage generating circuit and an analog to digital converter. The voltage generating circuit outputs voltage proportional to a third time interval between the clock signal and a second edge. [Reference numerals] (240) Upper bit counter; (260) Pulse residue conversion part;
摘要翻译：目的：提供2步模数转换器电路及其操作方法，以及包括2步模数转换器电路的器件，以提高高位分辨率下的处理速度。构成：比较器（220）输出将斜坡信号（RAMP）与输入信号（INPUT）进行比较的比较信号（COMP）。高位计数器（240）输出与时钟信号（CLK）的第一边沿的第一时间间隔相对应的高位值（UB）。脉冲残余转换部分（260）输出与第一边缘和状态转换定时之间的第二时间间隔相对应的较低位值（LB）。脉冲残余转换部分包括电压产生电路和模数转换器。电压产生电路输出与时钟信号和第二边沿之间的第三时间间隔成比例的电压。（附图标记）（240）高位计数器（260）脉冲残留转换部分;

2. 发明公开

KR1020040033596A 아날로그-디지털 변환기의 디지털 오류 교정 방법 失效
标题翻译：用于校正模拟/数字转换器的数字错误的方法
公开(公告)号：KR1020040033596A
公开(公告)日：2004-04-28
申请号：KR1020020062748
申请日：2002-10-15
申请人： 한국전자통신연구원
发明人： 이승철 , 유현규 , 김경수 , 김종대
IPC分类号： H03M1/12
CPC分类号： H03M1/16 , H03M2201/65
摘要： PURPOSE: A method for correcting a digital error of an analog/digital converter is provided to simplify an error correction process and minimize the power consumption by using a characteristic of a folding signal to divide a region of low bits and correcting errors of high bits according to the divided regions. CONSTITUTION: A low bit coding region is divided into four regions according to an odd number state and an even number state of predicting high bits. A coding process for low bits is performed. A coded result of the low bits is compared with the state of predictive high bits. The sum of the coded low bits and the predicting high bits is outputted if the coded result of the low bits corresponds to the state of predictive high bits. The sum of the coded low bits and the corrected high bits is outputted if the coded result of the low bits does not correspond to the state of predictive high bits.
摘要翻译：目的：提供一种用于校正模拟/数字转换器的数字误差的方法，以简化误差校正处理，并通过使用折叠信号的特征来最小化功率消耗，以分割低位的区域并校正高位的误差，到分区。构成：根据奇数状态和预测高位的偶数状态，将低位编码区划分为四个区域。执行低位的编码处理。将低位的编码结果与预测高位的状态进行比较。如果低位的编码结果对应于预测高位的状态，则输出编码的低位和预测高位的和。如果低位的编码结果与预测高位的状态不对应，则输出编码的低位和校正的高位的和。

3. 发明授权

KR101647102B1 2-스텝 아날로그-디지털 변환 회로, 이의 동작 방법, 및 상기 2-스텝 아날로그-디지털 변환 회로를 포함하는 장치들 有权
标题翻译： 2- 2- 2-步数转换电路的操作方法及其设备
公开(公告)号：KR101647102B1
公开(公告)日：2016-08-10
申请号：KR1020110107061
申请日：2011-10-19
申请人： 삼성전자주식회사
发明人： 박유진 , 유귀성 , 임승현
IPC分类号： H03M1/46
CPC分类号： H03M1/16 , H03M1/123 , H03M1/56 , H04N5/374 , H04N5/3742 , H04N5/378
摘要： 2-스텝아날로그-디지털변환회로와 2-스텝아날로그-디지털변환방법이개시된다. 2-스텝아날로그-디지털변환회로는램프신호와입력신호를비교하고비교신호를출력하는비교기, 클락신호에응답하여, 상기램프신호의생성시점과, 상기비교신호의상태천이시점의바로이전상기클락신호의제1 에지(edge)와의제1 시간간격에대응하는상위비트값들을출력하는상위비트카운터, 및상기제1 에지와상기상태천이시점과의제2 시간간격에대응하는하위비트값들을출력하는펄스레지듀(residue) 변환부를포함한다. 2-스텝아날로그-디지털변환방법은램프신호와입력신호를비교하고비교신호를출력하는단계, 상기램프신호의생성시점과, 상기비교신호의상태천이시점의바로이전클락신호의제1 에지와의제1 시간간격을카운트한값을상위비트값들로서출력하는단계, 및상기제1 에지와상기상태천이시점과의제2 시간간격에대응하는하위비트값들을출력하는단계를포함한다.

4. 发明公开

KR1020100027278A 문턱 전압 변화를 이용한 아날로그 디지털 컨버터 无效
标题翻译：使用阈值电压变化的模拟数字转换器
公开(公告)号：KR1020100027278A
公开(公告)日：2010-03-11
申请号：KR1020080086126
申请日：2008-09-02
申请人： 충북대학교 산학협력단
发明人： 김남수 , 최지원
IPC分类号： H03M1/12 , H03M1/16
CPC分类号： H03M1/16 , H03M1/002 , H03M1/18 , H03M2201/62 , H03M2201/814
摘要： PURPOSE: An analog to digital converter using threshold voltage variation is provided to simplify a configuration of a circuit by performing a comparison operation with a simple structure. CONSTITUTION: A switching inverter array(120) is comprised of a plurality of CMOS inverters. The switching inverter array receives an analog input voltage as an input signal. An encoder(150) generates a digital signal by encoding the output signals of the CMOS inverters. Each CMOS inverter has a different switching threshold voltage. The CMOS inverters is comprised of a PMOS transistor and an NMOS transistor including a gate insulation layer. The PMOS transistor and the NMOS transistor have different thicknesses according to each CMOS inverter.
摘要翻译：目的：提供使用阈值电压变化的模数转换器，通过简单的结构执行比较操作来简化电路的配置。构成：开关逆变器阵列（120）由多个CMOS反相器构成。开关逆变器阵列接收模拟输入电压作为输入信号。编码器（150）通过对CMOS反相器的输出信号进行编码来产生数字信号。每个CMOS反相器具有不同的开关阈值电压。 CMOS反相器由PMOS晶体管和包括栅极绝缘层的NMOS晶体管组成。根据每个CMOS反相器，PMOS晶体管和NMOS晶体管具有不同的厚度。

5. 发明公开

KR1020150041515A 전압 보간 회로 및 디지털-아날로그 변환기 审中-实审
标题翻译：电压插值电路和数字模拟转换器
公开(公告)号：KR1020150041515A
公开(公告)日：2015-04-16
申请号：KR1020130120134
申请日：2013-10-08
申请人： 주식회사 실리콘웍스
发明人： 김현식
IPC分类号： G09G3/36 , H03M1/16
CPC分类号： H03M1/0621 , G09G3/36 , H03M1/16 , H03M1/66 , H03M2201/194 , H03M2201/8152
摘要： 전압보간회로는복수의전원터미널들; 복수의커패시터들; 및제어신호에따라상기커패시터들및 상기복수의전원터미널들의직렬연결과상기커패시터들의병렬연결을교번적으로수행하는스위칭부를포함한다. 따라서, 전압보간회로및 디지털-아날로그변화회로는복수의커패시터를반복적으로직렬및 병렬연결하여보간회로내 소자간소자간부정합(mismatching)과기생소자와무관하게균일한전압을생성할수 있다.
摘要翻译：提供电压内插电路和数模转换器（DAC）。电压内插电路包括多个电源端子; 多个电容器; 以及开关单元，根据控制信号，串联并联并联电容器和电源端子。因此，不管元件之间的不匹配和电压内插电路内的寄生元件如何，内插电路和DAC可以通过串联并联地重复连接电容器来产生均匀的电压。

6. 发明公开

KR1020100064696A 디지털-아날로그 변환 회로 및 이를 포함하는 컬럼 드라이버 有权
标题翻译：具有数字模拟转换电路和列驱动器
公开(公告)号：KR1020100064696A
公开(公告)日：2010-06-15
申请号：KR1020080123253
申请日：2008-12-05
申请人： 삼성전자주식회사
发明人： 조규형 , 전용준 , 이형민 , 이성우 , 최윤경 , 김형래
IPC分类号： H03M1/16 , H03M1/66
CPC分类号： H03M1/664 , G09G3/20 , G09G2310/027 , G09G2310/0272 , G09G2310/0291 , H03M1/662 , H03M1/68 , H03M1/16 , H03M1/66
摘要： PURPOSE: A digital-analog conversion circuit and a column driver having the same are provided to minimize the area of a buffer amplifier by performing DC-AC conversion based on a bias current which is varied according to a lower bit data. CONSTITUTION: A buffer amplifier(50) comprises an add / output circuit, a first input terminals(54,55), a second input terminal(53,56), and a current DAC(Digital Analog Converter)(51). The add / output circuit adds the output current of the first and second output current and outputs the added current. The current DC-AC convertor supplies a bias current to the first and the second output terminal. A first reference gamma voltage is inputted to the first input terminal. A second reference gamma voltage is inputted to the second input terminal.
摘要翻译：目的：提供数模转换电路和具有该数字模拟转换电路的列驱动器，以通过基于根据较低位数据而变化的偏置电流进行DC-AC转换来最小化缓冲放大器的面积。构成：缓冲放大器（50）包括加法/输出电路，第一输入端（54,55），第二输入端（53,56）和电流DAC（数字模拟转换器）51。添加/输出电路将第一和第二输出电流的输出电流相加，并输出相加的电流。当前的DC-AC转换器向第一和第二输出端提供偏置电流。第一参考伽玛电压被输入到第一输入端。第二参考伽玛电压被输入到第二输入端。

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