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71. 发明公开

KR1020150054942A 기준 셀 보수 체계 审中-实审
标题翻译：参考细胞修复方案
公开(公告)号：KR1020150054942A
公开(公告)日：2015-05-20
申请号：KR1020157009094
申请日：2013-09-13
申请人： 퀄컴 인코포레이티드
发明人： 김,정필 , 김,태현 , 김,성률
IPC分类号： G11C29/00 , G11C11/16
CPC分类号： G11C11/16 , G11C11/165 , G11C11/1673 , G11C29/787 , G11C29/832
摘要： 자기랜덤액세스메모리(MRAM)에서, 기준비트셀들의수많은어레이들은, 이들의각각의비트라인들을병합된기준노드에결합시킴으로써함께결합된다. 각각의기준비트라인들과, 병합된기준노드사이에결합된패스게이트회로소자는, 기준비트라인들중 하나또는그 초과의것을병합된기준노드에선택적으로결합하고그리고병합된기준노드로부터선택적으로결합해제하도록구성된다. 패스게이트회로소자는패스게이트회로소자에결합된 OTP(one-time programmable) 디바이스들을프로그래밍함으로써제어가능하다. OTP(one-time programmable) 디바이스들은, 결함있는기준비트셀들의어레이들을병합된기준노드로부터결합해제하고또는기준노드로의커플링을위해서기준비트셀들의리던던트어레이들간에선택하도록프로그래밍될수 있다.

72. 发明公开

KR1020150030430A 셀프 리페어 장치 审中-实审
标题翻译：自修装置
公开(公告)号：KR1020150030430A
公开(公告)日：2015-03-20
申请号：KR1020130109649
申请日：2013-09-12
申请人： 에스케이하이닉스 주식회사
发明人： 심영보
IPC分类号： G11C29/12 , G11C29/04
CPC分类号： G11C29/787 , G11C29/808
摘要： The present invention relates to a self-repair device and, more particularly, to a technology for improving repair efficiency of a semiconductor device including a fuse array and reducing the area of the semiconductor device. The self-repair device includes: an array rupture electrical fuse (ARE) array unit configured to store fail addresses in a plurality of fuse sets; an ARE control unit configured to control a repair operation of the fuse sets according to the fail addresses, compare the fail addresses and determine a fail state in a test mode; and a redundancy unit configured to store fuse data of the fail addresses applied by the ARE array unit, compare an input address with the fail addresses and control row and column redundancy operations.
摘要翻译：本发明涉及自修复装置，更具体地，涉及一种用于提高包括熔丝阵列并减小半导体器件面积的半导体器件的修复效率的技术。所述自修复装置包括：阵列断裂电熔丝（ARE）阵列单元，被配置为在多个熔丝组中存储故障地址; ARE控制单元，被配置为根据故障地址控制熔丝组的修复操作，比较故障地址并确定测试模式中的故障状态; 以及冗余单元，被配置为存储由所述ARE阵列单元施加的故障地址的熔丝数据，将输入地址与所述故障地址进行比较，以及控制行和列冗余操作。

73. 发明公开

KR1020140085222A 퓨즈 회로 및 리페어 퓨즈 회로 审中-实审
标题翻译：保险丝电路和维修保险丝电路
公开(公告)号：KR1020140085222A
公开(公告)日：2014-07-07
申请号：KR1020120155556
申请日：2012-12-27
申请人： 에스케이하이닉스 주식회사
发明人： 이동근
IPC分类号： G11C29/04
CPC分类号： G11C29/787 , G11C17/18 , G11C29/808
摘要： The present invention relates to a fuse circuit to store various data. Provided is a fuse circuit including a fuse array including a plurality of fuses, a plurality of fuse information latching parts to latch each of the cutting information of the fuses outputted from the fuse array, and a common operating part to perform the common operation of the fuse information latching parts.
摘要翻译：本发明涉及一种用于存储各种数据的熔丝电路。提供了一种熔丝电路，其包括具有多个保险丝的保险丝阵列，多个保险丝信息锁存部件，用于锁存从保险丝阵列输出的保险丝的每个切割信息;以及公共操作部件，用于执行保险丝信息锁定部件。

74. 发明授权

KR101387376B1 비휘발성 메모리 및 그의 기록 방법, 및 반도체 디바이스 有权
标题翻译：非易失性存储器及其写入方法以及半导体器件
公开(公告)号：KR101387376B1
公开(公告)日：2014-04-21
申请号：KR1020130112474
申请日：2013-09-23
申请人： 가부시키가이샤 한도오따이 에네루기 켄큐쇼
发明人： 카토,키요시
IPC分类号： G11C29/04 , G11C29/00 , G11C29/56 , H01L27/10
CPC分类号： H01L27/1266 , G11C7/24 , G11C8/08 , G11C17/14 , G11C17/165 , G11C17/18 , G11C29/787 , G11C29/816 , G11C29/848 , H01L27/1214
摘要： 1회 기록(write-once) 메모리는 각각의 메모리 셀에 오직 1회 기록이 가능하다; 따라서, 결함 비트는 기록의 실제 검사에 의해 검출될 수 없다. 따라서, 전술한 바와 같이, 용장 회로가 제공되고, 결함 비트가 출하 이전에 조정되는 조치가 취해질 수 없다; 따라서, 결함이 거의 없는 메모리를 제공하는 것이 어렵다. 본 발명의 목적은 결함 가능성이 상당히 감소된 1회 기록 메모리를 제공하는 것이다. 오직 1회 기록 가능한 비휘발성 메모리가 용장 메모리 셀, 어드레스를 상기 용장 메모리 셀에 할당하는 제 1 회로; 기록이 정상적으로 수행되었는지의 여부를 나타내는 결정 신호를 출력하는 제 2 회로, 및 상기 결정 신호가 입력되고, 상기 제 1 회로 및 상기 제 2 회로를 제어하는 제 3 회로를 포함한다.

75. 发明公开

KR1020140036879A 스페어 워드라인들의 다중 액티베이션 방지 방법 审中-实审
标题翻译：用于保护半导体存储器中备用字线的多个激活的方法
公开(公告)号：KR1020140036879A
公开(公告)日：2014-03-26
申请号：KR1020120103550
申请日：2012-09-18
申请人： 삼성전자주식회사
发明人： 오종민 , 이윤영 , 송호영 , 김치욱
IPC分类号： G11C29/00
CPC分类号： G11C29/838 , G11C29/787 , G11C2229/763
摘要： Disclosed is a method for preventing the multiple activation of spare word lines when a memory cell fail of a second order or more is generated in a volatile semiconductor memory like DRAM. The method includes the steps of: reprogramming a fail address when a defect is in the repaired spare word line; and programming an additional bit of the fail address which is previously programmed. Also, the method includes the steps of: disabling the fail sensing data with the information of the additional bit when two or more fail sensing data is received; and activating the spare word line which is instructed by the fail sensing data which does not include the information of the additional bit.
摘要翻译：本发明公开了一种在诸如DRAM的易失性半导体存储器中产生二次以上的存储单元故障时防止备用字线多次激活的方法。该方法包括以下步骤：当缺陷处于已修复的备用字线时重新编程故障地址; 并编程预先编程的故障地址的另外一位。此外，该方法包括以下步骤：当接收到两个或更多个故障感测数据时，使用附加位的信息禁用故障感测数据; 以及激活由不包括附加位的信息的故障检测数据指示的备用字线。

76. 发明公开

KR1020140012203A 비휘발성 메모리 및 그의 기록 방법, 및 반도체 디바이스 无效
标题翻译：非易失性存储器及其写入方法及半导体器件
公开(公告)号：KR1020140012203A
公开(公告)日：2014-01-29
申请号：KR1020140002435
申请日：2014-01-08
申请人： 가부시키가이샤 한도오따이 에네루기 켄큐쇼
发明人： 카토,키요시
IPC分类号： G11C17/18 , H01L29/786
CPC分类号： H01L27/1266 , G11C7/24 , G11C8/08 , G11C17/14 , G11C17/165 , G11C17/18 , G11C29/787 , G11C29/816 , G11C29/848 , H01L27/1214
摘要： A write-once memory can be written only once to each memory cell; therefore, a defective bit cannot be detected by an actual inspection of writing. Accordingly, as described above, the measures, in which a redundant circuit is provided and the defective bit is modified before shipping, cannot be taken; thus, it is difficult to provide a memory with few defects. The purpose of the present invention is to provide a write-once memory where the probability of a defect is reduced considerably. A nonvolatile memory that can be written only once includes a redundant memory cell, a first circuit which allocates an address to the redundant memory cell, a second circuit which outputs a determination signal indicative of whether writing is performed normally, and a third circuit to which the determination signal is inputted and which controls the first circuit and the second circuit. [Reference numerals] (AA) Determination signal
摘要翻译：一次写入存储器只能写入每个存储单元一次; 因此，实际的写入检查不能检测到有缺陷的位。因此，如上所述，不能采取在运输之前提供冗余电路和有缺陷的位被修改的措施; 因此难以提供缺少缺陷的记忆体。本发明的目的是提供一种写入一次的存储器，其中缺陷的概率显着降低。只能写入一次的非易失性存储器包括冗余存储单元，向冗余存储单元分配地址的第一电路，输出指示正常执行写入的确定信号的第二电路，以及第三电路，确定信号被输入并且控制第一电路和第二电路。（标号）（AA）确定信号

77. 发明公开

KR1020140003100A ＥＣＣ 회로를 포함하는 반도체 장치 审中-实审
标题翻译：具有ECC电路的半导体器件
公开(公告)号：KR1020140003100A
公开(公告)日：2014-01-09
申请号：KR1020120070724
申请日：2012-06-29
申请人： 에스케이하이닉스 주식회사
发明人： 양형균 , 이형동 , 권용기 , 문영석
IPC分类号： G11C29/42
CPC分类号： G11C29/42 , G11C29/4401 , G11C29/787 , G11C2029/0409 , G11C2029/0411
摘要： Disclosed is a semiconductor device including an ECC circuit, capable of improving error correction performance. The semiconductor device according to one embodiment of the present invention includes a memory area which includes a plurality of banks and a redundancy area at each bank and an ECC area which corrects the defect of the memory area by detecting an error address in the memory area and replacing the error address with a redundancy line in the redundancy area using information about the corresponding address. [Reference numerals] (10) Bank; (210) Error check block; (220) Self repair tissue block; (230) Fuse block
摘要翻译：公开了一种能够提高纠错性能的包括ECC电路的半导体器件。根据本发明的一个实施例的半导体器件包括：存储区，其包括多个存储区和每个存储体处的冗余区;以及ECC区，其通过检测存储区中的错误地址来校正存储区的缺陷;以及使用关于相应地址的信息，用冗余区域中的冗余线替换错误地址。（附图标记）（10）银行; （210）错误检查块; （220）自修复组织块; （230）保险丝座

78. 发明公开

KR1020130135658A 패키징 후에 발생되는 불량 셀을 구제하는 메모리 장치 无效
标题翻译：包装后能够修复失败的细胞的记忆装置
公开(公告)号：KR1020130135658A
公开(公告)日：2013-12-11
申请号：KR1020120059427
申请日：2012-06-01
申请人： 삼성전자주식회사
发明人： 김철 , 신상호 , 김중식
IPC分类号： G11C29/00
CPC分类号： G11C29/04 , G11C29/4401 , G11C29/783 , G11C29/785 , G11C29/787 , G11C2029/4402
摘要： The present invention discloses a device for rescuing a defective cell generated after packaging. The memory device includes a memory cell array for a plurality of memory cells, a repair circuit part including a first storage part storing a defective cell address in the memory cell array, and a fuse circuit part including a second storage part programmed according to information about the defective cell stored in the first storage part. The first storage part is composed of volatile memory elements and the second storage part is composed of non-volatile memory elements.
摘要翻译：本发明公开了一种用于拯救包装后产生的有缺陷的电池的装置。所述存储装置包括用于多个存储单元的存储单元阵列，修复电路部分，包括存储单元阵列中存储有缺陷单元地址的第一存储单元和熔丝电路部分，所述熔丝电路部分包括根据关于存储在第一存储部分中的有缺陷的单元。第一存储部分由易失性存储元件组成，第二存储部分由非易失性存储元件组成。

79. 发明公开

KR1020130059200A 퓨즈회로를 포함하는 반도체 집적회로 및 퓨즈회로의 구동방법 无效
标题翻译：具有保险丝电路的半导体集成电路和保险丝电路的驱动方法
公开(公告)号：KR1020130059200A
公开(公告)日：2013-06-05
申请号：KR1020110125391
申请日：2011-11-28
申请人： 에스케이하이닉스 주식회사
发明人： 정영한 , 이종성 , 김정선
IPC分类号： G11C29/04 , G11C5/14 , G11C7/10
CPC分类号： G11C29/787 , G11C17/18 , G11C29/808 , G11C2229/766
摘要： PURPOSE: A semiconductor integrated circuit including a fuse circuit and a driving method of the fuse circuit are provided to improve reliability by preventing the electrical and chemical migration of metal ions having a fuse. CONSTITUTION: A first driving unit(610) pulls down a first node in an initialization section in response to a fuse sensing signal. A second driving unit(620) pulls up a second node in an initial first section of a fuse sensing section in response to the fuse sensing signal. A delay fuse sensing signal generating unit(650) generates a delay fuse sensing signal which delays an activation edge of the fuse sensing signal to an initial second section of the fuse sensing section. A third driving unit(640) drives the second node with a voltage level lower than the pull-up level of the second driving unit. [Reference numerals] (610) First driving unit; (620) Second driving unit; (630) Sensing unit; (640) Third driving unit; (650) Delay fuse sensing signal generating unit
摘要翻译：目的：提供一种包括熔丝电路和熔丝电路的驱动方法的半导体集成电路，以通过防止具有保险丝的金属离子的电化学迁移来提高可靠性。构成：响应于熔丝感测信号，第一驱动单元（610）拉下初始化部分中的第一节点。第二驱动单元（620）响应于熔丝感测信号在熔丝感测部分的初始第一部分中拉起第二节点。延迟熔丝检测信号生成单元（650）产生延迟熔丝检测信号，该信号将熔丝感测信号的激活边沿延迟到熔丝检测部分的初始第二部分。第三驱动单元（640）以比第二驱动单元的上拉电平低的电压电平驱动第二节点。（附图标记）（610）第一驱动单元; （620）第二驱动单元; （630）感应单元; （640）第三驱动单元; （650）延时保险丝检测信号发生单元

80. 发明公开

KR1020130012738A 반도체 메모리 장치의 퓨즈 회로 无效
标题翻译：半导体存储器的保险丝电路
公开(公告)号：KR1020130012738A
公开(公告)日：2013-02-05
申请号：KR1020110074078
申请日：2011-07-26
申请人： 에스케이하이닉스 주식회사
发明人： 차진엽
IPC分类号： G11C29/04
CPC分类号： G11C29/787 , G11C17/18 , G11C29/808 , G11C2229/763
摘要： PURPOSE: A fuse circuit of a semiconductor memory device is provided to reduce current consumption for cutting a fuse by preventing a fuse power applying signal from being inputted to the fuse circuit. CONSTITUTION: A fuse selecting unit(100) generates a fuse power applying signal by receiving a fuse address signal and a test mode signal. A fuse power applying unit(200) receives the fuse power applying signal, applies power to a fuse, and generates a power applying completion signal. A latch unit(300) receives the power applying completion signal and blocks the fuse power applying signal to the fuse power applying unit. [Reference numerals] (100) Fuse selecting unit; (200) Fuse power applying unit; (300) Latch unit
摘要翻译：目的：提供一种半导体存储器件的保险丝电路，以通过防止熔丝功率施加信号被输入到熔丝电路来减少切断熔丝的电流消耗。构成：熔丝选择单元（100）通过接收熔丝地址信号和测试模式信号来产生熔丝功率施加信号。保险丝功率施加单元（200）接收熔丝加电信号，向熔丝施加电力，并产生功率施加完成信号。锁存单元（300）接收功率施加完成信号，并将保险丝功率施加信号阻挡到保险丝功率施加单元。（附图标记）（100）保险丝选择单元; （200）保险丝加电单元; （300）锁存单元

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