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61. 发明公开

KR1020140139926A 프로그램 로드 시 전력소모를 줄이기 위한 칼럼 디코더를 포함하는 메모리 有权
标题翻译：具有省电列解码器的存储器用于程序负载操作
公开(公告)号：KR1020140139926A
公开(公告)日：2014-12-08
申请号：KR1020130060646
申请日：2013-05-28
申请人： 중소기업은행
发明人： 김용수
IPC分类号： G11C16/08 , G11C16/10 , G11C16/06
CPC分类号： G11C16/08 , G11C16/0483 , G11C16/10 , G11C2216/14
摘要： 본 발명은 메모리에서 프로그램 데이터 쓰기 드라이버의 구동 방법에 관한 것으로, 프로그램 로드 및 데이터 입력 명령에 맞추어 쓰기 드라이버를 구동하여 저전력 소모가 가능한 메모리를 구현할 수 있다.
摘要翻译：本发明涉及存储器中的程序数据写入驱动器的驱动方法。本发明实现了在加载程序之后能够实现低功耗并且根据数据输入命令操作写入驱动器的存储器。本发明具有一种列解码器结构，用于在将程序加载到存储器中时能够稳定地降低功耗并写入数据。

62. 发明公开

KR1020140026758A 비휘발성 메모리 장치 및 이를 포함하는 비휘발성 메모리 시스템 无效
标题翻译：非易失性存储器件和非易失性存储器系统，包括它们
公开(公告)号：KR1020140026758A
公开(公告)日：2014-03-06
申请号：KR1020120092290
申请日：2012-08-23
申请人： 에스케이하이닉스 주식회사
发明人： 엄기표 , 김상식
IPC分类号： G11C16/14 , G11C16/30 , G11C16/12 , G11C16/08
CPC分类号： G11C16/26 , G11C16/0483 , G11C16/08 , G11C16/105 , G11C16/30 , G11C2216/14
摘要： The present invention relates to a nonvolatile memory device capable of performing an erasing operation in page units and a nonvolatile memory system containing the same. The present invention provides the nonvolatile memory device which comprises: a cell array containing a plurality of pages; a select unit for selecting any one page among the plurality of pages according to a page selecting address; an operation control unit which reads data of a set number of pages adjacent to the page selected by the select unit according to a page erasing command and outputs as a back-up data, erases the data of the selected page, and re-programs update data and the back-up data to the selected page and the set number of pages adjacent to the selected page; and a data storage unit for storing the back-up data. [Reference numerals] (122) Page selection circuit; (124) Block selection circuit; (126 ) Block voltage selection circuit 1; (126 ) Block voltage selection circuit 2; (126 ) Block voltage selection circuit 3; (142) Bias voltage supply unit; (144 ) Page buffer 1; (144 ) Page buffer 2; (144 ) Page buffer M; (160) Data storage unit
摘要翻译：本发明涉及一种能够以页面单位执行擦除操作的非易失性存储器件和包含该擦除操作的非易失性存储器系统。本发明提供一种非易失性存储装置，包括：包含多页的单元阵列; 选择单元，用于根据页选择地址选择所述多页中的任何一页; 操作控制单元，根据页擦除命令读取与选择单元选择的页面相邻的设定页数的数据，并作为备份数据输出，擦除所选页的数据，并重新编程更新数据和备份数据到所选择的页面和与所选页面相邻的设定页数; 以及用于存储备份数据的数据存储单元。（122）页选择电路; （124）块选择电路; （126 <1>）块电压选择电路1; （126 <2>）块电压选择电路2; （126 ）页面缓冲区1; （144 <2>）页面缓冲区2; （144 ）页缓冲器M; （160）数据存储单元

63. 发明公开

KR1020130119201A 래치 회로 및 비휘발성 메모리 장치 审中-实审
标题翻译：锁存电路和非易失性存储器件
公开(公告)号：KR1020130119201A
公开(公告)日：2013-10-31
申请号：KR1020120042173
申请日：2012-04-23
申请人： 에스케이하이닉스 주식회사
发明人： 최성대
IPC分类号： G11C7/10 , G11C5/14
CPC分类号： G11C7/10 , G11C16/30 , G11C16/32 , G11C2216/14 , H03K3/012 , H03K3/356
摘要： PURPOSE: A latch circuit and a nonvolatile memory device are provided to prevent a power drop by initializing multiple latches with a minimum current in a minimum initializing time. CONSTITUTION: A latch (100_1) is operated by a power which is supplied to a pull-up power supply end and a pull-down power supply end. A delay unit (300) generates a delayed initialization signal by delaying the initialization signal. A power supply unit (200) supplies a same power to the pull-up power supply end and the pull-down power supply end in response to the initialization signal. An initialization unit (400) initializes the latch to a first level in response to the delayed initialization signal. [Reference numerals] (300) Delay unit
摘要翻译：目的：提供锁存电路和非易失性存储器件，以在最小初始化时间内以最小电流初始化多个锁存器来防止掉电。构成：锁存器（100_1）由提供给上拉电源端和下拉电源端的电源操作。延迟单元（300）通过延迟初始化信号来产生延迟的初始化信号。电源单元（200）响应于初始化信号向上拉电源端和下拉电源端提供相同的电力。初始化单元（400）响应于延迟的初始化信号将锁存器初始化为第一电平。（附图标记）（300）延迟单元

64. 发明公开

KR1020130088358A 불휘발성 메모리 장치 및 그것의 읽기 방법 审中-实审
标题翻译：非易失性存储器件及其读取方法
公开(公告)号：KR1020130088358A
公开(公告)日：2013-08-08
申请号：KR1020120009552
申请日：2012-01-31
申请人： 삼성전자주식회사
发明人： 심재성 , 이봉용
IPC分类号： G11C16/26 , G11C16/24 , G11C16/30
CPC分类号： G11C16/26 , G11C7/04 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/06 , G11C2216/14 , G11C16/24 , G11C16/30
摘要： PURPOSE: A non-volatile memory device and a reading method thereof are provided to compensate for the reduction of channel current corresponding to a change in temperature by increasing a development time as the temperature decreases. CONSTITUTION: A memory cell is connected to a bit line and a word line. A page buffer (131) senses data stored in the memory cell by being electrically connected to the bit line. A control logic (150) controls the page buffer to vary a development time of the bit line or a sensing node connected to the bit line according to the current temperature in a reading operation.
摘要翻译：目的：提供一种非易失性存储器件及其读取方法，以通过随着温度降低而增加显影时间来补偿对应于温度变化的通道电流的减小。构成：存储单元连接到位线和字线。页面缓冲器（131）通过电连接到位线来感测存储在存储单元中的数据。控制逻辑（150）控制页面缓冲器以根据读取操作中的当前温度来改变位线或连接到位线的感测节点的显影时间。

65. 发明公开

KR1020130043534A 플래시 메모리 장치 및 플래시 메모리 장치의 프로그램 방법 无效
标题翻译：闪存存储器装置和编程闪速存储器件的方法
公开(公告)号：KR1020130043534A
公开(公告)日：2013-04-30
申请号：KR1020110107750
申请日：2011-10-20
申请人： 삼성전자주식회사
发明人： 김승범 , 정재용 , 박기태
IPC分类号： G11C16/10 , G11C16/06
CPC分类号： G11C16/10 , G06F12/0246 , G11C2216/14
摘要： PURPOSE: A flash memory device and a method for programming the same are provided to increase an operation speed by reducing programming time. CONSTITUTION: Randomized data is inputted by using a seed for a target block. A buffer block(110) is programmed. A page buffer(130) reads the buffer block. The page buffer programs a target block(120) without outputting data from the read buffer block.
摘要翻译：目的：提供闪存设备及其编程方法，以通过减少编程时间来提高操作速度。构成：通过使用目标块的种子输入随机数据。缓冲块（110）被编程。页面缓冲器（130）读取缓冲器块。页缓冲器对目标块（120）进行编程，而不从读缓冲块输出数据。

66. 发明公开

KR1020130038527A 불휘발성 메모리 장치 및 이의 동작 방법 无效
标题翻译：非易失性存储器件及其操作方法
公开(公告)号：KR1020130038527A
公开(公告)日：2013-04-18
申请号：KR1020110102932
申请日：2011-10-10
申请人： 에스케이하이닉스 주식회사
发明人： 조명 , 박성제 , 이정환 , 김지환 , 하범석
IPC分类号： G11C29/42 , G11C16/34 , G11C16/06
CPC分类号： G11C7/1048 , G11C7/10 , G11C16/3459 , G11C2216/14
摘要： PURPOSE: A nonvolatile memory device and an operating method thereof are provided to check a pass or a fail at a column address unit processed by an error correcting code circuit by selectively checking the pass or the fail of only the page buffers with the same upper bits. CONSTITUTION: A page buffer unit(150) includes a plurality of page buffers connected to bit lines of a memory cell block. A pass and fail checking circuit(170) checks a pass or a fail by comparing a current amount changed according to verification data stored in the plurality of page buffers with a reference current amount corresponding to an error correctable bit number. A masking circuit(160) blocks pass and fail check operations by connecting a ground power source to sensing nodes of the remaining page buffers except the page buffers corresponding to a column address with the same data of an upper specific bit as the data of the upper specific bit of an inputted column address. [Reference numerals] (110) Memory block; (120) Control circuit; (130) Voltage generating circuit; (140) Low decoder; (160) Masking circuit; (170) Pass and fail checking circuit;
摘要翻译：目的：提供一种非易失性存储器件及其操作方法，通过选择性地检查具有相同高位的页缓冲器的通过或失败来检查由纠错码电路处理的列地址单元的通过或失败。构成：页缓冲器单元（150）包括连接到存储器单元块的位线的多个页缓冲器。通过和失败检查电路（170）通过将根据存储在多个页缓冲器中的验证数据而改变的当前量与对应于错误可校正位数的参考电流量比较来检查通过或失败。屏蔽电路（160）通过将接地电源连接到除了对应于具有与上位数据的数据相同的高位特定位的列地址的页缓冲器之外的剩余页缓冲器的感测节点来阻止通过和失败检查操作输入列地址的特定位。（附图标记）（110）存储块; （120）控制电路; （130）电压发生电路; （140）低解码器; （160）屏蔽电路; （170）通过和故障检查电路;

67. 发明公开

KR1020130028928A 비휘발성 메모리 직렬 코어 구조 有权
标题翻译：非易失性存储器串行核心架构
公开(公告)号：KR1020130028928A
公开(公告)日：2013-03-20
申请号：KR1020127028929
申请日：2007-11-26
申请人： 컨버전트 인텔렉츄얼 프로퍼티 매니지먼트 인코포레이티드
发明人： 김,진기
IPC分类号： G11C16/02 , G11C16/24 , G11C16/08
CPC分类号： G06F3/061 , G06F3/0629 , G06F3/0659 , G06F3/0679 , G11C5/025 , G11C7/1006 , G11C7/1033 , G11C7/1039 , G11C7/1042 , G11C7/1048 , G11C7/1051 , G11C7/1072 , G11C7/12 , G11C16/04 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/24 , G11C16/26 , G11C16/32 , G11C2207/107 , G11C2216/14 , G11C2216/20 , G11C2216/30
摘要： 직렬 비트스트림으로 적어도 하나의 메모리 뱅크로부터 데이터를 수신하고, 데이터를 제공하기 위해 직렬 데이터 인터페이스와 직렬 데이터 경로 코어를 갖는 메모리 시스템이 제공된다. 메모리 뱅크는 2개의 하프로 분할되고, 각 하프는 상부 및 하부 섹터로 분할된다. 각 섹터는 집적된 셀프 칼럼 디코딩 회로를 갖는 공유된 2차원 페이지 버퍼에 병렬로 데이터를 공급한다. 메모리 뱅크내의 직렬-병렬 데이터 컨버터는 하프로부터의 병렬 데이터를 직렬 데이터 경로 코어에 결합한다. 집적된 셀프 칼럼 디코딩 회로를 갖는 공유된 2차원 페이지 버퍼는 각 뱅크에 대한 회로 및 칩영역 오버헤드를 최소화하고, 직렬 데이터 경로 코어는 광 데이터 버스를 라우팅하기 위해 일반적으로 사용되는 칩 영역을 감소시킨다. 그러므로, 동일한 밀도를 갖는 단일 메모리 뱅크 시스템과 비교할 때 현저한 대응하는 칩 영역 증가없이 다중 메모리 뱅크 시스템이 구현된다.

68. 发明公开

KR1020120108882A 증폭 회로, 그것을 갖는 출력 회로, 비휘발성 메모리 장치, 메모리 시스템, 및 메모리 카드, 그리고 그것의 데이터 출력 방법 有权
标题翻译：感应放大电路，输出电路，非易失性存储器件，存储器系统及具有该存储器系统的存储卡及其数据输出方法
公开(公告)号：KR1020120108882A
公开(公告)日：2012-10-05
申请号：KR1020110042986
申请日：2011-05-06
申请人： 삼성전자주식회사
发明人： 이태성 , 임재우
IPC分类号： G11C16/26 , G11C16/06
CPC分类号： G11C16/26 , G11C7/18 , G11C16/08 , G11C2216/14
摘要： PURPOSE: An amplification circuit, an output circuit including the same, a nonvolatile memory device, a memory system, a memory card, and a data outputting method thereof are provided to output data at a high speed by using a differential sensing method. CONSTITUTION: A memory cell array(110) includes a plurality of memory blocks. Page buffer latches latch data read from memory cells. Sub data lines receive voltages corresponding to latched data in response to latch addresses. A data line(DL) connects the sub data lines in a sensing operation. A current path is formed in a reference data line(DLref) in the sensing operation. A sensing amplification circuit(140) differentially senses the data line and the reference data line in the sensing operation and outputs data corresponding to a sensing result.
摘要翻译：目的：提供一种放大电路，包括该放大电路的输出电路，非易失存储器件，存储器系统，存储卡及其数据输出方法，以通过使用微分检测方法高速输出数据。构成：存储单元阵列（110）包括多个存储块。页缓冲器锁存从存储单元读取的数据。子数据线响应于锁存地址接收对应于锁存数据的电压。数据线（DL）在感测操作中连接子数据线。在感测操作中，在参考数据线（DLref）中形成电流路径。感测放大电路（140）在感测操作中差分地感测数据线和参考数据线，并且输出与感测结果对应的数据。

69. 发明公开

KR1020120069533A 불휘발성 반도체 기억 장치 无效
标题翻译：非易失性半导体存储器件
公开(公告)号：KR1020120069533A
公开(公告)日：2012-06-28
申请号：KR1020110094706
申请日：2011-09-20
申请人： 삼성전자주식회사
发明人： 카와무라,쇼이치 , 미야모토,토모히사
IPC分类号： G11C16/34 , G11C16/06
CPC分类号： G11C16/3413 , G11C16/0483 , G11C16/08 , G11C16/3463 , G11C2216/14
摘要： PURPOSE: A nonvolatile semiconductor memory device is provided to improve the reliability of the nonvolatile semiconductor memory device by erasing an over program memory cell with a bit unit. CONSTITUTION: A plurality of bit lines and a plurality of word lines intersect in a memory cell array(11) and a nonvolatile memory cell is arranged in an intersection. A page buffer(13) includes a latch which stores data read from a memory cell or data to be written in the memory cell. A control circuit(20) performs an over program verification operation in a plurality of page buffers by referring to the data stored in the latch.
摘要翻译：目的：提供一种非易失性半导体存储器件，通过用位单元擦除程序存储单元来提高非易失性半导体存储器件的可靠性。构成：在存储单元阵列（11）和非易失性存储单元中相交的多个位线和多个字线布置在交叉点中。页面缓冲器（13）包括存储从存储器单元读取的数据或要写入存储单元的数据的锁存器。控制电路（20）通过参照存储在锁存器中的数据在多个页缓冲器中执行过程编码验证操作。

70. 发明公开

KR1020120068071A 패스/페일 체크 회로 无效
标题翻译：通过/失败检查电路
公开(公告)号：KR1020120068071A
公开(公告)日：2012-06-27
申请号：KR1020100104674
申请日：2010-10-26
申请人： 에스케이하이닉스 주식회사
发明人： 민민
IPC分类号： G11C16/34 , G11C16/06
CPC分类号： G11C16/3459 , G11C16/10 , G11C2216/14
摘要： PURPOSE: A pass/fail check circuit is provided to reduce an area thereof by using a sensing node without an additional capacitor. CONSTITUTION: A first capacitor unit(310) includes a plurality of first capacitors which is activated or inactivated in response to a plurality of verification completion data. The first capacitor unit has capacitance determined by activated capacitors among the plurality of the first capacitors. A second capacitor unit(320) has preset capacitance. A pass/fail signal generating unit(330) generates a pass/fail signal by comparing the capacitance of the first capacitor unit with the capacitance of the second capacitor unit.
摘要翻译：目的：提供通过/失败检查电路，通过使用没有附加电容器的感测节点来减小其面积。构成：第一电容器单元（310）包括响应于多个验证完成数据被激活或失活的多个第一电容器。第一电容器单元具有由多个第一电容器中的激活的电容器确定的电容。第二电容器单元（320）具有预设的电容。通过/失败信号生成单元（330）通过将第一电容器单元的电容与第二电容器单元的电容进行比较来产生通过/失败信号。

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