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31. 发明公开

KR1020090032884A 반도체 소자의 제조 방법 无效
标题翻译：制造半导体器件的方法
公开(公告)号：KR1020090032884A
公开(公告)日：2009-04-01
申请号：KR1020070098461
申请日：2007-09-28
申请人： 에스케이하이닉스 주식회사
发明人： 성현석
IPC分类号： H01L27/108
CPC分类号： H01L28/91 , H01L21/32135 , H01L27/10855
摘要： A manufacturing method of a semiconductor device is provided to prevent the fail of the storage electrode by progressing the etch back process for the separation of the conductive layer for the storage electrode with two steps. An etch stopping layer(320) and a sacrificial dielectric film are formed on a semiconductor substrate(300) including a storage node contact(310). The mask pattern defining the store electrode territory is formed on the top of the sacrificial dielectric film. The storage node contact is exposed by etching the sacrificial dielectric film and the etch stopping layer. A conductive layer(350) for the storage electrode and a barrier metal layer of the constant thickness are formed on the whole surface. The conductive layer for the storage electrode is separated by removing the conductive layer for the storage electrode of the upper part of the sacrifice insulating layer pattern. The pattern residue formed on the top of the conductive layer for the storage electrode is removed using the etching process. The cylindrical storage node is formed by removing the sacrifice insulating layer pattern. A dielectric film(360) is formed on the whole surface including the storage electrode. A plate electrode(370) is formed on the top of the dielectric film.
摘要翻译：提供半导体器件的制造方法，以通过进行用于分离用于存储电极的导电层的回蚀工艺两步来防止存储电极的故障。在包括存储节点接触件（310）的半导体衬底（300）上形成蚀刻停止层（320）和牺牲绝缘膜。限定存储电极区域的掩模图案形成在牺牲电介质膜的顶部。通过蚀刻牺牲绝缘膜和蚀刻停止层来暴露存储节点接触。在整个表面上形成用于存储电极的导电层（350）和恒定厚度的阻挡金属层。通过去除牺牲绝缘层图案的上部的存储电极的导电层来分离用于存储电极的导电层。使用蚀刻工艺除去形成在用于存储电极的导电层的顶部上的图案残留物。通过去除牺牲绝缘层图案形成圆柱形存储节点。在包括存储电极的整个表面上形成电介质膜（360）。在电介质膜的顶部形成有平板电极（370）。

32. 发明公开

KR1020090004056A 반도체 소자의 제조방법 无效
标题翻译：制造半导体器件的方法
公开(公告)号：KR1020090004056A
公开(公告)日：2009-01-12
申请号：KR1020070067946
申请日：2007-07-06
申请人： 에스케이하이닉스 주식회사
发明人： 박상준
IPC分类号： H01L21/28
CPC分类号： H01L21/76877 , H01L21/3212 , H01L21/32135
摘要： The method of manufacturing the semiconductor device is provided to prevent the short of the top conductive layer and contact plug by burying the contact hole with the second conductive film. The interlayer insulating film(32) having the contact hole(33) exposing the constant area of the substrate(30) is formed on the substrate. The bottom of the contact hole is buried with the first conductive film(34). The contact hole is completely buried with the second conductive film(35). The polishing is performed in order to remove the second conductive film of the upper part of interlayer insulating film and then the contact plug(36) is formed. The first conductive film is formed with the polysilicon layer. The second conductive film is formed with the tungsten film.
摘要翻译：提供制造半导体器件的方法，以通过将接触孔埋入第二导电膜来防止顶部导电层和接触插塞的短路。在衬底上形成具有暴露衬底（30）的恒定区域的接触孔（33）的层间绝缘膜（32）。接触孔的底部被第一导电膜（34）掩埋。接触孔与第二导电膜（35）完全掩埋。进行研磨以去除层间绝缘膜的上部的第二导电膜，然后形成接触插塞（36）。第一导电膜由多晶硅层形成。第二导电膜由钨膜形成。

33. 发明公开

KR1020090003730A 반도체 소자의 금속배선 형성 방법 无效
标题翻译：形成半导体器件金属线的方法
公开(公告)号：KR1020090003730A
公开(公告)日：2009-01-12
申请号：KR1020070066641
申请日：2007-07-03
申请人： 에스케이하이닉스 주식회사
发明人： 김세진 , 유미현
IPC分类号： H01L21/28
CPC分类号： H01L21/76877 , H01L21/32135
摘要： The method of forming the metal wiring in the semiconductor device is provided to increase the contact resistance and process margin by adding the O2 buffer gas by using the mixed gas of Ar and SF6 as the etching gas. The interlayer insulating film in which the metal wiring contact hole is equipped in the semiconductor substrate upper is formed. The tungsten layer burying the metal wiring contact hole on the semiconductor substrate is formed. The metal wiring contact plug is formed by etching the tungsten layer using the etching gas adding the O2 gas in the mixed gas of Ar and SF6. The metal wiring connected with the metal wiring contact plug is formed. The mixed ratio of Ar and SF6 is 18~20:1. The mixed ratio of the O2 gas to SF6 is 8~10:1. The rate of the bias voltage and the RF source voltage in the etching process is maintained by 12~13:1.
摘要翻译：提供了在半导体器件中形成金属布线的方法，通过使用Ar和SF6的混合气体作为蚀刻气体，通过添加O 2缓冲气体来提高接触电阻和加工余量。形成在半导体衬底上配置有金属配线接触孔的层间绝缘膜。形成在半导体衬底上埋设金属布线接触孔的钨层。通过在Ar和SF6的混合气体中添加O 2气体的蚀刻气体来蚀刻钨层，形成金属配线接触插塞。形成与金属布线接触插塞连接的金属布线。 Ar和SF6的混合比为18〜20：1。 O2气体与SF6的混合比例为8〜10：1。蚀刻工艺中的偏置电压和RF源电压的比率保持在12〜13：1。

34. 发明公开

KR1020080088720A 반도체 메모리 소자의 배선 제조방법 无效
标题翻译：制造半导体存储器件互连线的方法
公开(公告)号：KR1020080088720A
公开(公告)日：2008-10-06
申请号：KR1020070031316
申请日：2007-03-30
申请人： 삼성전자주식회사
发明人： 김영주 , 김동우
IPC分类号： H01L21/28 , H01L21/3205
CPC分类号： H01L21/32135 , H01L21/31116 , H01L21/31144 , H01L21/32139 , H01L21/76834 , H01L21/76841
摘要： A method for fabricating an interconnection of a semiconductor memory device is provided to minimize generation of particles by performing an in-situ process by one step while using one kind of etchant. A stacked material layer is formed on a semiconductor substrate(100), composed of a plurality of insulation layers and a conductive layer. By using etchant having low etch selectivity with respect to the insulation layer and the conductive layer, the stacked material layer is anisotropically etched by one etch process. A barrier metal layer, an aluminum layer, a capping layer and a hard mask layer are sequentially deposited in the stacked material layer.
摘要翻译：提供一种用于制造半导体存储器件的互连的方法，以通过在使用一种蚀刻剂的同时进行一步的原位处理来最小化颗粒的产生。层叠材料层形成在由多个绝缘层和导电层构成的半导体基板（100）上。通过使用相对于绝缘层和导电层具有低蚀刻选择性的蚀刻剂，通过一个蚀刻工艺对堆叠的材料层进行各向异性蚀刻。阻挡金属层，铝层，覆盖层和硬掩模层依次沉积在堆叠的材料层中。

35. 发明公开

KR1020080061154A 반도체 소자의 캐패시터 형성방법 无效
标题翻译：形成半导体器件电容器的方法
公开(公告)号：KR1020080061154A
公开(公告)日：2008-07-02
申请号：KR1020060136141
申请日：2006-12-28
申请人： 에스케이하이닉스 주식회사
发明人： 양철훈
IPC分类号： H01L27/108
CPC分类号： H01L28/92 , H01L21/31116 , H01L21/32135 , H01L28/40
摘要： A method for forming a capacitor of a semiconductor device is provided to increase the effective area of a capacitor by respectively performing a deposition process and an over etch process after a first conductive layer, a dielectric layer and a second conductive layer are deposited. A first conductive layer(102) is formed on a semiconductor substrate(100) and is selectively etched to form a lower electrode layer whose upper part is round. After a dielectric material is deposited on the lower electrode layer, the dielectric material is etched to form a dielectric layer(105) whose upper part is round. A second conductive layer(107) is formed on the dielectric layer and is selectively etched to form an upper electrode layer whose upper part is round. The process for forming the lower electrode layer can include the following steps. A silicon oxide layer, the first conductive layer and an ARC(anti-reflective coating) are sequentially stacked on the semiconductor substrate. After a photoresist pattern is formed on the ARC, the ARC, the first conductive layer and the silicon oxide layer are sequentially etched by a selective etch process. An additional etch process is performed to remove the ARC while the upper part of the first conductive layer is rounded.
摘要翻译：提供一种用于形成半导体器件的电容器的方法，用于在沉积第一导电层，电介质层和第二导电层之后分别执行沉积工艺和过蚀刻工艺来增加电容器的有效面积。第一导电层（102）形成在半导体衬底（100）上，并被选择性地蚀刻以形成上部为圆形的下电极层。在电介质材料沉积在下电极层上之后，电介质材料被蚀刻以形成上部为圆形的电介质层（105）。第二导电层（107）形成在电介质层上，并被选择性地蚀刻以形成其上部是圆形的上电极层。形成下电极层的工艺可以包括以下步骤。氧化硅层，第一导电层和ARC（抗反射涂层）依次堆叠在半导体衬底上。在ARC上形成光致抗蚀剂图案之后，通过选择性蚀刻工艺依次蚀刻ARC，第一导电层和氧化硅层。执行额外的蚀刻工艺以去除ARC，同时第一导电层的上部被倒圆。

36. 发明公开

KR1020080060327A 반도체 소자의 플러그 제조 방법 无效
标题翻译：用于在半导体器件中制作插片的方法
公开(公告)号：KR1020080060327A
公开(公告)日：2008-07-02
申请号：KR1020060134277
申请日：2006-12-27
申请人： 에스케이하이닉스 주식회사
发明人： 김석기 , 최익수 , 김은미 , 김래현
IPC分类号： H01L21/28
CPC分类号： H01L21/76883 , H01L21/32135 , H01L21/7684 , H01L21/76897 , H01L27/10855 , H01L27/10888
摘要： A method for manufacturing a plug of a semiconductor device is provided to prevent defects of a self aligned process by removing a step caused by a seam through a double etch-back process. An interlayer dielectric(37) is formed on a substrate(31). A contact hole is formed by etching the interlayer dielectric. A plug conductive layer for filling up the contact hole is formed on the entire surface of the substrate. A step is removed by performing a first etch-back. A second etch-back is performed to the plug conductive layer. A plug which is buried into the contact hole is formed by flattening the plug conductive layer processed with the second etch-back.
摘要翻译：提供一种用于制造半导体器件的插头的方法，以通过通过双重回蚀处理去除由接缝引起的步骤来防止自对准工艺的缺陷。在基板（31）上形成层间电介质（37）。通过蚀刻层间电介质形成接触孔。用于填充接触孔的插塞导电层形成在基板的整个表面上。通过执行第一次回蚀来去除一个步骤。对插头导电层进行第二次回蚀。埋入接触孔中的插头通过使用第二次回蚀处理的插头导电层变平而形成。

37. 发明公开

KR1020080058314A 티타늄 나이트리드 제거 방법 无效
标题翻译：氮化钛去除方法
公开(公告)号：KR1020080058314A
公开(公告)日：2008-06-25
申请号：KR1020080053253
申请日：2008-06-05
申请人： 에어 프로덕츠 앤드 케미칼스, 인코오포레이티드
发明人： 우딩준 , 지빙 , 카르왁키유진조셉쥬니어.
IPC分类号： H01L21/3065
CPC分类号： C23G5/00 , C23C16/4405 , H01L21/32135 , H01L21/32136
摘要： A method for removing titanium nitride is provided to effectively remove titanium nitride from surfaces of processing chambers or components without damaging the surfaces thereof. A method for removing titanium nitride from a surface of a substrate includes: providing a process gas having at least one reactive material selected from the group consisting of NF3, NClF2, NCl2F, F2, ClF3, ClF, SF6, BrF3, and BF3; enriching the process gas with at least one reactive species of the at least one reactive material to form an enriched process gas, in which the enriching is performed at a first position; providing the substrate at a substrate temperature greater than 90 °C, in which the surface of the substrate is at least partially coated with the titanium nitride; and contacting the titanium nitride on the surface of the substrate with enriched process to volatilize and remove the titanium nitride from the surface of the substrate, in which the contact occurs at a second position different from the first position.
摘要翻译：提供一种用于去除氮化钛的方法以有效地从处理室或部件的表面去除氮化钛而不损害其表面。从衬底表面去除氮化钛的方法包括：提供具有选自由NF3，NClF2，NCl2F，F2，ClF3，ClF，SF6，BrF3和BF3组成的组中的至少一种反应性材料的工艺气体; 用所述至少一种反应性材料的至少一种反应性物质富集工艺气体以形成富集的工艺气体，其中在第一位置进行富集; 在大于90℃的衬底温度下提供衬底，其中衬底的表面至少部分地涂覆有氮化钛; 以及使所述基板的表面上的所述氮化钛与所述基板的表面挥发并除去所述氮化钛，所述氮化钛在与所述第一位置不同的第二位置处发生所述接触。

38. 发明公开

KR1020080051139A 펄스 에칭 냉각 有权
标题翻译：脉冲蚀刻冷却
公开(公告)号：KR1020080051139A
公开(公告)日：2008-06-10
申请号：KR1020087006919
申请日：2006-08-23
申请人： 잭틱스 인코포레이티드
发明人： 레보이츠,카일,에스. , 스프링거,데이비드,엘.
IPC分类号： H01L21/306 , H01L21/00
CPC分类号： H01L21/3065 , H01L21/32135 , H01L21/67109
摘要： In an apparatus and method of vapor etching, a sample (S) to be etched is located in a main chamber (107) from which the atmosphere inside is evacuated. Etching gas is input into the main chamber (107) for a first period of time. Thereafter, the etching gas is evacuated from the main chamber (107) and cooling/purging gas is input into the main chamber for a second interval of time. Thereafter, the cooling/purging gas is evacuated from the main chamber (107). Desirably, the steps of inputting the etching gas into the main chamber (107) for the first period of time, evacuating the etching gas from the main chamber, inputting the cooling/purging gas into the main chamber (107) for the second period of time, and evacuating the cooling/purging gas from the main chamber are repeated until samples have been etched to a desired extent.
摘要翻译：在蒸气蚀刻的装置和方法中，待蚀刻的样品（S）位于主室（107）中，从其中抽空空气。蚀刻气体在第一时间段内输入主室（107）。之后，从主室107排出蚀刻气体，第二时间将冷却/净化气体输入主室。之后，从主室（107）排出冷却/净化气体。期望的是，将蚀刻气体输入到主室（107）中一段时间的步骤，从主室排出蚀刻气体，将冷却/净化气体输入到主室（107）的第二时段重复时间，并从主室排出冷却/吹扫气体，直到样品已经被蚀刻到期望的程度。

39. 发明公开

KR1020080033105A 반도체장치의 제조 방법 및 에칭장치 有权
标题翻译：制造显示装置的方法和蚀刻装置
公开(公告)号：KR1020080033105A
公开(公告)日：2008-04-16
申请号：KR1020070102417
申请日：2007-10-11
申请人： 가부시키가이샤 한도오따이 에네루기 켄큐쇼
发明人： 타나카코이치로 , 모리수에마사푸미
IPC分类号： H01L21/306 , H01L21/3063
CPC分类号： G02F1/136227 , H01L21/31111 , H01L21/31116 , H01L21/32134 , H01L21/32135 , H01L21/6708 , H01L21/76802 , H01L21/76804 , H01L21/76816 , H01L21/76817 , H01L27/124 , H01L27/1248 , H01L29/66765 , Y02P80/30
摘要： A method for manufacturing a display device, and an etching apparatus are provided to simplify processes by forming a contact hole without forming a mask on an insulating layer, and to reduce costs by coating a photoresist instead of exposure and developing processes. A tube(503) is arranged to be in contact with an insulating layer(502) in an opening formation region, and a treatment agent(etching gas or etchant) is discharged to the insulating layer through the tube. With the discharged treatment agent(etching gas or etchant), the insulating layer is selectively removed to form an opening(505) in the insulating layer. Therefore, the insulating layer provided with the opening is formed over a first conductive layer(501), and the first conductive layer below the insulating layer is exposed at the bottom of the opening. A second conductive layer is formed in the opening to be in contact with an exposed part of the first conductive layer, so that the first conductive layer and the second conductive layer are electrically connected in the opening provided in the insulating layer.
摘要翻译：提供一种制造显示装置的方法和蚀刻装置，以通过在绝缘层上形成掩模而形成接触孔来简化工艺，并且通过涂覆光致抗蚀剂而不是曝光和显影工艺来降低成本。管（503）布置成与开口形成区域中的绝缘层（502）接触，并且处理剂（蚀刻气体或蚀刻剂）通过管被排出到绝缘层。利用排出的处理剂（蚀刻气体或蚀刻剂），绝缘层被选择性地去除以在绝缘层中形成开口（505）。因此，设置有开口的绝缘层形成在第一导电层（501）上，并且绝缘层下方的第一导电层在开口的底部露出。在开口中形成第二导电层以与第一导电层的暴露部分接触，使得第一导电层和第二导电层在设置在绝缘层中的开口中电连接。

40. 发明公开

KR1020080018414A 반도체 장치 제조 방법 失效
标题翻译：制造半导体器件的方法
公开(公告)号：KR1020080018414A
公开(公告)日：2008-02-28
申请号：KR1020060080481
申请日：2006-08-24
申请人： 동부일렉트로닉스 주식회사
发明人： 이완기
IPC分类号： H01L21/3205 , H01L21/28
CPC分类号： H01L21/76802 , H01L21/0273 , H01L21/32135 , H01L21/32139 , H01L21/76838
摘要： A method of fabricating a semiconductor device is provided to prevent formation of arcing defect on a substrate by suppressing arc discharge generated at a plasma etching process of forming a via hole. A first interlayer dielectric(10) is formed on a process substrate with a device, and then is patterned to form a contact hole. A metallic layer for plug is deposited to fill the contact hole. The substrate is subjected to an etch-back process to form a metal plug. A conductive layer is formed on the substrate with the tungsten plug, and then is patterned to form a wiring pattern. A second interlayer dielectric(140) is deposited and patterned to form a via hole(150). In the step of forming the wiring pattern, an edge of the substrate is exposed to a light.
摘要翻译：提供一种制造半导体器件的方法，以通过抑制在形成通孔的等离子体蚀刻工艺中产生的电弧放电来防止在基板上形成电弧缺陷。在具有器件的处理衬底上形成第一层间电介质（10），然后将其图案化以形成接触孔。沉积用于塞子的金属层以填充接触孔。对衬底进行回蚀处理以形成金属插塞。在具有钨塞的基板上形成导电层，然后将其图案化以形成布线图案。沉积第二层间电介质（140）并图案化以形成通孔（150）。在形成布线图案的步骤中，将基板的边缘曝光。

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