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1. 发明公开

KR1020110037242A 반도체 소자의 형성 방법 无效
标题翻译：形成半导体器件的方法
公开(公告)号：KR1020110037242A
公开(公告)日：2011-04-13
申请号：KR1020090094599
申请日：2009-10-06
申请人： 에스케이하이닉스 주식회사
发明人： 유미현 , 김재영
IPC分类号： H01L21/28
CPC分类号： H01L21/76802 , H01L21/0337 , H01L21/76816 , H01L21/76831
摘要： PURPOSE: A semiconductor device formation method is provided to improve the characteristic of the semiconductor device by fundamentally solving the problem that the bottom of the contact hole is not open. CONSTITUTION: A bottom metal layer(110) is formed on a semiconductor substrate. A sacrificial dielectric film(130) is formed on the upper part of the bottom metal layer. The first contact hole is formed on the sacrificial dielectric film. An insulation spacer(160) is formed on the sidewall of the first contact hole.
摘要翻译：目的：通过从根本上解决接触孔的底部不开放的问题，提供半导体器件形成方法来改善半导体器件的特性。构成：在半导体衬底上形成底部金属层（110）。牺牲绝缘膜（130）形成在底部金属层的上部。第一接触孔形成在牺牲绝缘膜上。绝缘垫片（160）形成在第一接触孔的侧壁上。

2. 发明公开

KR1020090025809A 반도체 소자의 형성 방법 无效
标题翻译：形成半导体器件的方法
公开(公告)号：KR1020090025809A
公开(公告)日：2009-03-11
申请号：KR1020070090931
申请日：2007-09-07
申请人： 에스케이하이닉스 주식회사
发明人： 김세진 , 유미현
IPC分类号： H01L21/28 , H01L21/027
CPC分类号： H01L21/28008 , H01L21/0273 , H01L21/0274 , H01L21/0337
摘要： A method for forming a semiconductor device is provided to improve etching selectivity by using the mixed gas of BCl3 and Cl2 with a ratio of 1 - 1.5 : 1. An interlayer insulating layer(120) including a metal wire contact plug(130) is formed on a semiconductor substrate(100). A metal layer(140) is formed on the interlayer insulating layer. A photosensitive pattern(160) is formed on the metal layer. When etching the metal layer using the photosensitive pattern as a mask, a metal wire is formed by using the mixed gas of BCl3 and Cl2 with a ratio of 1-1.5 : 1. The photosensitive pattern is removed.
摘要翻译：提供一种用于形成半导体器件的方法，通过使用比例为1-1.5:1的BCl3和Cl2的混合气体来提高蚀刻选择性。形成包括金属线接触插塞（130）的层间绝缘层（120）在半导体衬底（100）上。金属层（140）形成在层间绝缘层上。在金属层上形成感光图案（160）。当使用感光图案作为掩模蚀刻金属层时，通过使用比例为1-1.5:1的BCl3和Cl2的混合气体形成金属线。去除感光图案。

3. 发明授权

KR101204920B1 반도체 소자의 제조 방법 有权
标题翻译：制造半导体器件的方法
公开(公告)号：KR101204920B1
公开(公告)日：2012-11-26
申请号：KR1020060137002
申请日：2006-12-28
申请人： 에스케이하이닉스 주식회사
发明人： 유미현
IPC分类号： H01L21/28
摘要： 본 발명은 반도체 소자의 제조 방법에 관한 것으로, 비트라인 형성 공정 시 도전층 일부를 선택 식각하고, 하드마스크층 패턴 및 상기 선택 식각된 도전층 측벽에 제 1 스페이서를 형성하여 하부의 글루막 및 장벽 금속층 식각 시 비트라인 콘택홀의 손상을 방지하며, 비트라인 패턴 형성 후 상기 비트라인 패턴 측벽에 제 2 스페이서를 형성함으로써, 후속 공정으로 형성되는 저장전극 콘택홀의 면적을 증가시켜 소자의 특성을 향상시키는 기술을 개시한다.
摘要翻译：本发明中，位线形成工序当导电层，并选择一些蚀刻，硬掩模层图案和形成在所述下部胶水层上的第一间隔物和所述屏障以在半导体元件的制造方法中的选择蚀刻的导电层侧壁防止在所述孔位线接触损伤蚀刻金属层，以及通过提供在图案侧壁上的第二间隔件改善了位线的特性的技术之后形成位线图案，通过增加在随后的处理元件形成的存储电极接触孔的面积它公开了。

4. 发明公开

KR1020110012412A 반도체소자의 형성방법 无效
标题翻译：制造半导体器件的方法
公开(公告)号：KR1020110012412A
公开(公告)日：2011-02-09
申请号：KR1020090070127
申请日：2009-07-30
申请人： 에스케이하이닉스 주식회사
发明人： 김재영 , 유미현
IPC分类号： H01L21/28 , H01L21/3205
CPC分类号： H01L21/76819 , H01L21/31053 , H01L27/10888 , H01L27/10894
摘要： PURPOSE: A semiconductor device forming method is provided to prevent the phenomenon of resulting in the level difference on an interface portion between a cell area and a peripheral circuit area during forming process of a semiconductor device including a buried gate. CONSTITUTION: An element isolation film(42) defining an active area is formed on the top of a semiconductor substrate(40). A recess is formed by etching the semiconductor substrate and the element isolation film. A hard mask layer(46) filling the top of the recess is formed. An interlayer insulating film(48) is formed on the top of the whole surface.
摘要翻译：目的：提供半导体器件形成方法，以防止在包括掩埋栅极的半导体器件的形成过程期间在单元区域和外围电路区域之间的界面部分上产生电平差的现象。构成：在半导体衬底（40）的顶部上形成限定有源区的元件隔离膜（42）。通过蚀刻半导体衬底和元件隔离膜形成凹部。形成填充凹部顶部的硬掩模层（46）。在整个表面的顶部形成层间绝缘膜（48）。

5. 发明公开

KR1020100001127A 반도체 소자의 금속 배선 형성 방법 失效
标题翻译：形成半导体器件金属线的方法
公开(公告)号：KR1020100001127A
公开(公告)日：2010-01-06
申请号：KR1020080060926
申请日：2008-06-26
申请人： 에스케이하이닉스 주식회사
发明人： 유미현 , 김세진
IPC分类号： H01L21/308
CPC分类号： H01L21/32139 , H01L21/31116 , H01L21/31144 , H01L21/32135 , H01L21/76838
摘要： PURPOSE: A method for forming a metal line of a semiconductor device is provided to prevent a fail interfering with an etch profile by using a titanium nitride film instead of silicon oxynitride film. CONSTITUTION: A metal layer(116), diffusion barrier layer, a titanium nitride(126) and a reflection barrier layer are laminated on the semiconductor substrate having a lower structure. A photoresist pattern(130) is formed on the reflection barrier layer. A titanium nitride pattern is formed by etching the lamination structure of titanium nitride film and reflection barrier layer through an etching process. A hard mask film pattern is formed by etching hard mask with the titanium nitride film pattern through a second etch process.
摘要翻译：目的：提供一种用于形成半导体器件的金属线的方法，以通过使用氮化钛膜代替氮氧化硅膜来防止干扰蚀刻轮廓的失败。构成：在具有较低结构的半导体衬底上层压金属层（116），扩散阻挡层，氮化钛（126）和反射阻挡层。在反射阻挡层上形成光致抗蚀剂图案（130）。通过蚀刻工艺蚀刻氮化钛膜和反射阻挡层的层叠结构，形成氮化钛图案。通过第二蚀刻工艺通过用氮化钛膜图案蚀刻硬掩模来形成硬掩模膜图案。

6. 发明公开

KR1020120067126A 반도체 소자 및 반도체 소자의 제조 방법 无效
标题翻译：半导体器件及其制造方法
公开(公告)号：KR1020120067126A
公开(公告)日：2012-06-25
申请号：KR1020100128572
申请日：2010-12-15
申请人： 에스케이하이닉스 주식회사
发明人： 김재영 , 유미현
IPC分类号： H01L21/28
CPC分类号： H01L21/76879 , H01L21/7685 , H01L21/76897 , H01L27/10855 , H01L27/10885 , H01L27/10888
摘要： PURPOSE: A semiconductor device and a manufacturing method thereof are provided to prevent the loss of a bit line contact plug and a bit line by performing a cleaning process after forming a storage electrode contact hole. CONSTITUTION: A bit line contact hole(107) includes a projecting active area(103). A first spacer(110a) is formed on an inner wall and a bottom portion of the bit line contact hole. A bit line contact plug(115) and a bit line(120) are prepared on an upper portion of an exposed active area. A second spacer(125) is formed on the surface of a semiconductor substrate including the bit line contact plug and the bit line. The first spacer and the second spacer include a nitride film.
摘要翻译：目的：提供一种半导体器件及其制造方法，以在形成存储电极接触孔之后执行清洁处理来防止位线接触插头和位线的损失。构成：位线接触孔（107）包括突出的有效区域（103）。第一间隔件（110a）形成在位线接触孔的内壁和底部。在暴露的有源区的上部准备位线接触插头（115）和位线（120）。在包括位线接触插头和位线的半导体衬底的表面上形成第二间隔物（125）。第一间隔物和第二间隔物包括氮化物膜。

7. 发明公开

KR1020090003730A 반도체 소자의 금속배선 형성 방법 无效
标题翻译：形成半导体器件金属线的方法
公开(公告)号：KR1020090003730A
公开(公告)日：2009-01-12
申请号：KR1020070066641
申请日：2007-07-03
申请人： 에스케이하이닉스 주식회사
发明人： 김세진 , 유미현
IPC分类号： H01L21/28
CPC分类号： H01L21/76877 , H01L21/32135
摘要： The method of forming the metal wiring in the semiconductor device is provided to increase the contact resistance and process margin by adding the O2 buffer gas by using the mixed gas of Ar and SF6 as the etching gas. The interlayer insulating film in which the metal wiring contact hole is equipped in the semiconductor substrate upper is formed. The tungsten layer burying the metal wiring contact hole on the semiconductor substrate is formed. The metal wiring contact plug is formed by etching the tungsten layer using the etching gas adding the O2 gas in the mixed gas of Ar and SF6. The metal wiring connected with the metal wiring contact plug is formed. The mixed ratio of Ar and SF6 is 18~20:1. The mixed ratio of the O2 gas to SF6 is 8~10:1. The rate of the bias voltage and the RF source voltage in the etching process is maintained by 12~13:1.
摘要翻译：提供了在半导体器件中形成金属布线的方法，通过使用Ar和SF6的混合气体作为蚀刻气体，通过添加O 2缓冲气体来提高接触电阻和加工余量。形成在半导体衬底上配置有金属配线接触孔的层间绝缘膜。形成在半导体衬底上埋设金属布线接触孔的钨层。通过在Ar和SF6的混合气体中添加O 2气体的蚀刻气体来蚀刻钨层，形成金属配线接触插塞。形成与金属布线接触插塞连接的金属布线。 Ar和SF6的混合比为18〜20：1。 O2气体与SF6的混合比例为8〜10：1。蚀刻工艺中的偏置电压和RF源电压的比率保持在12〜13：1。

8. 发明公开

KR1020080061872A 반도체 소자의 제조방법 无效
标题翻译：半导体器件制造方法
公开(公告)号：KR1020080061872A
公开(公告)日：2008-07-03
申请号：KR1020060137026
申请日：2006-12-28
申请人： 에스케이하이닉스 주식회사
发明人： 유미현 , 이정석
IPC分类号： H01L21/28
CPC分类号： H01L21/76802 , H01L21/31111 , H01L21/31144 , H01L21/76877 , H01L21/76897 , H01L27/10855
摘要： A method for manufacturing a semiconductor device is provided to secure overlay margin between storage electrode contact plugs by expanding the lower part of a contact hole through a wet etching although the contact plugs are misaligned. A first interlayer dielectric comprising a first storage electrode contact plug(14) is formed a semiconductor substrate. A second interlayer dielectric(12) is formed on the first interlayer dielectric. A first contact hole is formed by etching the second interlayer dielectric as a photolithograph using a second storage electrode contact mask. A nitride layer and a capping oxide layer are formed on the entire surface including the first contact hole. A second contact hole exposing the first storage electrode contact plug is formed by etching the lower part of the first contact hole. A conductive layer is formed on the entire surface including the first and second contact holes. A second storage electrode contact plug(36) is formed by performing a planarization process until the conductive layer is exposed.
摘要翻译：提供一种用于制造半导体器件的方法，用于通过通过湿蚀刻扩大接触孔的下部来确保接触插塞未对准，从而确保存储电极接触插塞之间的覆盖边界。包括第一存储电极接触插塞（14）的第一层间电介质形成半导体衬底。在第一层间电介质上形成第二层间电介质（12）。通过使用第二存储电极接触掩模通过蚀刻第二层间电介质作为光刻法形成第一接触孔。在包括第一接触孔的整个表面上形成氮化物层和覆盖氧化物层。暴露第一存储电极接触插塞的第二接触孔通过蚀刻第一接触孔的下部而形成。在包括第一和第二接触孔的整个表面上形成导电层。第二存储电极接触插塞（36）通过执行平面化处理直到导电层露出来形成。

9. 发明公开

KR1020080010951A 반도체 소자의 콘택홀 제조 방법 无效
标题翻译：用于在半导体器件中制作接触孔的方法
公开(公告)号：KR1020080010951A
公开(公告)日：2008-01-31
申请号：KR1020060071676
申请日：2006-07-28
申请人： 에스케이하이닉스 주식회사
发明人： 최익수 , 김석기 , 유미현 , 이해정
IPC分类号： H01L21/28
CPC分类号： H01L21/7685 , H01L21/31116 , H01L21/76802
摘要： A method for fabricating a contact hole in a semiconductor device is provided to inhibit etch residues generation simultaneously with reacting fluorinated etching gas during a via hole etching process. A method for fabricating a contact hole in a semiconductor device includes the steps of: forming a metal layer on an upper part of a substrate; forming a conductive barrier layer not to be reactive with the etch gas used during an etching process of an insulation layer formed on the metal layer; forming the insulation layer on the entire surface including the barrier layer; and forming holes to expose the barrier layer by etching the insulation layer.
摘要翻译：提供一种用于在半导体器件中制造接触孔的方法，用于在通孔蚀刻工艺期间与氟化蚀刻气体反应同时抑制蚀刻残留物产生。在半导体器件中制造接触孔的方法包括以下步骤：在衬底的上部形成金属层; 形成不与在金属层上形成的绝缘层的蚀刻工艺期间使用的蚀刻气体不反应的导电阻挡层; 在包括阻挡层的整个表面上形成绝缘层; 并通过蚀刻绝缘层形成孔以暴露阻挡层。

10. 发明公开

KR1020080003208A 반도체 소자의 스토리지노드 콘택 제조 방법 失效
标题翻译：在半导体器件中制造储存节点接触的方法
公开(公告)号：KR1020080003208A
公开(公告)日：2008-01-07
申请号：KR1020070037837
申请日：2007-04-18
申请人： 에스케이하이닉스 주식회사
发明人： 이해정 , 최익수 , 황창연 , 유미현
IPC分类号： H01L21/28
CPC分类号： H01L27/10855 , H01L21/31111 , H01L21/31144 , H01L21/76804 , H01L21/76897
摘要： A method for fabricating a storage node contact in a semiconductor device is provided to decrease the number of process steps by forming a plug capable of securing a contact area by one mask process. A method for fabricating a storage node contact in a semiconductor device includes the steps of: forming a landing plug(35) on a substrate(31); forming a first insulating film on the landing plug; forming a bit line pattern on the first insulating film; forming a second insulating film on the entire substrate on which the bit line pattern is formed; forming a mask pattern(41) for the storage node contact on the second insulating film; forming a storage node contact hole(42b) of a wine glass shape by etching the second insulating film and the first insulating film so as to expose the landing plug; forming a contact plug by burying a conductive material in the contact hole; and forming a storage node on the contact plug.
摘要翻译：提供一种用于在半导体器件中制造存储节点接触的方法，以通过形成能够通过一个掩模处理来确保接触面积的插头来减少工艺步骤的数量。一种用于在半导体器件中制造存储节点接触的方法包括以下步骤：在基底（31）上形成着陆塞（35）; 在着陆塞上形成第一绝缘膜; 在所述第一绝缘膜上形成位线图案; 在其上形成有位线图案的整个基板上形成第二绝缘膜; 在所述第二绝缘膜上形成用于所述存储节点接触的掩模图案（41）; 通过蚀刻所述第二绝缘膜和所述第一绝缘膜来形成所述酒杯形状的存储节点接触孔（42b），以暴露所述着陆塞; 通过在导电孔中埋入导电材料形成接触塞; 以及在所述接触插塞上形成存储节点。

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