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31. 发明授权

KR100243336B1 차동 증폭기 失效
标题翻译：差分放大器
公开(公告)号：KR100243336B1
公开(公告)日：2000-02-01
申请号：KR1019970062081
申请日：1997-11-21
申请人： 에스케이하이닉스 주식회사
发明人： 박낙규
IPC分类号： H03F3/45
摘要： 본 발명은 차동 증폭기에 관한 것으로, 특히 커런트 싱크를 다이오드 커넥션 형태로 구성하여 활성전류의 크기를 제어하고, 또다른 커런트 미러를 추가하여 전류의 진폭을 안정화시켜 저전류 소모 및 증폭률을 향상시킨 것이다.

32. 发明授权

KR101877820B1 컬럼 리페어 회로 有权
公开(公告)号：KR101877820B1
公开(公告)日：2018-08-08
申请号：KR1020120056120
申请日：2012-05-25
申请人： 에스케이하이닉스 주식회사
发明人： 박낙규
IPC分类号： G11C29/00 , G11C29/04 , G11C29/18
CPC分类号： G11C29/808 , G11C17/16 , G11C17/18 , G11C29/787
摘要： 컬럼리페어회로는조합매트어드레스생성부및 적어도 2 이상의퓨즈부를포함한다. 상기조합매트어드레스생성부는매트어드레스를수신하여인접한상기매트어드레스값을조합하고상기조합결과의인접한값을다시조합하는방식으로적어도 1회이상의조합단계를거치며, 수신한상기매트어드레스및 상기각 조합단계의상기조합결과를각 단계의조합매트어드레스로출력한다. 상기각각의퓨즈부는컬럼어드레스의각 비트에대하여상기조합매트어드레스에대응되는복수의퓨즈를포함하고, 상기조합매트어드레스에대응되는상기퓨즈의커팅여부에따라해당컬럼이리던던시컬럼으로대체된다. 이때상기각각의퓨즈부는어느하나의단계에서출력되는상기조합매트어드레스를각각수신한다.

33. 发明公开

KR1020120087712A 반도체 집적회로 无效
标题翻译：半导体集成电路
公开(公告)号：KR1020120087712A
公开(公告)日：2012-08-07
申请号：KR1020110009077
申请日：2011-01-28
申请人： 에스케이하이닉스 주식회사
发明人： 송근수 , 박낙규
IPC分类号： G11C11/4093 , G11C11/4096 , G11C11/408
CPC分类号： G11C11/4072 , G11C7/1045 , G11C11/4093 , G11C2207/105
摘要： PURPOSE: A semiconductor integrated circuit is provided to improve the productivity of the semiconductor integrated circuit by not using a fuse. CONSTITUTION: A first pad is allocated to input a row address(A13). A second pad is allocated to distinguish a first input and output method from a second input and output method. A detection unit(110) generates a detection signal in response to a logic level of the first pad and the second pad. A column address control unit(120) inactivates a column address(A9) in response to a detection signal. One of a first memory capacity and a second memory capacity and one of the first input and output method and the second input and output method are selectively supported by changing the logic levels of the first pad and the second pad.
摘要翻译：目的：提供半导体集成电路，通过不使用保险丝来提高半导体集成电路的生产率。构成：分配第一个焊盘以输入行地址（A13）。分配第二焊盘以区分第一输入和输出方法与第二输入和输出方法。检测单元（110）响应于第一焊盘和第二焊盘的逻辑电平产生检测信号。列地址控制单元（120）响应于检测信号而使列地址（A9）失活。通过改变第一焊盘和第二焊盘的逻辑电平来选择性地支持第一存储容量和第二存储容量之一以及第一输入和输出方法以及第二输入和输出方法之一。

34. 发明公开

KR1020110120463A 반도체장치 및 이의 동작방법, 메모리 시스템 有权
标题翻译：半导体器件及其相关开发方法，存储器系统
公开(公告)号：KR1020110120463A
公开(公告)日：2011-11-04
申请号：KR1020100039888
申请日：2010-04-29
申请人： 에스케이하이닉스 주식회사
发明人： 박낙규
IPC分类号： G11C5/14 , G11C7/22 , G11C8/00
CPC分类号： G11C5/148 , H03K17/22
摘要： PURPOSE: A semiconductor device, an operation method thereof, and a memory system are provided to reduce a current consumed in a semiconductor device by making the power down mode of an internal circuit during the locking operation of a clock supply circuit. CONSTITUTION: In a semiconductor device, an operation method thereof, and a memory system, a clock supply circuit(220) generates an internal clock. An internal circuit(210) is synchronized with the internal clock. The internal circuit is entered into a power down mode in response to a power down signal. A controller(230) controls a clock supply circuit to be entered into the power down mode.
摘要翻译：目的：提供半导体器件及其操作方法和存储器系统，以在时钟供给电路的锁定操作期间通过使内部电路的掉电模式来减少半导体器件中的电流消耗。构成：在半导体器件及其操作方法和存储器系统中，时钟供给电路（220）产生内部时钟。内部电路（210）与内部时钟同步。响应于掉电信号，内部电路进入掉电模式。控制器（230）控制时钟供给电路进入掉电模式。

35. 发明公开

KR1020110110554A 커맨드디코더 및 반도체 메모리 장치 有权
标题翻译： 커맨드디코더및반도체메모리장치
公开(公告)号：KR1020110110554A
公开(公告)日：2011-10-07
申请号：KR1020100029938
申请日：2010-04-01
申请人： 에스케이하이닉스 주식회사
发明人： 박낙규
IPC分类号： G11C8/10 , G11C7/22 , G11C7/10
CPC分类号： G11C7/22 , G11C7/1078 , G11C7/109 , G11C2207/2209
摘要： A command decoder includes a snoop read control signal generation unit that generates a snoop read control signal from a internal chip select signal according to a level of a transmission mode control signal, and an internal snoop read command generation unit that generates an internal snoop read command by driving a first node in response to an internal command and the snoop read control signal.
摘要翻译：命令解码器包括：窥探读取控制信号生成单元，根据传输模式控制信号的电平从内部芯片选择信号生成窥探读取控制信号;以及内部窥探读取命令生成单元，生成内部窥探读取命令通过响应于内部命令和窥探读取控制信号来驱动第一节点。

36. 发明授权

KR101046276B1 컬럼 리던던시 퓨즈 블록을 구비한 반도체 집적 회로 장치 有权
标题翻译：具有列冗余熔丝模块的半导体集成电路器件
公开(公告)号：KR101046276B1
公开(公告)日：2011-07-04
申请号：KR1020100064314
申请日：2010-07-05
申请人： 에스케이하이닉스 주식회사
发明人： 송근수 , 박낙규
IPC分类号： G11C29/04 , G11C8/12
摘要： 높은 유효 넷 다이를 확보할 수 있는 반도체 집적 회로 장치를 개시한다. 개시된 반도체 집적 회로 장치는, 에지 영역 및 상기 에지 영역 내측에 배치되는 뱅크 영역을 구비한 반도체 칩, 및 상기 에지 영역에 배치되는 컬럼 리던던시 퓨즈 블록을 포함한다.
摘要翻译：公开了一种能够确保高效净裸片的半导体集成电路器件。所公开的半导体集成电路器件包括半导体芯片和设置在边缘区域中的列冗余熔丝块，所述半导体芯片具有设置在边缘区域内的边缘区域和堤岸区域。

37. 发明公开

KR1020100102793A 반도체 집적 회로 无效
标题翻译：半导体集成电路
公开(公告)号：KR1020100102793A
公开(公告)日：2010-09-27
申请号：KR1020090021022
申请日：2009-03-12
申请人： 에스케이하이닉스 주식회사
发明人： 박낙규
IPC分类号： H03K19/173 , H01L21/82
CPC分类号： G11C29/40 , G11C29/44 , G11C29/70 , G11C29/808
摘要： PURPOSE: A semiconductor integrated circuit is provided to improve the layout area efficiency by adding a signal related to a redundancy information in order to provide repairing information without separate addition circuit. CONSTITUTION: A compressive blocK(212b) includes a pull-up circuit part(213), a pull-down circuit part(214), a test controlling part(215), and a latch part(L). The pull-up circuit part includes a fourth NAND gate(ND4), a fifth NAND gate(ND5), a sixth NAND gate(ND6), a third inverter(INV3), and a first p-type metal oxide semiconductor(MOS) transistor(P1). The pull-down circuit part includes a first NAND gate(ND1), a second NAND gate(ND2), a third NAND gate(ND3), a first inverter(INV1), a second inverter(INV2), and a first n-type MOS transistor(N1). The latch part includes a fourth inverter(INV4) and a fifth inverter(INV5).
摘要翻译：目的：提供一种半导体集成电路，通过添加与冗余信息有关的信号来提高布局面积效率，以便提供修复信息而无需单独的加法电路。构成：压缩串行（212b）包括上拉电路部分（213），下拉电路部分（214），测试控制部分（215）和闩锁部分（L）。上拉电路部分包括第四与非门（ND4），第五与非门（ND5），第六与非门（ND6），第三反相器（INV3）和第一p型金属氧化物半导体（MOS）晶体管（P1）。下拉电路部分包括第一NAND门（ND1），第二NAND门（ND2），第三NAND门（ND3），第一反相器（INV1），第二反相器（INV2）型的MOS晶体管（N1）。闩锁部分包括第四反相器（INV4）和第五反相器（INV5）。

38. 发明授权

KR100892687B1 반도체 집적회로의 온 다이 터미네이션 보정 장치 및 방법 有权
标题翻译：用于校准半导体集成电路的电极终止的装置和方法
公开(公告)号：KR100892687B1
公开(公告)日：2009-04-15
申请号：KR1020070114371
申请日：2007-11-09
申请人： 에스케이하이닉스 주식회사
发明人： 박낙규
IPC分类号： G11C7/10
CPC分类号： H03K19/0005 , H04L25/0298
摘要： An apparatus and a method for calibrating on-die termination of a semiconductor integrated circuit are provided to simplify a circuit configuration by reducing unnecessary power consumption. A comparing unit(300) compares a reference voltage and code converting voltage and outputs comparison result. A code controller(400) outputs the update signal for an external code according to a comparison result. A counter(500) increases or decreases an internal code according to a comparison result. The internal code is outputted as an external code according to external update code.
摘要翻译：提供了用于校准半导体集成电路的管芯端接的装置和方法，以通过减少不必要的功率消耗来简化电路配置。比较单元（300）比较参考电压和代码转换电压并输出比较结果。代码控制器（400）根据比较结果输出外部代码的更新信号。计数器（500）根据比较结果增加或减少内部代码。内部代码根据外部更新代码作为外部代码输出。

39. 发明授权

KR100646941B1 고주파수에서 안정적으로 파워 모드를 제어하기 위한반도체 메모리 장치 및 그것의 파워 모드 제어방법 有权
标题翻译： 고주파수에서안정적으로파워모드를제어하기위한반도체메모리장치및그것의파워모드제어방
公开(公告)号：KR100646941B1
公开(公告)日：2006-11-23
申请号：KR1020050067347
申请日：2005-07-25
申请人： 에스케이하이닉스 주식회사
发明人： 박낙규
IPC分类号： G11C11/406
摘要： A semiconductor memory device for stably controlling a power mode at high frequency and a power mode control method thereof are provided to generate an internal clock signal more stably by sensing an internal clock generation control signal at a high phase of a buffered clock signal and then generating the internal clock signal at a row phase. An input buffer part(111) buffers addresses, command signals, a clock signal and a clock enable signal. A clock enable latch part(119) generates an internal clock enable signal by latching the buffered clock enable signal. A control signal generation part(120) generates a first control signal to receive the addresses and the command signals and a second control signal to control the generation of an internal clock signal, by using the internal clock enable signal, the buffered clock signal and the buffered first control signal. An internal clock generation part(118) generates the internal clock signal by receiving the buffered clock signal in response to the second control signal. A latch part generates internal addresses and command signals by receiving the buffered addresses and the command signals in synchronization with the internal clock signal. The input buffer part buffers the first control signal. The control signal generation part generates the first control signal by using the internal clock enable signal, and generates the second control signal by synchronizing the first control signal and the buffered first control signal with the buffered clock signal.
摘要翻译：提供一种用于稳定地控制高频功率模式的半导体存储器件及其功率模式控制方法，以通过感测缓冲时钟信号的高相位处的内部时钟产生控制信号并且然后产生内部时钟信号来更稳定地产生内部时钟信号内部时钟信号在行相位。输入缓冲器部分（111）缓冲地址，命令信号，时钟信号和时钟使能信号。时钟使能锁存部分（119）通过锁存缓冲时钟使能信号来产生内部时钟使能信号。控制信号生成部分（120）通过使用内部时钟使能信号，缓冲时钟信号和第一控制信号生成部分（120）生成用于接收地址和命令信号的第一控制信号以及用于控制内部时钟信号的生成的第二控制信号缓冲的第一控制信号。内部时钟产生部分（118）响应于第二控制信号通过接收缓冲时钟信号来产生内部时钟信号。锁存器部分通过与内部时钟信号同步地接收缓冲地址和命令信号来产生内部地址和命令信号。输入缓冲器部分缓冲第一控制信号。控制信号生成部分通过使用内部时钟使能信号生成第一控制信号，并且通过使第一控制信号和缓冲的第一控制信号与缓冲时钟信号同步来生成第二控制信号。

40. 发明授权

KR100608362B1 펄스 발생기 失效
标题翻译：脉冲发生器
公开(公告)号：KR100608362B1
公开(公告)日：2006-08-08
申请号：KR1020040027889
申请日：2004-04-22
申请人： 에스케이하이닉스 주식회사
发明人： 박낙규
IPC分类号： G11C7/00
CPC分类号： H03K3/033 , H03K3/355
摘要： 본 발명은 입력신호의 주파수와 무관하게 일정한 펄스 폭을 갖는 신호를 출력하는 내부 펄스 발생기에 관한 것이다.
본 발명의 펄스 발생기는 전원전압과 접지사이에 직렬로 연결된 PMOS 트랜지스터(P82)와 PMOS 트랜지스터(P83)와 NMOS 트랜지스터(N83)와, NMOS 트랜지스터(N83)의 드레인인 노드(a)와 출력단자(out)사이에 연결된 래치(INV84, INV85)와, PMOS 트랜지스터(P83)와 NMOS 트랜지스터(N83)의 공통 게이트인 노드(b)와 출력단자(out)사이에 연결된 Y 시간 지연부(82)를 구비한다.

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