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1. 发明公开

KR1020140080903A 반도체 장치 审中-实审
标题翻译：半导体器件
公开(公告)号：KR1020140080903A
公开(公告)日：2014-07-01
申请号：KR1020120149964
申请日：2012-12-20
申请人： 에스케이하이닉스 주식회사
发明人： 박낙규
IPC分类号： G11C7/10 , G11C7/22 , G11C5/14
CPC分类号： H03K5/26 , H03K5/2481
摘要： The present invention relates to a semiconductor device using a differential signal, and including: a first differential amplifier amplifying an external differential signal having a swing width and a differential input cross-point voltage (VIX) defined within a tolerable range of an external voltage with the external voltage, and generating an internal differential signal; a control circuit unit adjusting the swing width and VIX of the internal differential signal to be within the tolerable range of the internal voltage, which has lower voltage level than the external voltage, in response to a control signal; a second differential amplification unit amplifying the internal differential signal of which the swing width and VIX are adjusted by the control circuit unit with the internal voltage and generating an internal synchronization signal; and a duty correction unit correcting a duty of the internal synchronization signal using the internal voltage.
摘要翻译：本发明涉及一种使用差分信号的半导体器件，包括：放大外部差分信号的第一差分放大器，其具有在外部电压的可容许范围内定义的摆幅宽度和差分输入交叉点电压（VIX）外部电压，并产生内部差分信号; 控制电路单元，响应于控制信号，将所述内部差分信号的摆动宽度和VIX调整在比外部电压低的电压的内部电压的容许范围内; 第二差分放大单元，利用所述内部电压放大所述控制电路单元的摆幅和VIX的内差分信号，并产生内部同步信号; 以及占空比校正单元，使用内部电压校正内部同步信号的占空比。

2. 发明公开

KR1020120070428A 반도체 메모리 장치의 내부 클럭 생성 회로 无效
标题翻译：半导体存储器内部时钟发生电路
公开(公告)号：KR1020120070428A
公开(公告)日：2012-06-29
申请号：KR1020100131986
申请日：2010-12-21
申请人： 에스케이하이닉스 주식회사
发明人： 박낙규 , 송근수
IPC分类号： G11C7/22 , G11C7/10
CPC分类号： G11C7/222 , G11C2207/2227 , G11C2207/2272
摘要： PURPOSE: An inner clock generating circuit of a semiconductor memory device is provided to reduce power consumption by providing an inner clock with a different duty ratio according to a high speed operation and a low speed operation. CONSTITUTION: A clock delay control unit(100) outputs a delay clock by delaying a clock if a frequency of a clock is lower than a preset frequency and sets a delay clock with a specific level if the frequency of the clock is higher than the preset frequency. An inner clock generating unit(200) outputs the clock as the inner clock if the delay clock is set with the specific level. The inner clock generating unit generates an inner clock with a high section from a high level transition point of the clock to the high level transition point of the delay clock if the clock is delayed.
摘要翻译：目的：提供半导体存储器件的内部时钟发生电路，以通过根据高速操作和低速操作提供具有不同占空比的内部时钟来降低功耗。构成：如果时钟频率低于预设频率，时钟延迟控制单元（100）通过延迟时钟来输出延迟时钟，并且如果时钟的频率高于预设的频率，则设置具有特定电平的延迟时钟频率。如果延迟时钟被设置为特定电平，则内部时钟产生单元（200）将时钟作为内部时钟输出。如果时钟被延迟，则内部时钟产生单元产生具有从时钟的高电平转变点到延迟时钟的高电平转变点的高部分的内部时钟。

3. 发明公开

KR1020110001410A 임피던스 조정 회로 및 이를 이용한 반도체 장치 有权
标题翻译：用于校准阻抗和半导体装置的电路
公开(公告)号：KR1020110001410A
公开(公告)日：2011-01-06
申请号：KR1020090058932
申请日：2009-06-30
申请人： 에스케이하이닉스 주식회사
发明人： 박낙규
IPC分类号： G11C7/10
CPC分类号： G11C5/06 , H01L25/0657 , H01L2224/16
摘要： PURPOSE: An impedance control circuit and a semiconductor device using the same are provided to reduce the circuit area by comprising one external resistance regardless of the number of die inside the semiconductor package. CONSTITUTION: An enable signal generation unit(210) generates the enable signal in response to the chip select signal. A code generation part(211) generates the impedance correction code using the external resistance connected to an electrode. A digital to analog converter(220) changes the internal code into the code voltage.
摘要翻译：目的：提供阻抗控制电路和使用该阻抗控制电路的半导体器件，以便与半导体封装内的管芯数量无关地包括一个外部电阻来减小电路面积。构成：使能信号生成单元（210）响应于芯片选择信号生成使能信号。代码生成部（211）使用与电极连接的外部电阻来生成阻抗校正码。数模转换器（220）将内部代码改变为代码电压。

4. 发明公开

KR1020100123043A 반도체 집적회로 无效
标题翻译：半导体集成电路
公开(公告)号：KR1020100123043A
公开(公告)日：2010-11-24
申请号：KR1020090042044
申请日：2009-05-14
申请人： 에스케이하이닉스 주식회사
发明人： 박낙규
IPC分类号： G11C5/14 , G11C8/12
CPC分类号： G11C5/14 , G05F1/465 , G11C29/021
摘要： PURPOSE: The semiconductor IC individually controls internal voltage generators with minimizing the signal line burden. Steadily, the internal voltage is offered. CONSTITUTION: The voltage generation block(110) comprises a plurality of voltage generation units. The voltage generation unit controls the voltage generating operation in response to the goal ID. With the active type which the voltage generation unit is appointed in the normal operation for the active state.
摘要翻译：目的：半导体IC单独控制内部电压发生器，使信号线负担最小化。稳定地提供内部电压。构成：电压产生块（110）包括多个电压产生单元。电压产生单元响应于目标ID来控制电压产生操作。利用在激活状态的正常操作中指定电压产生单元的有源类型。

5. 发明授权

KR100935598B1 컬럼 어드레스 제어 회로 및 이를 이용한 반도체 메모리장치 失效
标题翻译：用于控制列地址的电路和使用其的半导体存储器件
公开(公告)号：KR100935598B1
公开(公告)日：2010-01-07
申请号：KR1020080013477
申请日：2008-02-14
申请人： 에스케이하이닉스 주식회사
发明人： 박낙규
IPC分类号： G11C8/18 , G11C8/06 , G11C29/00
摘要： 본 발명은 라이트 신호, 및 리드 신호에 응답하여 어드레스를 컬럼 어드레스로서 출력하며 제어 신호에 응답하여 상기 컬럼 어드레스의 레벨을 반전시켜 출력하는 컬럼 어드레스 출력부, 및 테스트 신호 및 카운팅 인에이블 신호에 응답하여 상기 제어 신호를 생성하는 제어부를 포함한다.
컬럼 어드레스, 최하위 비트 어드레스, 테스트, 데이터 출력

6. 发明公开

KR1020090088119A 컬럼 어드레스 제어 회로 및 이를 이용한 반도체 메모리장치 失效
标题翻译：用于控制柱地址的电路和使用其的半导体存储器装置
公开(公告)号：KR1020090088119A
公开(公告)日：2009-08-19
申请号：KR1020080013477
申请日：2008-02-14
申请人： 에스케이하이닉스 주식회사
发明人： 박낙규
IPC分类号： G11C8/18 , G11C8/06 , G11C29/00
CPC分类号： G11C8/18 , G11C7/1051 , G11C7/1078 , G11C8/06 , G11C29/022 , G11C29/56
摘要： A column address control circuit and a semiconductor memory device using the same are provided to reduce the manufacturing cost using the test equipment of the low speed motion. A column address control circuit comprises a column address output part(100) and a controller(200). The column address output part outputs the address(Add) to the column address(Yadd) by corresponding to the write signal(WT) and the read signal(RD). The column address output part inverts the level of the column address corresponding to the control signal(crl1) and outputs the column address which is level-inverted. The controller produces the control signal by corresponding to the test signal(Test) and the counting enable signal(Icasp).
摘要翻译：提供列地址控制电路和使用该列地址控制电路的半导体存储器件，以使用低速运动的测试设备来降低制造成本。列地址控制电路包括列地址输出部分（100）和控制器（200）。列地址输出部分通过对应写入信号（WT）和读取信号（RD）将地址（Add）输出到列地址（Yadd）。列地址输出部分反转与控制信号（crl1）对应的列地址的电平，并输出电平反转的列地址。控制器根据测试信号（测试）和计数使能信号（Icasp）产生控制信号。

7. 发明授权

KR100849065B1 동기식 메모리 장치의 드라이버 및 오디티 임피던스 조절방법 有权
标题翻译：用于校准驱动器和同步存储器件的ODT的方法
公开(公告)号：KR100849065B1
公开(公告)日：2008-07-30
申请号：KR1020050124072
申请日：2005-12-15
申请人： 에스케이하이닉스 주식회사
发明人： 박낙규
IPC分类号： G11C7/00 , G11C7/10
CPC分类号： H03K19/0005 , G11C7/1051 , G11C7/1057 , G11C29/02 , G11C29/022 , G11C29/025 , G11C29/028 , G11C29/50008 , G11C2207/2254 , H04L25/0278
摘要： 동기식 메모리 장치의 드라이버 및 ODT 임피던스 조절 방법은 (a)조절 동작 모드 진입을 나타내는 조절 인에이블 신호 발생 단계;(b)일정 시간 간격마다 ODT 조절을 위한 코드 신호를 순차적으로 발생하는 단계;(c)상기 조절 인에이블 신호에 기초하여 발생하는 제 1 제어 신호를 생성하는 단계; (d)상기 제 1 제어 신호를 상기 순차적으로 발생되는 코드 신호중에서 마지막 코드 신호를 래치하여, 드라이버 및 ODT 임피던스 조절 신호로 사용하는 단계를 구비한다.

8. 发明授权

KR100845807B1 온 다이 터미네이션 제어신호 생성회로 有权
标题翻译：电路终端控制信号发生电路
公开(公告)号：KR100845807B1
公开(公告)日：2008-07-14
申请号：KR1020070057582
申请日：2007-06-13
申请人： 에스케이하이닉스 주식회사
发明人： 박낙규
IPC分类号： G11C7/10
CPC分类号： G11C11/406 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1057 , G11C7/1078 , G11C7/1084 , G11C11/40611 , G11C11/40615 , G11C11/4093 , G11C7/22 , H03K19/017545 , H04L25/0278
摘要： A circuit for generating an on-die termination control signal is provided to prevent adjustment error according as performing on-die termination calibration operation in a period except normal operation period. A first signal generation part(100) generates a first signal to prevent first on-die termination calibration during a fixed period in order to change a voltage or a frequency. A second signal generation part(200) generates a second signal in order to perform second on-die termination calibration operation at initial time of operation. A signal output part(300) outputs an on-die termination control signal by assembling the first signal and the second signal. The fixed period includes a self refresh period.
摘要翻译：提供一种用于产生片上终止控制信号的电路，以防止在除了正常操作时段之外的周期中执行片上终止校准操作的调整误差。第一信号产生部分（100）产生第一信号以防止在固定时段期间的第一片上终端校准，以便改变电压或频率。第二信号产生部分（200）产生第二信号，以便在初始操作时执行第二次片上终止校准操作。信号输出部（300）通过组装第一信号和第二信号来输出片上终端控制信号。固定期间包括自刷新期间。

9. 发明公开

KR1020080029309A 반도체 메모리 장치 有权
标题翻译：半导体存储器件
公开(公告)号：KR1020080029309A
公开(公告)日：2008-04-03
申请号：KR1020060095181
申请日：2006-09-28
申请人： 에스케이하이닉스 주식회사
发明人： 박낙규
IPC分类号： G11C8/12 , G11C7/10 , G11C11/40
CPC分类号： G11C8/12 , G11C5/025 , G11C5/063 , G11C7/1048 , G11C7/18 , G11C11/4093 , G11C11/4097 , G11C2207/105
摘要： A semiconductor memory device is provided to reduce loading of a global line to use a bank region during read operation and write operation separately, and to generate a bank strobe signal in the bank region. A semiconductor memory device comprises a global input/output line, a first global core line, a second global core line, a global core line controller(100,200,300,400), a first bank and a second bank. The global core line controller is formed between the global input/output line and the first and the second global core line. The first bank is connected to the global core line controller through the first global core line. The second bank is connected to the global core line controller through the second global core line. The global core line controller controls the first global core line and the second global core line separately.
摘要翻译：提供了一种半导体存储器件，用于在读操作和写操作期间单独地减少全局线的负载以使用存储体区，并在存储区中产生存储体选通信号。半导体存储器件包括全局输入/输出线，第一全局核心线，第二全局核心线，全局核心线控制器（100,200,300,400），第一组和第二组。全局核心线控制器形成在全局输入/输出线与第一和第二全局核心线之间。第一家银行通过第一个全球核心线连接到全球核心线控制器。第二家银行通过第二个全球核心线连接到全球核心线控制器。全球核心线控制器分别控制第一个全球核心线和第二个全球核心线。

10. 发明授权

KR100795025B1 ＤＬＬ 회로의 동작 모드 설정 장치 및 방법 失效
标题翻译：在DLL电路中设置操作模式的装置和方法
公开(公告)号：KR100795025B1
公开(公告)日：2008-01-16
申请号：KR1020060123567
申请日：2006-12-07
申请人： 에스케이하이닉스 주식회사
发明人： 박낙규
IPC分类号： H03L7/00
CPC分类号： H03L7/0805 , G11C7/22 , H03L7/0814
摘要： An apparatus and a method for setting an operation mode in a DLL(Delay Locked Loop) are provided to decrease the possibility of an operational error by generating a locking completion signal according to the phase difference between a reference clock and a feedback clock only in case that the interval with the same phase of the reference clock and the feedback clock is wider than that with the different phase. An apparatus includes a reset unit(10), a power supply unit(20), a first control unit(30), a second control unit(40), an output control unit(60), and a latch unit(50). The reset unit controls the potential of a first node(N1) in response to the input of a reset signal(rst). The power supply unit supplies power to a second node(N2) in response to the input of a locking completion signal(lock) and a pulse signal(pls). The first control unit controls the potentials of the first and second nodes in response to the input of a phase comparing unit(phcmp) and the pulse signal. The second control unit controls the potential of the second node in response to the input of the phase comparing unit and the pulse signal. The output control unit generates an output control signal(outcon) by comparing the phases of a reference clock(clk_ref) and a feedback clock(clk_fb). The latch unit latches the potential of the first node, and outputs the locking completion signal according to whether the output control signal is enabled or not.
摘要翻译：提供了一种用于设置DLL（延迟锁定环路）中的操作模式的装置和方法，用于通过仅在基准时钟和反馈时钟之间的相位差产生锁定完成信号来减小操作错误的可能性，参考时钟和反馈时钟相同相位的间隔比不同相位的间隔更宽。一种装置，包括复位单元（10），电源单元（20），第一控制单元（30），第二控制单元（40），输出控制单元（60）和锁存单元（50）。复位单元响应于复位信号（rst）的输入来控制第一节点（N1）的电位。响应于锁定完成信号（锁定）和脉冲信号（pls）的输入，电源单元向第二节点（N2）供电。第一控制单元响应于相位比较单元（phcmp）和脉冲信号的输入来控制第一和第二节点的电位。第二控制单元响应于相位比较单元和脉冲信号的输入来控制第二节点的电位。输出控制单元通过比较参考时钟（clk_ref）和反馈时钟（clk_fb）的相位来产生输出控制信号（outcon）。锁存单元锁存第一节点的电位，并根据输出控制信号是否使能输出锁定完成信号。

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