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21. 发明授权

KR100558543B1 에스·오·아이(ＳＯＩ) 웨이퍼 제조방법 失效
标题翻译：制造SOI晶片的方法
公开(公告)号：KR100558543B1
公开(公告)日：2006-03-10
申请号：KR1019990054181
申请日：1999-12-01
申请人： 삼성전자주식회사
发明人： 곽성호 , 김병선
IPC分类号： H01L21/20
摘要： SOI 웨이퍼의 구조를 변경하여, 상기 웨이퍼를 사용하여 SOI 소자를 제조할 때 야기되던 플로우팅 바디 효과(floating body effect)를 감소시킬 수 있도록 한 SOI 웨이퍼 제조방법이 개시된다.
이를 구현하기 위하여 본 발명에서는, 제 1 실리콘층을 준비한 후, 상기 실리콘층 상에 Si
1-X Ge
x 를 형성하는 단계와; 상기 Si
1-X Ge
x 상으로 하이드로겐을 이온주입하여, 상기 제 1 실리콘층 내에 소정 깊이의 하이드로겐 주입 영역을 형성하는 단계와; 제 2 실리콘층을 준비한 후, 상기 실리콘층 상에 BOX층을 형성하는 단계와; 상기 Si
1-X Ge
x (X는 Si과 Ge의 조성비를 나타낸 것으로, 0.5 ~ 1의 값을 갖는다)와 상기 BOX층이 마주보도록 상기 제 1 실리콘층과 상기 제 2 실리콘층을 위치 정렬한 후 이들 두 실리콘 기판을 접합하는 단계; 및 상기 제 1 실리콘층중, 하이드로겐이 주입되지 않은 부분을 절단하는 단계로 이루어진 SOI 웨이퍼 제조방법이 제공된다.

22. 发明授权

KR100464443B1 이피롬(ＥＰＲＯＭ, ＥｒａａｂｌｅＰｒｏｇｒａｍｍａｂｌｅＲｅａｄＯｎｌｙＭｅｍｏｒｙ} 소자의 셀 구조 및 그 제조방법 失效
标题翻译： 피롬（EPROM，EraableProgrammable Read OnlyMemory）소자의셀구조및그제조방
公开(公告)号：KR100464443B1
公开(公告)日：2005-01-03
申请号：KR1020030001815
申请日：2003-01-11
申请人： 삼성전자주식회사
发明人： 이태정 , 김병선 , 이준형
IPC分类号： H01L27/115
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324 , H01L29/7885
摘要： A cell structure of a non-volatile memory device, which uses a nitride layer as a floating gate spacer, includes a gate stack and a floating gate transistor formed over a semiconductor substrate. The gate stack includes a first portion of a floating gate, a control gate formed over the first portion of the floating gate, and a non-nitride spacer adjacent to sidewalls of the first portion of floating gate. The floating gate transistor includes a second portion of the floating gate, which substantially overlaps a source and/or drain formed in the substrate. The application of ultraviolet rays to the non-nitride spacer of a programmed cell can causes the second portion of the floating gate to discharge, thereby easily erasing the programmed cell.
摘要翻译：使用氮化物层作为浮栅隔离物的非易失性存储器件的单元结构包括形成在半导体衬底上的栅极堆叠和浮置栅极晶体管。栅极叠层包括浮置栅极的第一部分，形成在浮置栅极的第一部分上方的控制栅极以及与浮置栅极的第一部分的侧壁相邻的非氮化物间隔物。浮动栅极晶体管包括浮动栅极的第二部分，其基本上与形成在衬底中的源极和/或漏极重叠。将紫外线施加到已编程单元的非氮化物隔离物上会导致浮栅的第二部分放电，从而容易擦除已编程的单元。

23. 发明授权

KR100464442B1 이피롬(ＥＰＲＯＭ, ＥｒａａｂｌｅＰｒｏｇｒａｍｍａｂｌｅＲｅａｄＯｎｌｙＭｅｍｏｒｙ)소자의 셀 구조 및 그 제조방법 失效
标题翻译： 피피롬（EPROM，EraableProgrammable Read OnlyMemory）소자의셀구조및그제조방
公开(公告)号：KR100464442B1
公开(公告)日：2005-01-03
申请号：KR1020030001814
申请日：2003-01-11
申请人： 삼성전자주식회사
发明人： 이준형 , 김병선 , 이태정
IPC分类号： H01L27/115
CPC分类号： H01L21/28273 , H01L29/42324 , H01L29/513 , H01L29/66825 , H01L29/7881
摘要： Provided are a cell structure of an EPROM device and a method for fabricating the same. The cell structure includes a gate stack, which includes a first floating gate, an insulating pattern including a nitride layer, and a control gate that are sequentially stacked on a semiconductor substrate, and includes a window for exposing the top surface or both sidewalls of the first floating gate on both sides of the control gate, so that charges of the first floating gate can be erased by ultraviolet rays. The cell structure further includes a floating gate transistor, which includes a gate insulating layer formed on the semiconductor substrate, a second floating gate that is formed on the gate insulating layer and is connected to the first floating gate in the gate stack, and a source/drain that is formed in the semiconductor substrate so as to be aligned to the second floating gate. In the cell structure, the window is formed on the top surface or both sidewalls of the first floating gate of the gate stack. Thus, ultraviolet rays can penetrate through the window and easily erase charges of the programmed cell.
摘要翻译：提供了一种EPROM器件的单元结构及其制造方法。所述单元结构包括栅极叠层，其包括第一浮置栅极，包括氮化物层的绝缘图案以及控制栅极，所述绝缘图案顺序地堆叠在半导体衬底上，并且包括用于暴露所述第一浮置栅极的顶表面或两个侧壁第一浮置栅极位于控制栅极的两侧，使得第一浮置栅极的电荷可以被紫外线消除。该单元结构进一步包括浮置栅极晶体管，该浮置栅极晶体管包括形成在半导体衬底上的栅极绝缘层，形成在栅极绝缘层上并连接到栅极堆叠中的第一浮置栅极的第二浮置栅极， /漏极，其形成在半导体基板中以便与第二浮置栅极对准。在单元结构中，窗口形成在栅极堆叠的第一浮置栅极的顶表面或两个侧壁上。因此，紫外线可穿透窗口并容易擦除已编程单元的电荷。

24. 发明公开

KR1020040054361A 더블 포트 반도체 메모리 장치 有权
标题翻译：双端口半导体存储器件
公开(公告)号：KR1020040054361A
公开(公告)日：2004-06-25
申请号：KR1020020081393
申请日：2002-12-18
申请人： 삼성전자주식회사
发明人： 이태정 , 김병선 , 이준형
IPC分类号： G11C11/40
CPC分类号： G11C8/16
摘要： PURPOSE: A double port semiconductor memory device is provided to reduce an area occupied by an isolation area formed at a boundary between a N-well and a P-well. CONSTITUTION: A semiconductor substrate includes a memory cell divided into a N-well and a P-well. The semiconductor memory device includes the first word line, the second word line, the first bit line and the second bit line. The first CMOS inverter includes the first NMOS transistor(N1), the first PMOS transistor(P1) and an input terminal and an output terminal. The second CMOS inverter includes the second NMOS transistor(N2), the second PMOS transistor(P2) and an input terminal and an output terminal. The third NMOS transistor(N3) has a gate connected to the first word line, and a drain connected to the first bit line and a source connected to the first memory node(N1). The fourth NMOS transistor(N4) has a gate connected to the first word line, a drain connected to the first bit line and a source connected to the second memory node(N2). The fifth NMOS transistor(N5) has a gate connected to the first memory node and a source connected to a ground line. And the sixth NMOS transistor(N6) has a gate connected to the second word line, a source connected to the drain of the fifth NMOS transistor and a drain connected to the second bit line.
摘要翻译：目的：提供双端口半导体存储器件，以减少形成在N阱和P阱之间的边界处的隔离区所占据的面积。构成：半导体衬底包括分为N阱和P阱的存储单元。半导体存储器件包括第一字线，第二字线，第一位线和第二位线。第一CMOS反相器包括第一NMOS晶体管（N1），第一PMOS晶体管（P1）和输入端子以及输出端子。第二CMOS反相器包括第二NMOS晶体管（N2），第二PMOS晶体管（P2）和输入端子以及输出端子。第三NMOS晶体管（N3）具有连接到第一字线的栅极，连接到第一位线的漏极和连接到第一存储器节点（N1）的源极。第四NMOS晶体管（N4）具有连接到第一字线的栅极，连接到第一位线的漏极和连接到第二存储器节点（N2）的源极。第五NMOS晶体管（N5）具有连接到第一存储器节点的栅极和连接到地线的源极。并且第六NMOS晶体管（N6）具有连接到第二字线的栅极，连接到第五NMOS晶体管的漏极的源极和连接到第二位线的漏极。

25. 发明公开

KR1020030001835A ＳＯＩ 기판을 채용한 반도체 소자의 제조방법 无效
标题翻译：使用SOI衬底制造半导体器件的方法
公开(公告)号：KR1020030001835A
公开(公告)日：2003-01-08
申请号：KR1020010037642
申请日：2001-06-28
申请人： 삼성전자주식회사
发明人： 오명환 , 김병선 , 유승한 , 신명선 , 이태정
IPC分类号： H01L27/12 , H01L29/78 , H01L21/84
摘要： PURPOSE: A method for fabricating a semiconductor device by using an SOI substrate is provided to remove a short-circuit phenomenon between a local wire and a silicon layer by preventing the formation of a recess portion on a field region. CONSTITUTION: A trench oxide layer(17) is formed on a trench of a silicon layer(15) of an SOI substrate in order to define a field region(FR) and an active region(AR). A gate electrode is formed on the active region(AR). The first contact hole is formed by patterning the field oxide layer(17), the silicon layer(15), and a buried oxide layer(13) of the field region(FR). A gate spacer(23) is formed on a side wall of the gate electrode. A sidewall spacer(25) is formed on both sidewalls of the first contact hole. A plurality of silicide layers(27a,27b,27c) are formed on the exposed lower silicon substrate(11). A recess barrier and the first photoresist pattern are formed thereon. A field recess barrier pattern(29a), an interlayer dielectric(33), and the second photoresist pattern(35) are formed thereon. The second contact hole(37) is formed by patterning the interlayer dielectric(33).
摘要翻译：目的：提供一种通过使用SOI衬底制造半导体器件的方法，以通过防止在场区域上形成凹陷部分来消除局部线和硅层之间的短路现象。构成：为了限定场区（FR）和有源区（AR），在SOI衬底的硅层（15）的沟槽上形成沟槽氧化物层（17）。在有源区（AR）上形成栅电极。通过对场区（17），硅层（15）和场区（FR）的掩埋氧化物层（13）进行构图来形成第一接触孔。栅极间隔物（23）形成在栅电极的侧壁上。侧壁间隔件（25）形成在第一接触孔的两个侧壁上。在暴露的下硅基板（11）上形成多个硅化物层（27a，27b，27c）。在其上形成凹陷屏障和第一光致抗蚀剂图案。在其上形成场凹陷屏障图案（29a），层间电介质（33）和第二光致抗蚀剂图案（35）。第二接触孔（37）通过图案化层间电介质（33）而形成。

26. 发明公开

KR1020030001834A ＳＯＩ 기판을 채용한 반도체 소자의 제조방법 无效
标题翻译：使用SOI衬底制造半导体器件的方法
公开(公告)号：KR1020030001834A
公开(公告)日：2003-01-08
申请号：KR1020010037641
申请日：2001-06-28
申请人： 삼성전자주식회사
发明人： 오명환 , 김병선 , 이태정
IPC分类号： H01L27/12 , H01L29/78 , H01L21/84
摘要： PURPOSE: A method for fabricating a semiconductor device using an SOI substrate is provided to prevent the formation of a recess portion on a trench oxide layer of a field region when a contact hole is formed on the SOI substrate. CONSTITUTION: A trench oxide layer(17) is formed on a trench of a silicon layer(15) of an SOI substrate in order to define a field region(FR) and an active region(AR). A gate electrode is formed on the active region(AR). The first contact hole is formed on the field region(FR) by patterning the field oxide layer(17), the silicon layer(15), and a buried oxide layer(13) of the field region(FR). A gate spacer is formed on a side wall of the gate electrode. A sidewall spacer is formed on both sidewalls of the first contact hole. A plurality of silicide layers(27a,27b,27c) are formed on an exposed lower silicon substrate(11). The first etch stopper(29), the first interlayer dielectric(31), the second etch stopper(33), and the second interlayer dielectric(35) are serially formed thereon. The second interlayer dielectric(35) is patterned by using the second etch stopper(33). The second etch stopper(33) and the first interlayer dielectric(31) are patterned by using the first etch stopper(29). The second contact hole(39) is formed to expose the lower silicon substrate(11) of the field region(FR) and the silicon layer(15) of the active region(AR).
摘要翻译：目的：提供一种使用SOI衬底制造半导体器件的方法，以防止在SOI衬底上形成接触孔时在场区的沟槽氧化物层上形成凹陷部分。构成：为了限定场区（FR）和有源区（AR），在SOI衬底的硅层（15）的沟槽上形成沟槽氧化物层（17）。在有源区（AR）上形成栅电极。通过对场区（FR）的场氧化物层（17），硅层（15）和掩埋氧化物层（13）进行构图，在场区（FR）上形成第一接触孔。栅极间隔件形成在栅电极的侧壁上。侧壁间隔件形成在第一接触孔的两个侧壁上。在暴露的下硅基板（11）上形成多个硅化物层（27a，27b，27c）。第一蚀刻停止器（29），第一层间电介质（31），第二蚀刻停止器（33）和第二层间电介质（35）被顺序地形成在其上。通过使用第二蚀刻停止器（33）对第二层间电介质（35）进行构图。通过使用第一蚀刻停止器（29）对第二蚀刻停止器（33）和第一层间电介质（31）进行构图。第二接触孔（39）形成为暴露场区（FR）的下硅衬底（11）和有源区（AR）的硅层（15）。

27. 发明授权

KR100343147B1 에스오아이 모스 트랜지스터를 구비한 반도체 소자 및신호 처리 장치 失效
标题翻译：具有SOO IMMOS晶体管的半导体器件和信号处理装置
公开(公告)号：KR100343147B1
公开(公告)日：2002-07-06
申请号：KR1020000066212
申请日：2000-11-08
申请人： 삼성전자주식회사
发明人： 정무경 , 김병선
IPC分类号： H01L29/78
摘要： SOI 구조를 가지는 MOS 트랜지스터를 구비한 본 발명에 따른 반도체 소자 및 신호 처리 장치는 메인 MOS 트랜지스터와 어시스턴스 MOS 트랜지스터를 포함한다. 메인 MOS 트랜지스터는 외부 신호를 받는 제1 게이트 배선과, 제1 도전형의 제1 소스/드레인 영역과, 바디를 포함한다. 어시스턴스 MOS 트랜지스터는 제2 게이트 배선과, 제1 도전형과 반대인 제2 도전형의 제2 소스/드레인 영역을 포함한다. 어시스턴스 MOS 트랜지스터는 외부 신호에 따라 바디를 플로팅 상태 또는 그라운딩 상태로 선택적으로 전환시키기는 역할을 한다. 제1 게이트 배선과 제2 게이트 배선은 배선층에 의하여 서로 전기적으로 접속되어 있다.

28. 发明公开

KR1020020036170A 에스오아이 모스 트랜지스터를 구비한 반도체 소자 및신호 처리 장치 失效
标题翻译：具有绝缘体的金属氧化物半导体晶体管的半导体器件和处理信号的装置
公开(公告)号：KR1020020036170A
公开(公告)日：2002-05-16
申请号：KR1020000066212
申请日：2000-11-08
申请人： 삼성전자주식회사
发明人： 정무경 , 김병선
IPC分类号： H01L29/78
CPC分类号： H01L27/1203 , H01L23/522 , H01L27/0207 , H01L29/7841 , H01L2924/0002 , H01L2924/00
摘要： PURPOSE: A semiconductor device having a silicon-on-insulator(SOI) metal-oxide-semiconductor(MOS) transistor is provided to make the body of a main MOS transistor grounded and to reduce a leakage current in an off-state of the main MOS transistor, by connecting the body extending from the channel region of the main MOS transistor connected to an assistance MOS transistor and by electrically connecting a gate interconnection of the main MOS transistor with a gate interconnection of the assistance MOS transistor. CONSTITUTION: The main MOS transistor(100) includes the first gate interconnection receiving an outside signal, the first source/drain region(122) of the first conductivity and the body(108). The assistance MOS transistor(150) selectively switches the body to a floating or grounding state according to the outside signal, including the second gate interconnection, the second source/drain region(172) of the second conductivity type opposite to the first conductivity type. An interconnection layer(140) electrically connects the first gate interconnection with the second gate interconnection.
摘要翻译：目的：提供一种具有绝缘体上硅（SOI）金属氧化物半导体（MOS）晶体管的半导体器件，以使主MOS晶体管的主体接地，并减少主体断开状态下的漏电流 MOS晶体管，通过连接从连接到辅助MOS晶体管的主MOS晶体管的沟道区延伸的主体，并且通过将主MOS晶体管的栅极互连与辅助MOS晶体管的栅极互连电连接。构成：主MOS晶体管（100）包括接收外部信号的第一栅极互连，第一导电体的第一源极/漏极区域（122）和主体（108）。辅助MOS晶体管（150）根据包括第二栅极互连的外部信号，与第一导电类型相反的第二导电类型的第二源极/漏极区域（172）有选择地将主体切换到浮动或接地状态。互连层（140）将第一栅极互连与第二栅极互连电连接。

29. 发明授权

KR100302189B1 에스.오.아이(ＳＯＩ)구조를 갖는 반도체 소자 및 그 제조방법 失效
标题翻译：具有SOI结构的半导体器件及其制造方法
公开(公告)号：KR100302189B1
公开(公告)日：2001-11-02
申请号：KR1019990042801
申请日：1999-10-05
申请人： 삼성전자주식회사
发明人： 고영건 , 김병선
IPC分类号： H01L21/20
CPC分类号： H01L21/76264 , H01L21/76283 , H01L21/84 , H01L27/1203
摘要： 절연특성저하없이도다이오드나웰 레지스터간의거리를줄일수 있도록하여반도체소자의고집적화를이룰수 있도록한 SOI 구조를갖는반도체소자및 그제조방법이개시된다. 이를위하여본 발명에서는, 제 1 도전형의반도체기판상에절연층을개재하여형성된표면실리콘층과; 소자분리영역으로사용되어질부분의반도체기판이노출되도록, 표면실리콘층과절연층및 기판의일부가식각되어형성된트랜치와; 트랜치내에형성된 STI와; 상기절연층과 STI에의해둘러싸여진표면실리콘층상에형성되며, 중앙부에는게이트전극이놓여지고, 그양 에지측의표면실리콘층내부에는소오스·드레인영역이형성되어있는구조의트랜지스터와; STI를사이에두고트랜지스터의일측에배치되며, 상기반도체기판내에형성되어있는제 2 도전형의웰 표면이소정부분이노출되도록표면실리콘층과절연층의식각에의해형성된제 1 요홈부와; STI를사이에두고제 1 요홈부의일측에배치되며, 반도체기판표면이소정부분노출되도록표면실리콘층과절연층의식각에의해형성된제 2 요홈부와; 제 1 요홈부저면의제 2 도전형웰 내에형성된제 1 도전형의제 1 다이오드확산영역; 및제 2 요홈부저면의반도체기판내에형성된제 2 도전형의제 2 다이오드확산영역으로이루어진반도체소자가제공된다.

30. 发明公开

KR1020010053707A 에스·오·아이(ＳＯＩ) 웨이퍼 제조방법 失效
标题翻译： SOI WAFER制造方法
公开(公告)号：KR1020010053707A
公开(公告)日：2001-07-02
申请号：KR1019990054181
申请日：1999-12-01
申请人： 삼성전자주식회사
发明人： 곽성호 , 김병선
IPC分类号： H01L21/20
摘要： PURPOSE: A method for manufacturing an SOI(Silicon On Insulator) wafer is provided to reduce a junction capacitance by forming a BOX(Buried OXide) layer for separating unit devices from a silicon substrate. CONSTITUTION: The first silicon layer(14) is prepared. A Si1-x Gex is formed on the first silicon layer(14). A hydrogen is implanted into the Si1-x Gex in order to form a hydrogen implanting region. The second silicon layer(10) is prepared. A BOX layer(12) is formed on the second silicon layer. The first and the second layers(14,10) are aligned to face the Si1-x Gex and the BOX layer(12) to each other. The first and the second layers(14,10) are bonded to each other. A part of the first silicon layer(14) without the hydrogen is removed therefrom.
摘要翻译：目的：提供一种用于制造SOI（绝缘体上硅）晶片的方法，以通过形成用于将单元器件与硅衬底分离的BOX（掩埋氧化物）层来降低结电容。构成：制备第一硅层（14）。在第一硅层（14）上形成Si1-xGex。为了形成氢注入区，将氢注入到Si1-xGex中。制备第二硅层（10）。 BOX层（12）形成在第二硅层上。将第一层和第二层（14）对准以使Si1-xGex和BOX层（12）彼此面对。第一层和第二层（14）彼此结合。从其中除去没有氢的第一硅层（14）的一部分。

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