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1. 发明公开

KR1020020026991A 선택적 절연막을 이용한 반도체 소자의 정션 커패시턴스개선방법 无效
标题翻译：使用选择性绝缘层改善半导体器件的结电容的方法
公开(公告)号：KR1020020026991A
公开(公告)日：2002-04-13
申请号：KR1020000058115
申请日：2000-10-04
申请人： 삼성전자주식회사
发明人： 곽성호
IPC分类号： H01L29/78
摘要： PURPOSE: A method for improving junction capacitance of a semiconductor device using a selective insulation layer is provided to embody a shallow source/drain and to prevent a latch-up phenomenon by forming an oxide layer while using the selective insulation layer instead of a buried oxide layer, and to prevent off-current from increasing by controlling a kink effect in a voltage characteristic of the semiconductor device. CONSTITUTION: A mask is formed in a region for the source/drain of the first semiconductor substrate(100). The surface of the first semiconductor substrate is oxidized to form the selective insulation layer(104) by using the mask. The mask is eliminated. A process for easily sawing the surface of the second semiconductor substrate is performed. The first and second semiconductor substrates are bonded together while the first semiconductor substrate faces downward and the second semiconductor substrate faces upward. The surface of the second semiconductor substrate wherein the process for easily sawing the second semiconductor substrate is performed faces upward. The surface is polished. A gate pattern and a source/drain region(116,118) are formed on the second semiconductor substrate.
摘要翻译：目的：提供一种用于改善使用选择性绝缘层的半导体器件的结电容的方法来体现浅源极/漏极，并且通过在使用选择性绝缘层而不是埋入氧化物的同时形成氧化物层来防止闩锁现象并且通过控制半导体器件的电压特性中的扭结效应来防止截止电流的增加。构成：在用于第一半导体衬底（100）的源极/漏极的区域中形成掩模。通过使用掩模，将第一半导体衬底的表面氧化形成选择性绝缘层（104）。面具被淘汰。执行用于容易地锯切第二半导体衬底的表面的工艺。第一半导体衬底和第二半导体衬底在第一半导体衬底面向下并且第二半导体衬底朝上的同时结合在一起。其中执行用于容易地锯切第二半导体衬底的工艺的第二半导体衬底的表面面向上。表面抛光。栅极图案和源极/漏极区域（116,118）形成在第二半导体衬底上。

2. 发明公开

KR1020010017502A 반도체 소자 제조방법 无效
标题翻译：制造半导体器件的方法
公开(公告)号：KR1020010017502A
公开(公告)日：2001-03-05
申请号：KR1019990033052
申请日：1999-08-12
申请人： 삼성전자주식회사
发明人： 곽성호
IPC分类号： H01L21/76
摘要： PURPOSE: A method for manufacturing a semiconductor device is provided to make an upper edge portion of a trench round without an additional complicated process, by performing an isolating process to form the trench after an oxide accelerating material is ion-implanted into a field region. CONSTITUTION: A pad oxide layer and a nitride layer are sequentially formed on a semiconductor substrate(100). The nitride layer and the pad oxide layer are selectively etched to expose the substrate of a portion to be used as a field region. An oxide accelerating material is ion-implanted into the resultant structure to form an impurity doping region(108) on the surface of the field region in the substrate while using the nitride layer as a mask. The exposed surface of the substrate is partially etched to form a trench by using the nitride as a mask. The nitride layer and the pad oxide layer are eliminated. A shallow trench isolation(STI)(110) is formed in the trench. A gate electrode(114) is formed in a predetermined portion of the substrate by intervening a gate insulating layer(112) so that a predetermined portion of the gate electrode overlaps the STI.
摘要翻译：目的：提供一种制造半导体器件的方法，以便通过在将氧化物加速材料离子注入到场区域中之后执行隔离工艺以形成沟槽，从而使沟槽的上边缘部分无需额外的复杂工艺。构成：在半导体衬底（100）上依次形成焊盘氧化物层和氮化物层。选择性地蚀刻氮化物层和衬垫氧化物层以暴露用作场区域的部分的衬底。将氧化物加速材料离子注入到所得结构中，以在使用氮化物层作为掩模的同时在衬底中的场区的表面上形成杂质掺杂区（108）。通过使用氮化物作为掩模，部分地蚀刻衬底的暴露表面以形成沟槽。消除氮化物层和衬垫氧化物层。在沟槽中形成浅沟槽隔离（STI）（110）。通过插入栅极绝缘层（112），使栅电极的预定部分与STI重叠，在栅极电极（114）形成在基板的预定部分中。

3. 发明授权

KR100558543B1 에스·오·아이(ＳＯＩ) 웨이퍼 제조방법 失效
标题翻译：制造SOI晶片的方法
公开(公告)号：KR100558543B1
公开(公告)日：2006-03-10
申请号：KR1019990054181
申请日：1999-12-01
申请人： 삼성전자주식회사
发明人： 곽성호 , 김병선
IPC分类号： H01L21/20
摘要： SOI 웨이퍼의 구조를 변경하여, 상기 웨이퍼를 사용하여 SOI 소자를 제조할 때 야기되던 플로우팅 바디 효과(floating body effect)를 감소시킬 수 있도록 한 SOI 웨이퍼 제조방법이 개시된다.
이를 구현하기 위하여 본 발명에서는, 제 1 실리콘층을 준비한 후, 상기 실리콘층 상에 Si
1-X Ge
x 를 형성하는 단계와; 상기 Si
1-X Ge
x 상으로 하이드로겐을 이온주입하여, 상기 제 1 실리콘층 내에 소정 깊이의 하이드로겐 주입 영역을 형성하는 단계와; 제 2 실리콘층을 준비한 후, 상기 실리콘층 상에 BOX층을 형성하는 단계와; 상기 Si
1-X Ge
x (X는 Si과 Ge의 조성비를 나타낸 것으로, 0.5 ~ 1의 값을 갖는다)와 상기 BOX층이 마주보도록 상기 제 1 실리콘층과 상기 제 2 실리콘층을 위치 정렬한 후 이들 두 실리콘 기판을 접합하는 단계; 및 상기 제 1 실리콘층중, 하이드로겐이 주입되지 않은 부분을 절단하는 단계로 이루어진 SOI 웨이퍼 제조방법이 제공된다.

4. 发明公开

KR1020010053707A 에스·오·아이(ＳＯＩ) 웨이퍼 제조방법 失效
标题翻译： SOI WAFER制造方法
公开(公告)号：KR1020010053707A
公开(公告)日：2001-07-02
申请号：KR1019990054181
申请日：1999-12-01
申请人： 삼성전자주식회사
发明人： 곽성호 , 김병선
IPC分类号： H01L21/20
摘要： PURPOSE: A method for manufacturing an SOI(Silicon On Insulator) wafer is provided to reduce a junction capacitance by forming a BOX(Buried OXide) layer for separating unit devices from a silicon substrate. CONSTITUTION: The first silicon layer(14) is prepared. A Si1-x Gex is formed on the first silicon layer(14). A hydrogen is implanted into the Si1-x Gex in order to form a hydrogen implanting region. The second silicon layer(10) is prepared. A BOX layer(12) is formed on the second silicon layer. The first and the second layers(14,10) are aligned to face the Si1-x Gex and the BOX layer(12) to each other. The first and the second layers(14,10) are bonded to each other. A part of the first silicon layer(14) without the hydrogen is removed therefrom.
摘要翻译：目的：提供一种用于制造SOI（绝缘体上硅）晶片的方法，以通过形成用于将单元器件与硅衬底分离的BOX（掩埋氧化物）层来降低结电容。构成：制备第一硅层（14）。在第一硅层（14）上形成Si1-xGex。为了形成氢注入区，将氢注入到Si1-xGex中。制备第二硅层（10）。 BOX层（12）形成在第二硅层上。将第一层和第二层（14）对准以使Si1-xGex和BOX层（12）彼此面对。第一层和第二层（14）彼此结合。从其中除去没有氢的第一硅层（14）的一部分。

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