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11. 发明公开

KR1020130049418A 반도체 시스템을 위한 무선 신호 송수신 장치 无效
标题翻译：无线信号传输/接收装置的半导体系统
公开(公告)号：KR1020130049418A
公开(公告)日：2013-05-14
申请号：KR1020110114427
申请日：2011-11-04
申请人： 에스케이하이닉스 주식회사
发明人： 김양희 , 오익수 , 이준호 , 김현석 , 정부호 , 조선기
IPC分类号： G11C7/10 , G11C29/00 , H04B5/00
CPC分类号： H04L25/4906
摘要： PURPOSE: A wireless signal transceiver for a semiconductor system is provided to stably transmit and receive a signal by securing sufficient inductance in a limited area. CONSTITUTION: A transmission control unit(101) transmits a plurality of input signals received through a signal transmission line. A SERDES circuit(105) generates a serial signal from the plurality of input signals and provides the serial signal to an input and output buffer. The SERDES circuit generates a plurality of parallel signals by dividing the serial signal from the input and output buffer. An input and output buffer(107) provides a division signal obtained by dividing the serial signal to a driver and provides a signal from the driver to the SERDES circuit. A coupling pad generates inductance according to the division signal and provides a signal generated by induction coupling with an external device to the driver. A reception control unit receives the plurality of serial signals from the SERDES circuit and transmits the plurality of serial signals to the signal transmission line. [Reference numerals] (101) Transmission control unit; (103) Path control unit; (107) Input and output buffer; (109) Driver; (113) Reception control unit; (A1,A2,A3) Transmission processing unit; (B1,B2,B3) Coupler; (C1,C2,C3) Reception processing unit
摘要翻译：目的：提供用于半导体系统的无线信号收发器，以通过在有限的区域中确保足够的电感来稳定地发送和接收信号。构成：传输控制单元（101）发送通过信号传输线接收的多个输入信号。 SERDES电路（105）从多个输入信号产生串行信号，并将串行信号提供给输入和输出缓冲器。 SERDES电路通过从输入和输出缓冲器中分离串行信号来产生多个并行信号。输入和输出缓冲器（107）提供通过将串行信号分配给驱动器而获得的分频信号，并将来自驱动器的信号提供给SERDES电路。耦合垫根据分频信号产生电感，并将通过与外部装置的感应耦合产生的信号提供给驱动器。接收控制单元从SERDES电路接收多个串行信号，并将多个串行信号发送到信号传输线。（附图标记）（101）变速器控制单元; （103）路径控制单元; （107）输入输出缓冲器; （109）司机; （113）接收控制单元; （A1，A2，A3）传输处理单元; （B1，B2，B3）耦合器; （C1，C2，C3）接收处理单元

12. 发明公开

KR1020130041619A 내부 전압 생성 회로 및 내부 전압 생성 방법 无效
标题翻译：内部电压发生电路及其方法
公开(公告)号：KR1020130041619A
公开(公告)日：2013-04-25
申请号：KR1020110105996
申请日：2011-10-17
申请人： 에스케이하이닉스 주식회사
发明人： 김현석 , 오익수 , 이준호 , 정부호 , 조선기 , 김양희
IPC分类号： G11C5/14
CPC分类号： H02M3/07 , H02M3/1584
摘要： PURPOSE: An internal voltage generating circuit and an internal voltage generating method are provided to stably generate an internal voltage of a target level by controlling a voltage pump quantity according to the level of an internal voltage. CONSTITUTION: A sub-voltage generating unit(100) outputs a first sub-voltage and a second sub-voltage by distributing a target level with a preset interval. A sensing unit(200) receives an internal voltage and compares the first sub-voltage with the second sub-voltage. The sensing unit generates a first sensing signal and a second sensing signal according to the comparison result. A pumping control signal generating unit(300) generates a first pumping control signal and a second pumping control signal according to the activation states of the first sensing signal and the second sensing signal. A pump unit(400) generates the internal voltage by receiving the first pumping control signal and the second pumping control signal. [Reference numerals] (100) Sub-voltage generating unit; (200) Sensing unit; (300) Pumping control signal generating unit; (400) Pump unit;
摘要翻译：目的：提供内部电压产生电路和内部电压产生方法，以通过根据内部电压的电平控制电压泵量来稳定地产生目标电平的内部电压。构成：子电压产生单元（100）通过以预设间隔分配目标电平来输出第一子电压和第二子电压。感测单元（200）接收内部电压并将第一子电压与第二子电压进行比较。感测单元根据比较结果产生第一感测信号和第二感测信号。泵送控制信号产生单元（300）根据第一感测信号和第二感测信号的激活状态产生第一泵送控制信号和第二泵送控制信号。泵单元（400）通过接收第一泵送控制信号和第二泵送控制信号来产生内部电压。（附图标记）（100）子电压产生单元; （200）感应单元; （300）泵送控制信号发生单元; （400）泵单元;

13. 发明公开

KR1020120109208A 크로스토크를 방지할 수 있는 반도체 집적 회로 장치 无效
标题翻译：用于防止信号线之间的晶体管的半导体集成电路设备
公开(公告)号：KR1020120109208A
公开(公告)日：2012-10-08
申请号：KR1020110027581
申请日：2011-03-28
申请人： 에스케이하이닉스 주식회사
发明人： 이준호 , 김현석 , 정부호 , 조선기 , 김양희 , 김영원
IPC分类号： H01L23/58
CPC分类号： H01L23/552 , H01L23/481 , H01L23/5222 , H01L24/16 , H01L25/0657 , H01L2224/16146 , H01L2225/06513 , H01L2225/06541 , H01L2924/00013 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599
摘要： PURPOSE: A semiconductor integrated circuit device for preventing crosstalk is provided to reduce noise coupling in a semiconductor substrate by installing a TSV contacted to a shielding line between adjacent signal lines and a lower part of the shielding line. CONSTITUTION: An inter-layer insulating film(110) is formed on a semiconductor substrate(100). A pair of signal lines(120a,120b) is formed on the inter-layer insulating film. A shielding line(125) is formed on a space between the signal lines. A TSV(Through Silicon Via)(150) is installed between the signal lines. An insulating film(160) is coated on the outer sidewall of the TSV.
摘要翻译：目的：提供一种用于防止串扰的半导体集成电路器件，用于通过安装与相邻信号线和屏蔽线下部之间的屏蔽线接触的TSV来减少半导体衬底中的噪声耦合。构成：在半导体衬底（100）上形成层间绝缘膜（110）。一层信号线（120a，120b）形成在层间绝缘膜上。屏蔽线（125）形成在信号线之间的空间上。信号线之间安装TSV（Through Silicon Via）（150）。绝缘膜（160）涂覆在TSV的外侧壁上。

14. 发明公开

KR1020120003618A 멀티 칩 패키지 无效
标题翻译：多芯片包装
公开(公告)号：KR1020120003618A
公开(公告)日：2012-01-11
申请号：KR1020100064319
申请日：2010-07-05
申请人： 에스케이하이닉스 주식회사
发明人： 김영원 , 이준호 , 김현석 , 정부호 , 조선기 , 김양희
IPC分类号： G11C5/06 , G11C7/10 , G11C7/22
CPC分类号： G11C5/063 , G11C7/1051 , G11C7/22 , G11C2207/2254
摘要： PURPOSE: A multi chip package is provided to reduce the distortion of an inputted signal by comparing input data signal with reference data. CONSTITUTION: In a multi chip package, a controller(160) compares an external data signal with a predetermined signal. The controller generates a control signal according to a comparison result. A signal transmission unit(120) compensates a distorted data signal with a normal data signal. The distorted data signal is generated due to impedance mismatching. A package unit(140) is comprised of a plurality of chips. The plural chips receives compensated data signal.
摘要翻译：目的：提供多芯片封装，通过将输入数据信号与参考数据进行比较来减少输入信号的失真。构成：在多芯片封装中，控制器（160）将外部数据信号与预定信号进行比较。控制器根据比较结果生成控制信号。信号传输单元（120）用正常数据信号补偿失真的数据信号。由于阻抗不匹配而产生失真的数据信号。包装单元（140）由多个芯片组成。多个芯片接收补偿数据信号。

15. 发明授权

KR101940110B1 반도체 장치의 출력 데이터 노이즈 제거 방법 및 이를 구현하는 반도체 장치 有权
公开(公告)号：KR101940110B1
公开(公告)日：2019-01-18
申请号：KR1020120095552
申请日：2012-08-30
申请人： 에스케이하이닉스 주식회사
发明人： 한성우 , 오익수 , 이준호 , 정부호 , 조선기 , 김양희 , 김태훈
IPC分类号： G11C7/10

16. 发明公开

KR1020140064275A 파워 패드 및 이를 포함하는 반도체 메모리 장치 审中-实审
标题翻译：电源线和半导体存储器件包括电源线
公开(公告)号：KR1020140064275A
公开(公告)日：2014-05-28
申请号：KR1020120131436
申请日：2012-11-20
申请人： 에스케이하이닉스 주식회사
发明人： 정부호 , 오익수 , 이준호 , 김현석 , 조선기 , 김양희
IPC分类号： H01L27/04 , H01L21/60
摘要： The present technique relates to a power pad capable of improving voltage drop in a core region, and a semiconductor memory device including the same. A power pad which supplies power to the inner part of an on-chip is arranged between a core region and a fuse region. Thereby, resistance is reduced by reducing the physical length of the power line which connects a power pad and the core region. In addition, the cause of the increase in resistance on the power line is removed by not allowing the power line to pass through the fuse region. Consequently, the voltage drop is improved in the core region, thereby improving the operational property of the entire semiconductor memory device.
摘要翻译：本技术涉及能够改善芯区域中的电压降的功率垫以及包括其的半导体存储器件。向芯片内部供电的功率垫配置在芯区域和保险丝区域之间。因此，通过减小连接功率垫和芯区域的电力线的物理长度来降低电阻。此外，通过不允许电力线通过熔丝区域来消除电力线上的电阻增加的原因。因此，核心区域的电压降得到改善，从而提高整个半导体存储器件的操作性能。

17. 发明公开

KR1020140028905A 차지 펌프를 포함한 적층형 반도체 메모리 장치 无效
标题翻译：具有充电泵的堆叠式半导体存储器件
公开(公告)号：KR1020140028905A
公开(公告)日：2014-03-10
申请号：KR1020120096279
申请日：2012-08-31
申请人： 에스케이하이닉스 주식회사
发明人： 조선기 , 오익수 , 이준호 , 김현석 , 정부호 , 김양희
IPC分类号： G11C5/02 , G11C5/14 , H01L23/48
CPC分类号： G11C5/02 , G11C5/063 , G11C5/145 , H02M3/07
摘要： A stacked semiconductor memory device containing a charge pump is disclosed. The stacked semiconductor memory device according to an embodiment of the present invention comprises a plurality of semiconductor memory devices staked to be able to access independently and a plurality of charge pumps provided in each of the semiconductor memory device, wherein the plurality of charge pumps are interconnected.
摘要翻译：公开了一种包含电荷泵的叠层半导体存储器件。根据本发明实施例的层叠半导体存储器件包括多个半导体存储器件，其被淀积以能够独立存取，以及设置在每个半导体存储器件中的多个电荷泵，其中多个电荷泵相互连接。

18. 发明公开

KR1020130072060A 반도체 집적회로 및 그의 구동방법 无效
标题翻译：半导体集成电路及其驱动方法
公开(公告)号：KR1020130072060A
公开(公告)日：2013-07-01
申请号：KR1020110139607
申请日：2011-12-21
申请人： 에스케이하이닉스 주식회사
发明人： 정부호 , 이준호 , 김현석 , 조선기 , 김양희 , 김영원
IPC分类号： H01L27/00 , H01L21/768
CPC分类号： H01L27/0611 , H01L23/5286 , H01L27/0207
摘要： PURPOSE: A semiconductor integrated circuit and a method for driving the same are provided to minimize the influence of inductance by electrically short-circuiting a power line for supplying the source voltage for a specific purpose and a power line for supplying the source voltage for a general purpose. CONSTITUTION: A first power voltage (VDD) is applied to a first power voltage pad (110_0-110_n). A first power line (120) is connected to the first power voltage pad. A second power voltage (VDDQ) is applied to a second power voltage pad (130_0-130_k). A second power line (140) is parallel to the first power line. A switching part (150) selectively connects the first and the second power line in response to a test mode signal (TM,TMB).
摘要翻译：目的：提供一种半导体集成电路及其驱动方法，以通过电气短路用于为特定用途提供源极电压的电力线和用于为一般的电源供应源电压的电力线来最小化电感的影响目的。构成：将第一电源电压（VDD）施加到第一电源电压垫（110_0-110_n）。第一电源线（120）连接到第一电源电压垫。第二电源电压（VDDQ）被施加到第二电源电压焊盘（130_0-130_k）。第二电力线（140）平行于第一电力线。开关部分（150）响应于测试模式信号（TM，TMB）选择性地连接第一和第二电力线。

19. 发明公开

KR1020110109125A 반도체메모리칩 및 집적회로 无效
标题翻译：半导体存储器芯片和集成电路
公开(公告)号：KR1020110109125A
公开(公告)日：2011-10-06
申请号：KR1020100028716
申请日：2010-03-30
申请人： 에스케이하이닉스 주식회사
发明人： 김현석 , 한성우 , 이준호 , 정부호 , 김양희
IPC分类号： G11C11/21 , G11C7/10 , G11C5/14
CPC分类号： G11C5/14
摘要： 반도체메모리칩은 전원전압 및 접지전압을 인가하는 구동전압수신부와, 상기 전원전압 및 상기 접지전압을 공급받아 구동되어, 제1 데이터를 제1 데이터라인으로 출력하는 제1 데이터구동부와, 상기 전원전압 및 상기 접지전압을 공급받아 구동되어, 제2 데이터를 제2 데이터라인으로 출력하는 제2 데이터구동부와, 상기 제1 및 제2 데이터라인 사이에 연결된 MOS 트랜지스터를 포함한다.

20. 发明公开

KR1020140064276A 파워 메탈 메쉬 및 이를 포함하는 반도체 메모리 장치 审中-实审
标题翻译：功率金属网和半导体存储器件包括功率金属网
公开(公告)号：KR1020140064276A
公开(公告)日：2014-05-28
申请号：KR1020120131437
申请日：2012-11-20
申请人： 에스케이하이닉스 주식회사
发明人： 이준호 , 한성우 , 오익수 , 정부호 , 조선기 , 김양희 , 김태훈
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H03H7/0115 , G11C5/14 , H01L23/147 , H01L23/49827 , H01L23/5223 , H01L23/5227 , H01L23/5286 , H01L23/552 , H01L23/66 , H01L2223/6661 , H01L2924/0002 , H01L2924/00
摘要： The present technique relates to a power metal mesh and a semiconductor memory device including the same. A band stop filter part, which has a parallel structure of a capacitor and an inductance between adjacent chips, is arranged by implementing a power metal mesh for reducing noise coupling generated between the adjacent chips on a silicon interposer. Consequently, the noise coupling of a specific frequency band generated between the adjacent chips can be effectively reduced.
摘要翻译：本技术涉及功率金属网和包括其的半导体存储器件。通过实现用于减少在硅插入件上的相邻芯片之间产生的噪声耦合的功率金属网来布置具有电容器的并联结构和相邻芯片之间的电感的带阻滤波器部分。因此，可以有效地减少相邻芯片之间产生的特定频带的噪声耦合。

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