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1. 发明专利

JPS6158321A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：JPS6158321A
公开(公告)日：1986-03-25
申请号：JP18095684
申请日：1984-08-30
申请人： Nec Corp
发明人： BESSHO MIKIO
IPC分类号： H03K19/20 , H03K19/094
CPC分类号： H03K19/09425
摘要： PURPOSE:To obtain a semiconductor integrated circuit which makes the operation of two pieces of input terminals with one piece of input terminal, by providing one piece of input terminal in which a quaternary input is inputted and two pieces of input buffers controlled by quaternary inputs. CONSTITUTION:When an output B1 is used as a signal line, an input high voltage=V1-V2 and input low voltage=V0-V1 are added to an input A1 like as timings of t1-t4. Then, by input-output characteristics of input buffers 22 and 23, an output C1 remains high in level and only the output B1 is changed in accordance with the input A1. When the output C1 is used as a signal line, on the contrary, an input high voltage=V2 and input low voltage=V1-V2 are added to the input A1 like as timings t5-t9. As a result the output B1 remains low in level and only the output C1 is changed in accordance with the input A1. Therefore, a semiconductor integrated circuit which makes the operation of two pieces of input terminals with one piece of input terminal is obtained without requiring any control signal, etc., to the input buffers 22 and 23.
摘要翻译：目的：通过提供输入四进制输入的一个输入端和由四进制输入控制的两个输入缓冲器来获得两片输入端与一个输入端的操作的半导体集成电路。构成：当输出B1用作信号线时，如t1-t4的定时，输入高电压= V1-V2和输入低电压= V0-V1被添加到输入A1。然后，通过输入缓冲器22和23的输入输出特性，输出C1保持高电平，只有输出B1根据输入A1而改变。当输出C1用作信号线时，相反地，输入高电压= V2和输入低电压= V1-V2如时刻t5-t9那样添加到输入A1。结果，输出B1保持低电平，并且仅输出C1根据输入A1而改变。因此，不需要任何控制信号等就可以获得使输入端与一条输入端子的操作的半导体集成电路等。

2. 发明专利

JPS59139725A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路设备
公开(公告)号：JPS59139725A
公开(公告)日：1984-08-10
申请号：JP1271283
申请日：1983-01-31
申请人： Hitachi Ltd
发明人： SUZUKI YUKIROU , MASUDA IKUROU , IWAMURA MASAHIRO , KATOUNO SHINJI , URAGAMI KEN , YOSHIMURA MASAYOSHI , MATSUBARA TOSHIAKI
IPC分类号： H03K19/0185 , H03K19/0175 , H03K19/018 , H03K19/08 , H03K19/094 , H03K19/0944 , H03K19/177
CPC分类号： H03K19/17744 , H03K19/017518 , H03K19/01806 , H03K19/09425 , H03K19/09448 , H03K19/1778 , H03K19/17792
摘要： PURPOSE:To reduce both the delay time of transmission and the dependency on capacity for a semiconductor IC device by providing an input buffer for TTL- CMOS level conversion and an input buffer for CMOS-TTL level conversion and using a bipolar transistor to the output of a buffer converter. CONSTITUTION:A semiconductor IC device is provided with an input buffer 20 for TTL-CMOS conversion, an output buffer 22 for CMOS-TTL conversion and an internal logical block 21 which works at the CMOS level. The input signals IN1-IN19 of TTL levels are converted into CMOS levels by level converters 201-20n of the buffer 20. These converted signals of CMOS levels are applied to each logical gate of the block 21. Then bipolar output TRs Q1 and Q2 are used to charge or discharge the output capacity CS of each of converters 201-20n of the buffer 20. This device reduces both the delay time of transmission and the dependency on capacity and increases the working speed of the semiconductor IC device.
摘要翻译：目的：通过提供用于TTL-CMOS电平转换的输入缓冲器和用于CMOS-TTL电平转换的输入缓冲器以及使用双极晶体管来输出半导体IC器件的输出，以减少传输的延迟时间和半导体IC器件的容量依赖性一个缓冲转换器。构成：半导体IC器件具有用于TTL-CMOS转换的输入缓冲器20，用于CMOS-TTL转换的输出缓冲器22和工作于CMOS电平的内部逻辑块21。 TTL电平的输入信号IN1-IN19由缓冲器20的电平转换器201-20n转换成CMOS电平。这些CMOS电平的转换信号被加到块21的每个逻辑门。然后双极性输出TR Q1和Q2是用于对缓冲器20的每个转换器201-20n的输出电容CS进行充电或放电。该装置减小了传输的延迟时间和对容量的依赖性，并且增加了半导体IC器件的工作速度。

3. 发明专利

JPS59139724A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路设备
公开(公告)号：JPS59139724A
公开(公告)日：1984-08-10
申请号：JP1271183
申请日：1983-01-31
申请人： Hitachi Ltd
发明人： SUZUKI YUKIROU , MASUDA IKUROU , IWAMURA MASAHIRO , KATOUNO SHINJI , URAGAMI KEN , YOSHIMURA MASAYOSHI , MATSUBARA TOSHIAKI
IPC分类号： H03K19/0185 , H03K19/0175 , H03K19/018 , H03K19/08 , H03K19/094 , H03K19/0944 , H03K19/0952 , H03K19/177
CPC分类号： H03K19/17744 , H03K19/017518 , H03K19/01806 , H03K19/09425 , H03K19/09448 , H03K19/1778 , H03K19/17792
摘要： PURPOSE:To reduce the dependency on the output capacity for the working speed of a buffer and to improve the degree of integration by using an internal logical block which works at the CMOS level, a buffer for TTL-CMOS level input conversion and a buffer for CMOS-TTL level output conversion. CONSTITUTION:A semiconductor integrated circuit device is provided with an input buffer 20 for TTL-CMOS level conversion, an internal logical block 21 which works at the CMOS level and an output buffer 22 for CMOS-TTL level conversion. The input signals of TTL levels supplied to terminals 1-19 are converted into CMOS levels by input level converters 201-20n of the buffer 20 and then applied to each gate of a block 21. The output signal of CMOS level delivered from the block 21 is converted into the TTL level through each of level converters 221-22m of the buffer 22 and delivered. Each transistor TR of buffers 20 and 22 is converted into a bipolar TR. This device reduces the dependency on the output capacity for the buffer working speed and improves the density of integration.
摘要翻译：目的：为了减少对缓冲器工作速度的输出容量的依赖性，并通过使用工作于CMOS电平的内部逻辑块来提高积分程度，一个用于TTL-CMOS电平输入转换的缓冲器和一个用于 CMOS-TTL电平输出转换。构成：半导体集成电路器件具有用于TTL-CMOS电平转换的输入缓冲器20，工作于CMOS电平的内部逻辑块21和用于CMOS-TTL电平转换的输出缓冲器22。提供给端子1-19的TTL电平的输入信号由缓冲器20的输入电平转换器201-20n转换成CMOS电平，然后施加到块21的每个栅极。从块21传送的CMOS电平的输出信号通过缓冲器22的每个电平转换器221-22m被转换成TTL电平并传送。缓冲器20和22的每个晶体管TR被转换成双极性TR。该设备减少了对缓冲区工作速度的输出容量的依赖性，并提高了集成密度。

4. 发明专利

JP2009302883A Ternary input circuit 审中-公开
标题翻译：三进制输入电路
公开(公告)号：JP2009302883A
公开(公告)日：2009-12-24
申请号：JP2008154833
申请日：2008-06-13
申请人： Sanyo Electric Co Ltd , Sanyo Semiconductor Co Ltd , 三洋半導体株式会社 , 三洋電機株式会社
发明人： ITO HIDEO
IPC分类号： H03K19/20 , H03K19/0175
CPC分类号： H03K19/09425 , H03K19/0002
摘要： PROBLEM TO BE SOLVED: To provide a ternary input circuit for outputting a digital signal indicating three states of an input.
SOLUTION: This ternary input circuit includes: a pull-up switch element 20 for controlling a connection and a nonconnection between an input terminal IN and a first power supply VDD; and a pull-down switch element 22 for controlling the connection and the nonconnection between the input terminal IN and a second power supply VSS. The pull-up switch element 20 and the pull-down switch element 22 are exclusively turned ON/OFF in time sharing, and the input terminal states at the respective operating states are held and output from two output terminals.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供用于输出指示输入的三种状态的数字信号的三进制输入电路。解决方案：该三元输入电路包括：上拉开关元件20，用于控制输入端子IN和第一电源VDD之间的连接和非连接; 以及用于控制输入端子IN和第二电源VSS之间的连接和非连接的下拉开关元件22。上拉开关元件20和下拉开关元件22在时间分配中被单独导通/截止，并且在各个操作状态下的输入端状态被保持并从两个输出端输出。版权所有（C）2010，JPO＆INPIT

5. 发明专利

JPS59139726A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路设备
公开(公告)号：JPS59139726A
公开(公告)日：1984-08-10
申请号：JP1271383
申请日：1983-01-31
申请人： Hitachi Ltd
发明人： SUZUKI YUKIROU , MASUDA IKUROU , IWAMURA MASAHIRO , KATOUNO SHINJI , URAGAMI KEN , YOSHIMURA MASAYOSHI , MATSUBARA TOSHIAKI
IPC分类号： H03K19/0185 , H03K19/0175 , H03K19/018 , H03K19/08 , H03K19/094 , H03K19/0944 , H03K19/177
CPC分类号： H03K19/17744 , H03K19/017518 , H03K19/01806 , H03K19/09425 , H03K19/09448 , H03K19/1778 , H03K19/17792
摘要： PURPOSE:To increase the working speed and to improve the density of integration by providing an input buffer for TTL-CMOS level conversion and an output buffer for CMOS-TTL level conversion and using an output bipolar transistor to the converter of each buffer. CONSTITUTION:A semiconductor IC device is provided with an input buffer 20 for TTL-CMOS level conversion, an output buffer 22 for CMOS-TTL level conversion and an internal logical block 21 which works at the CMOS level. The TTL output signal is applied to output level converters 221-22m of the buffer 22 respectively through each logical gate of the block 21. Then the CMOS level is converted into the TTL level and delivered. The output bipolar transistors TRQ10-14 are used to charge or discharge the output load capacity CX of each of converters 221-22m. This device reduces both the dependency on capacity as well as the delay time of transmission and improves the density of integration of a semiconductor IC device.
摘要翻译：目的：通过提供TTL-CMOS电平转换的输入缓冲器和用于CMOS-TTL电平转换的输出缓冲器，并将输出双极晶体管用于每个缓冲器的转换器，提高工作速度并提高集成密度。构成：半导体IC器件具有用于TTL-CMOS电平转换的输入缓冲器20，用于CMOS-TTL电平转换的输出缓冲器22和在CMOS电平工作的内部逻辑块21。 TTL输出信号分别通过块21的每个逻辑门施加到缓冲器22的输出电平转换器221-22m。然后将CMOS电平转换为TTL电平并传送。输出双极晶体管TRQ10-14用于对转换器221-22m的输出负载能力CX进行充电或放电。该器件减少了对容量的依赖性以及传输的延迟时间，并且提高了半导体IC器件的集成密度。

6. 发明专利

JPS58215135A Ternary input circuit 失效
标题翻译：三进制输入电路
公开(公告)号：JPS58215135A
公开(公告)日：1983-12-14
申请号：JP9802282
申请日：1982-06-08
申请人： Toshiba Corp
发明人： KAWASAKI MASAYUKI
IPC分类号： H03K19/20 , H03K19/094
CPC分类号： H03K19/09425
摘要： PURPOSE:To attain low cost, by constituting an inverter having a high circuit threshold voltage with the same channel type MOS transistors(TRs) for extending a manufacturing margin (range) of the threshold voltage of the MOS TRs, and reducing the pattern area of an integrated circuit. CONSTITUTION:The inverter 13 having a high circuit threshold voltage comprising P channel MOS TRs 11, 12 and the inverter 16 having a low circuit threshold voltage comprising N channel MOS TRs 14, 15 are used. That is, in the inverter 13 the P channel TRs 11, 12 are connected in series between a power supply VDD (1st potential supply terminal) and ground (2nd potential supply terminal), a gate of the TR11 is connected to a common input terminal 9, and a gate of the TR12 is grounded. In the inverter 16, N channel TRs 14, 15 are connected in series be tween the power supply VDD and ground, a gate of the TR15 is connected to the input terminal 9 and a gate of the TR14 is connected to the power supply VDD. Thus, the change in the circuit threshold voltage due to the dispersion in the threshold voltage VTH of the MOS TRs is prevented by constituting the inverters 13, 16 with the MOS TRs of the same channel type in this way.
摘要翻译：目的：为了实现低成本，通过构成具有用于延长MOS TR的阈值电压的制造裕度（范围）的相同沟道型MOS晶体管（TR）的具有高电路阈值电压的逆变器，并且减小集成电路。构成：使用包括P沟道MOS TR11,12的高电压阈值电压的逆变器13和具有包含N沟道MOS TR 14,15的低电路阈值电压的反相器16。也就是说，在反相器13中，P沟道TR 11,11串联连接在电源VDD（第一电位供给端子）和地（第二电位端子）之间，TR11的栅极连接到公共输入端子 9，并且TR12的门接地。在逆变器16中，N沟道TRs 14,15串联连接在电源VDD和地之间，TR15的栅极连接到输入端9，并且TR14的栅极连接到电源VDD。因此，通过以这种方式构成具有相同通道类型的MOS TR的反相器13,16来防止由于MOS TR的阈值电压VTH的偏差导致的电路阈值电压的变化。

7. 发明专利

JP3487510B2 Semiconductor device 失效
公开(公告)号：JP3487510B2
公开(公告)日：2004-01-19
申请号：JP51945995
申请日：1994-01-20
申请人：アイ・アンド・エフ株式会社 , ユーシーティー株式会社 , 忠弘大見 , 直柴田
发明人：リタアウ , 忠弘大見 , 直柴田
IPC分类号： H03K19/20 , H03K17/04 , H03K17/0416 , H03K17/06 , H03K19/0175 , H03K19/094 , H03K19/0944 , H03M1/36
CPC分类号： H03K17/063 , H03K17/04163 , H03K19/09425 , H03M1/361

8. 发明专利

JPS5975721A Signal input circuit and its controlling method 失效
标题翻译：信号输入电路及其控制方法
公开(公告)号：JPS5975721A
公开(公告)日：1984-04-28
申请号：JP18727882
申请日：1982-10-25
申请人： Toshiba Corp
发明人： OOTANI TAKAYUKI , IIZUKA TETSUYA
IPC分类号： H03K19/20 , G11C8/00 , H03K19/00 , H03K19/094
CPC分类号： H03K19/09425 , H03K19/09429
摘要： PURPOSE: To obtain a circuit which has less power consumption and a short access time and its controlling method by breaking a current path when an enable control signal is in a disabled state, and holding the output state of an input gate circuit right before a change to the disabled state.
CONSTITUTION: When the control signal is in an enabled state, P1 and P3 of an input gate circuit 1 turn on and N2 turns off; a gate 11 serves as an inverter for an input signal (i). Further, a gate 12 inverts and output a node 13. In a holding circuit 2, on the other hand, the output impedance of a gate 22 is increased and the output of the circuit 1 is supplied to an internal circuit 4. When the control signal enters the disabled state, a gate 21 serves as an inverter for the output of the circuit 11. The gate 22 inverts the output of the gate 21 and returns it to a node 14. On the other hand, the output impedance of the gate 12 of the circuit 1 increases and the circuit 2 holds the output of the circuit 1 right before the control signal changes to the disabled state. Therefore, the level of the node 14 is constant and held at the level of the input signal, so the power consumption is small and the access time is shortened.
COPYRIGHT: (C)1984,JPO&Japio
摘要翻译：目的：通过在使能控制信号处于禁止状态时，通过断开电流路径来获得功耗更少，访问时间短的电路，并保持输入门电路的输出状态正好在更改之前到残疾人士。构成：当控制信号处于使能状态时，输入门电路1的P1和P3导通，N2关断; 门11用作输入信号（i）的反相器。此外，门12反相并输出节点13.在保持电路2中，另一方面，门22的输出阻抗增加，电路1的输出被提供给内部电路4.当控制信号进入禁用状态，门21用作电路11的输出的反相器。门22将门21的输出反相并将其返回到节点14.另一方面，门的输出阻抗电路1的12增加，电路2在控制信号变为禁止状态之前保持电路1的输出。因此，节点14的电平恒定并保持在输入信号的电平，因此功耗小，存取时间缩短。

9. 发明专利

JPS5757032A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：JPS5757032A
公开(公告)日：1982-04-06
申请号：JP12135281
申请日：1981-08-04
申请人： Toshiba Corp
发明人： IWAHASHI HIROSHI , ASANO MASAMICHI
IPC分类号： H01L27/092 , G11C8/00 , G11C11/417 , H01L21/8238 , H01L29/78 , H03K5/00 , H03K17/00 , H03K17/296 , H03K17/94 , H03K17/945 , H03K19/0175 , H03K19/094 , H03K19/0944
CPC分类号： H03K19/09425
摘要： PURPOSE:To reduce the number of input terminals, to which a control signal is inputted, to improve the integration degree, by using one input terminal in common. CONSTITUTION:A select circuit 13 consists of a program circuit 17 and a control circuit 18, and the signal from a chip select terminal 19 is supplied to the select circuit 13. In the circuit 17, the terminal 19 is used for a signal for setting a program, and a program set voltage higher than the voltage of the chip selecting signal is given to the terminal 19 and other terminals 19a and 19b. Consequently, FETs 201 and 202 are set not to operate in the input level of the normal chip selecting signal. The chip selecting signal inputted to the terminal 19 is applied to an inverter 31. Detection levels for the logical level of the input signal in inverters 20 and 31 to which the signal supplied to the terminal 19 is inputted are made different from each other, thus using one terminal in common.
摘要翻译：目的：为了减少输入控制信号的输入端子的数量，通过共同使用一个输入端子来提高积分度。构成：选择电路13由编程电路17和控制电路18构成，来自芯片选择端子19的信号被提供给选择电路13.在电路17中，端子19用于设定信号一个程序和一个高于芯片选择信号的电压的程序设置电压被提供给终端19和其他终端19a和19b。因此，FET 201和202被设置为不在正常芯片选择信号的输入电平中工作。输入到端子19的芯片选择信号被施加到逆变器31.使输入到端子19的信号的反相器20和31中的输入信号的逻辑电平的检测电平彼此不同，因此使用一个共同的终端。

10. 发明专利

JPS5753150A 3-state drive circuit 失效
标题翻译： 3状态驱动电路
公开(公告)号：JPS5753150A
公开(公告)日：1982-03-30
申请号：JP12001881
申请日：1981-07-29
申请人： Rockwell International Corp
发明人： GEIRII RII HAIMUBIGUNAA
IPC分类号： H03K19/0175 , H03K5/02 , H03K19/00 , H03K19/094
CPC分类号： H03K5/023 , H03K19/0016 , H03K19/09425 , H03K19/09429

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