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1. 发明专利

JPS6235643A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS6235643A
公开(公告)日：1987-02-16
申请号：JP17416185
申请日：1985-08-09
申请人： HITACHI LTD
发明人： NISHIO YOJI , KUBOKI SHIGEO , MASUDA IKURO , MATSUBARA TOSHIAKI
IPC分类号： H01L21/3205 , H01L21/82 , H01L23/52 , H01L27/118
摘要： PURPOSE:To realize a high-efficiency gate array LSI by a method wherein the innermost chip peripheral power source line is a potential source line formed of a first-layer metal that is for the supply of power to the inner circuit and an outer peripheral power source line is a potential source line formed of a second-layer metal that is for the supply of power to the inner circuit. CONSTITUTION:A Vcc power source line 311 of a basic cell lineup 310 is formed of a first-layer metal (Al 1) and connected to a Vcc power source line 100 formed of Al 1 in the periphery. A GNDA power source line 312 is connected, with the intermediary of Al 2, to a GNDA power source line 201 in the periphery formed of a second layer metal Al 2. A Vcc power source central reinforcement line 400 is formed of Al 2 and connected to an Acc power source line 100 in the periphery formed of Al 1. A GNDA power source central reinforcement line 401 is formed of Al 2 and is connected as is to a GNDA power source line 201 in the periphery formed of Al 2. With power supply being accomplished to the basic cells and to power source middle reinforcement lines by using straight lines, the region may be reduced wherein computer-aided automatic wiring is forbidden. This method realizes a high-efficiency gate array LSI.

2. 发明专利

JPS61218143A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS61218143A
公开(公告)日：1986-09-27
申请号：JP5836685
申请日：1985-03-25
申请人： HITACHI LTD
发明人： SUZUKI YASUNAGA , MATSUBARA TOSHIAKI , URAGAMI KEN
IPC分类号： H01L27/06 , H01L21/82 , H01L21/8249 , H01L27/02 , H01L27/118 , H03K19/003 , H03K19/177
摘要： PURPOSE:To sufficiently enhance the damage resistant strength of an input buffer by composing an input protecting circuit of the buffer with circuit elements for forming an output buffer in a gate array or the like. CONSTITUTION:An I/O buffer 2 of a semiconductor integrated circuit device formed with a gate array is disposed between an internal circuit 200 and an external connection terminal pad 3. In the buffer 2, a region 2a for an input buffer 111 and a region 2b for an output buffer 121 are formed as a pair. An input protecting circuit 4 is formed at the input side of the buffer 111. Thus it can be effectively protected from any of positive and negative polarity abnor mally high voltages. Circuit elements having large drive capacity are used at the output stage of the buffer 121. In other words, a reliable input protecting circuit is composed with a bipolar transistor as the element of the output stage.

3. 发明专利

JPS59144168A Bipolar mos semiconductor device and manufacture thereof 失效
标题翻译：双极MOS半导体器件及其制造
公开(公告)号：JPS59144168A
公开(公告)日：1984-08-18
申请号：JP1734083
申请日：1983-02-07
申请人： Hitachi Ltd
发明人： ANZAI NORIO , MURAMATSU AKIRA , YASUOKA HIDEKI , MATSUBARA TOSHIAKI , IKEDA TAKAHIDE
IPC分类号： H01L27/08 , H01L21/8249 , H01L27/06
CPC分类号： H01L27/0623
摘要： PURPOSE:To reduce a p-n junction area and to simultaneously improve the withstand voltage yield by forming a p-channel MOSFET in an n type insular region surrounded by a p type isolating region or p type well. CONSTITUTION:A p type isolation layer 3a to a p type substrate 1 is formed to surround an n type Si region formed with p-channel MOSFET, and a p-channel MOS region is formed in n type island. In this manner, a p-n junction which has a relation to the withstand voltage of the p-n junction to the entire MOS region can be reduced to the p-channel MOS region.
摘要翻译：目的：通过在由p型隔离区域或p型阱围绕的n型岛状区域中形成p沟道MOSFET来降低p-n结面积并同时提高耐压产量。构成：形成p型衬底1的p型隔离层3a以围绕由p沟道MOSFET形成的n型Si区，并且在n型岛中形成p沟道MOS区。以这种方式，可以将与p-n结的耐电压相关的p-n结减小到p沟道MOS区。

4. 发明专利

JPS57103344A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS57103344A
公开(公告)日：1982-06-26
申请号：JP17884880
申请日：1980-12-19
申请人： HITACHI LTD , HITACHI IRUMA DENSHI KK
发明人： IGA KAZUYOSHI , MATSUBARA TOSHIAKI
IPC分类号： H01L21/822 , H01L27/04 , H01L27/20
摘要： PURPOSE:To reduce the variation in the characteristics of an active element in an IC forming the element on a pellet by disposing the active element such as a transistor at the periphery of the pellet, thereby reducing the influence of thermal strain and external force strain. CONSTITUTION:In an IC formed, for example, of a plurality of bipolar transistors (TR)Q1-Q8 and resistors R1-R3, each TR is approached to the inside of a pad P formed at the periphery of a pellet 10. The disposing range of the element is such that an active element is contained at the position of 70-80% of a pellet size from the periphery and passive elements such as resistors, capacitors are disposed within the active element. Thus, the variation in the characteristics of the element due to the strain of the pellet can be reduced at the pellet bonding time and molding time, thereby increasing the accuracy and stability of the IC. For example, the variation rate of an N-P-N transistor is less than 1/3.

5. 发明专利

JPS57103336A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS57103336A
公开(公告)日：1982-06-26
申请号：JP17884980
申请日：1980-12-19
申请人： HITACHI LTD , HITACHI IRUMA DENSHI KK
发明人： UTSUKI ATSUSHI , MATSUBARA TOSHIAKI
IPC分类号： H01L21/52 , H01L23/29 , H01L23/31
摘要： PURPOSE:To obtain a resin molded semiconductor device having small temperature drift by absorbing the resin stress change to a chip coating material by covering a mounted pellet with the chip coating material when the pellet is mounted at the pellet mounting unit of a lead frame with silver paste. CONSTITUTION:A paste 16 of semiconductor chip is mounted via silver paste on a tab 12 of the pellet mounting unit of a lead frame 10, and the electrode of the pellet 16 is electrically connected to the inner lead of the frame 10 via a wire 18. Thereafter, they are molded with molding resin 22, and a dome-shaped chip coating material 20 is covered on the periphery of the pellet 16 at this time. Thus, the stress from the resin 22 can be absorbed by the coating material 20, the stress is not applied directly to the pellet 16, and the temperature hysteresis phenomenon such as offset voltage can be remarkably reduced.

6. 发明专利

JPS5396687A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS5396687A
公开(公告)日：1978-08-24
申请号：JP1067777
申请日：1977-02-04
申请人： HITACHI LTD
发明人： MATSUBARA TOSHIAKI
IPC分类号： H01L27/04 , H01L21/331 , H01L21/822 , H01L29/08 , H01L29/73
摘要： PURPOSE:A N -type emitter layer divided into a plural number, is caused to float against the N-type epitaxial layer which is a collector, so that the resistance element with high dielectric and high resistivity can be manufactured from a small element area.

7. 发明专利

JPH02216850A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH02216850A
公开(公告)日：1990-08-29
申请号：JP1601190
申请日：1990-01-29
申请人： HITACHI LTD
发明人： SUZUKI YUKIRO , MASUDA IKURO , IWAMURA MASAHIRO , KATONO SHINJI , URAGAMI KEN , YOSHIMURA MASAYOSHI , MATSUBARA TOSHIAKI
IPC分类号： H01L21/822 , H01L21/82 , H01L27/04 , H01L27/118 , H03K19/0175
摘要： PURPOSE:To lessen the output capacity dependency of the operation speed of an input and/or an output buffer so as to improve integration density and operation speed by forming an output transistor to implement the charge or discharge of the output capacity of a level converter out of a bipolar transistor. CONSTITUTION:In a semiconductor integrated circuit device IC for logic, an input buffer 20 has plural TTL-CMOS lever convertors 201, 202,...20n, and each output is connected with an interval logic block 21 inside the circuit device IC by an aluminum wiring layer. Moreover, the internal logic block 21 includes CMOS.NAND gates 211-214, etc. And the CMOS.NAND gate 211 can be constituted of a quasi-CMOS circuit which further includes, for example, NPN transistors Q1 and Q2, and resistances R1 and R2 and in this quasi-CMOS circuit the output stage is constituted of the bipolar transistors Q1 and Q2, so the output driving capacity is improved, and output load capacity dependency during transmission delay time can be lessened.

8. 发明专利

JPH02101758A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH02101758A
公开(公告)日：1990-04-13
申请号：JP25377988
申请日：1988-10-11
申请人： HITACHI LTD
发明人： HONMA KAZUKI , MATSUBARA TOSHIAKI
IPC分类号： H01L21/301 , H01L21/78
摘要： PURPOSE:To shorten a producing time while improving throughput and reducing manufacturing cost by providing scribe lines having several different widths while providing semiconductor integrated circuit bodies in respective regions demarkated by the scribe lines having the minimum width and providing bonding pads within the regions. CONSTITUTION:Semiconductor integrated circuits of semiconductor chips C1, C2 are provided in rectangular regions demarkated by narrower scribe lines l1. Bonding pads of the semiconductor chip C1 are formed on the periphery of the regions demarkated by the scribe lines l1 while bonding pads of the semiconductor chip C2 are provided on the periphery of regions demarkated by scribe lines l2. The corresponding pads of the chips C1 and C2 are interconnected by wires. A semiconductor wafer having such arrangement can be obtained easily by using a set of photo masks consisting of several different photo masks. Such wafer is cut off into the semiconductor chips C1, C2 in a dicing process.

9. 发明专利

JPS61171150A SEMICONDUCTOR IC DEVICE 失效
公开(公告)号：JPS61171150A
公开(公告)日：1986-08-01
申请号：JP1083285
申请日：1985-01-25
申请人： HITACHI LTD
发明人： SUZUKI YASUNAGA , MATSUBARA TOSHIAKI , MAAKEDA HARUYOSHI
IPC分类号： H01L21/82 , H01L21/8249 , H01L27/06 , H01L27/118
摘要： PURPOSE:To enable the attainment of the increase in scale of gate arrays by a method wherein the circuit of quasi CMOS type Bi-CMOS gate arrays can be constructed by writing power source (VCC) lines and ground (GND) lines above and below basic cell arrays. CONSTITUTION:Bi-polar elements are arranged outside both MOSFETs; accordingly, a VCC line 13 and a GND line 14 are wired in parallel with the basic cell array above and below basic cells 10. That is, two NPN transistors Q1, Q2 of totem pole connection at the output stage in the basic cell 10 are arranged on both sides of MOSFETs. This construction is followed by the running of the VCC line 13 and the GND line 14 above and below cells. Accordingly, similarly the first layer Al wiring can be freely laid at the center of the basic cell 10, e.g. the region sandwiched between the lines 13 and 14. This means no restriction of the degree or wiring freedom in the presence of the lines 13 and 14.

10. 发明专利

JPS6139549A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路设备
公开(公告)号：JPS6139549A
公开(公告)日：1986-02-25
申请号：JP16001684
申请日：1984-07-30
申请人： Hitachi Ltd
发明人： NISHIO YOJI , MASUDA IKURO , IWAMURA MASAHIRO , MATSUBARA TOSHIAKI
IPC分类号： H01L27/092 , H01L21/82 , H01L21/8238 , H01L27/118
CPC分类号： H01L27/11807
摘要： PURPOSE:To accelerate the current by means of eliminating any unfavorable effect of poly Si gate electrode by a method wherein a PMOS side input terminal and an NMOS side input terminal of a CMOS transistor are connected to each other by an Al wiring on the second layer out of two layer wiring. CONSTITUTION:A CMOS inverter composed of a PMOS1 and an NMOS2 is provided with a common poly Si electrode 3. Input terminals 17, 18 are connected to the Si gate electrode 3 through the intermediary of contacts 15, 16. The input terminal 17 on the PMOS1 side and the other input terminal 18 on the NMOS2 side are connected to each other using an Al wiring 42 on the second layer through the intermediary of throughholes 40, 41. Through these procedures, the current may be accelerated because the operational speed may not be unbalanced by the positions of input besides the unfavorable effect of resistance 21 from the central part of NMOS1 to the border of NMOS1 and PMOS2 as well as that of resistance 22 from the border to the central part of PMOS2 is entirely eliminated.
摘要翻译：目的：为了通过消除多晶硅栅电极的任何不利影响来加速电流，其中CMOS晶体管的PMOS侧输入端和NMOS侧输入端通过第二层上的Al布线相互连接两层布线。构成：由PMOS1和NMOS2组成的CMOS反相器具有公共的多晶硅电极3.输入端子17,18通过触点15,16与中间的Si栅电极3连接。 NMOS2侧的PMOS1侧和另一个输入端子18通过中间的通孔40,41在第二层上使用Al布线42彼此连接。通过这些步骤，由于操作速度可能不能除了从NMOS1的中心部分到NMOS1和PMOS2的边界的电阻21的不利影响以及从PMOS2的边界到中心部分的电阻22的不利影响之外，输入位置不平衡。

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