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1. 发明专利

JP2013069891A Shift register for memory 有权
标题翻译：记忆移位寄存器
公开(公告)号：JP2013069891A
公开(公告)日：2013-04-18
申请号：JP2011207707
申请日：2011-09-22
申请人： Toshiba Corp , 株式会社東芝
发明人： FUKUZUMI YOSHIAKI , AOCHI HIDEAKI , FUJIWARA TOMOKO
IPC分类号： H01L21/336 , H01L21/339 , H01L21/8242 , H01L21/8247 , H01L27/10 , H01L27/108 , H01L27/115 , H01L29/06 , H01L29/762 , H01L29/788 , H01L29/792
CPC分类号： B82Y10/00 , G11C19/00 , G11C19/282 , G11C19/38 , H01L27/1052 , H01L27/1057 , H01L27/115 , H01L27/11517 , H01L29/0676 , H01L29/068 , H01L29/788
摘要： PROBLEM TO BE SOLVED: To provide a shift register for large-capacity memory.SOLUTION: A shift register for memory comprises a substrate 101 and a spiral-shaped channel layer 111 which is formed on the substrate 101 and rotates around a shaft L vertical to a principal surface of the substrate 101. The shift register for memory further comprises three or more control electrodes 1121, 1122, and 1123 which are formed on the substrate 101 and used to transfer electric charge in the channel layer 111, and extend in a direction parallel to the shaft L.
摘要翻译：要解决的问题：提供用于大容量存储器的移位寄存器。解决方案：用于存储器的移位寄存器包括衬底101和形成在衬底101上并围绕垂直于衬底101的主表面的轴L旋转的螺旋形沟道层111.用于存储器的移位寄存器进一步包括三个或更多个控制电极1121,1122和1123，这些控制电极1121,1122和1123形成在基板101上并用于在沟道层111中传送电荷，并且在平行于轴L的方向上延伸。（C ）2013，JPO＆INPIT

2. 发明专利

JP4031552B2 Film formation method of a semiconductor device 失效
公开(公告)号：JP4031552B2
公开(公告)日：2008-01-09
申请号：JP8219597
申请日：1997-03-14
申请人：三星電子株式会社Samsung Electronics Co.,Ltd.
发明人：昌錫姜
IPC分类号： C30B29/32 , H01L21/31 , H01L21/316 , H01L21/8242 , H01L27/108
CPC分类号： H01L28/55 , H01L27/1057 , H01L27/11507

3. 发明专利

JPS5724940B2 JPS5724940B2 - 失效
公开(公告)号：JPS5724940B2
公开(公告)日：1982-05-26
申请号：JP4754976
申请日：1976-04-26
IPC分类号： H01L21/76 , H01L21/339 , H01L27/105 , H01L29/762
CPC分类号： H01L27/1057

4. 发明专利

JPS5778180A Semiconductor information transmission and memory device 失效
标题翻译：半导体信息传输和存储器件
公开(公告)号：JPS5778180A
公开(公告)日：1982-05-15
申请号：JP13311481
申请日：1981-08-24
申请人： Semiconductor Res Found
发明人： NISHIZAWA JIYUNICHI , NONAKA TERUMOTO
IPC分类号： G11C27/04 , H01L21/82 , H01L21/8247 , H01L27/105 , H01L27/146 , H01L29/788 , H01L29/792
CPC分类号： H01L27/1057
摘要： PURPOSE:To reduce the size of a semiconductor information transmission and memory device by adding an impurity forming a deep energy level on the surface of a semiconductor substrate contacted with an insulating layer and collecting and storing desired electrode position with the deep level transferred carrier, thereby eliminating a peripheral circuit, e.g., regenerative circuit. CONSTITUTION:A plurality of electrodes 5 are planarly disposed via an insulating layer 2 on one surface of a semiconductor region 1 of an MIS structure, and an electrode 4 functioning a ground is covered on the overall surface of the other surface. One carrier injecting electrode 3 is formed at the ends of a plurality of electrodes 5-1-5-n, 5 -1-5 -n, 5 -1-5 -n, 5 -1-5 -n, 5 -1-5 -n, 5 -1-5 -n. In this structure, an impurity forming deep collecting level, e.g., Ni, S, Ag, Au or the like is diffused or ion injected on the surface layer contacted with the layer 2 of the substrate 1. In the structure thus constructed, the prescribed voltage is applied to a plurality of electrodes 5. Then, carriers transferred from the adjacent electrode is collected by the deep level, thereby enabling desired information transmission and storage.
摘要翻译：目的：通过在与绝缘层接触的半导体衬底的表面上添加形成深能级的杂质并且与深层转移载体收集并存储期望的电极位置来减小半导体信息传输和存储器件的尺寸，由此消除外围电路，例如再生电路。构成：在MIS结构的半导体区域1的一个表面上经由绝缘层2平面地设置多个电极5，并且在另一个表面的整个表面上覆盖作为地面的电极4。一个载流子注入电极3形成在多个电极5-1-5-n，5-1-5-1 -n，5-2-1-5-2的末端，5,3-5,3-n，5 4 -1- [5-n，5n-1〜15n -n。在该结构中，形成深集合水平的杂质，例如Ni，S，Ag，Au等，在与衬底1的层2接触的表面层上扩散或离子注入。在这样构成的结构中，电压被施加到多个电极5.然后，从相邻电极传送的载流子被深层收集，从而实现期望的信息传输和存储。

5. 发明专利

JPS5726481A Solid state image pickup device 失效
标题翻译：固态图像拾取器件
公开(公告)号：JPS5726481A
公开(公告)日：1982-02-12
申请号：JP10161880
申请日：1980-07-23
申请人： Matsushita Electric Ind Co Ltd
发明人： YAMADA TAKAHIRO
IPC分类号： H01L27/06 , H01L27/105 , H01L27/146 , H01L27/148 , H04N5/335 , H04N5/341 , H04N5/372
CPC分类号： H01L27/1057 , H01L27/0688 , H01L27/14679 , H01L27/14831
摘要： PURPOSE:To perform extremely high speed and stable vertical transfer in an image pickup device by employing a vertical n n n configuration having p type well gate and vertically transferring via controlled drift electric field. CONSTITUTION:An n type region 303 is formed directly under an n type diffused layer 302 becoming a photodiode, and a p type region 304 operating as a gate surrounds the periphery of the region 303. The carrier photoelectrically converted from incident light 305 via diode 302 and stored operates to raise the voltage of an external power source E' and to lower the barrier voltage of the channel of the region 303, and reaches the lower n type region 306 vertically via the channel of the region 303. The carrier is then collected to a depletion layer formed in the region 306 by the voltage applied to the terminals 311, 312. Thereafter, 2-phase drive pulses applied to the terminals 311, 312 operate to frame transfer the carrier to the right side, and the carrier is thus horizontally transferred under the electrode of the horizontal transfer CCD17.
摘要翻译：目的：通过采用具有p型阱栅的垂直n + n + n +配置并通过受控漂移电场垂直传输，在图像拾取器件中执行极高速度和稳定的垂直传输。构成：n +型区域303直接形成在n +型扩散层302的正下方，成为光电二极管，作为栅极工作的p型区域304围绕区域303的周围。载流子从事件光电转换通过二极管302存储的光305操作以升高外部电源E'的电压并降低区域303的通道的势垒电压，并且经由通道的通道垂直到达下部n +型区域306 区域303.然后，通过施加到端子311,312的电压将载体收集到形成在区域306中的耗尽层。此后，施加到端子311,312的两相驱动脉冲将框架传送到因此水平传送CCD17的电极水平地传送载体。

6. 发明专利

JP5055980B2 Method of manufacturing a method of manufacturing a semiconductor device and the electronic device 有权
公开(公告)号：JP5055980B2
公开(公告)日：2012-10-24
申请号：JP2006322463
申请日：2006-11-29
申请人：富士通セミコンダクター株式会社
发明人：康由三島 , 輝雄倉橋 , 秀治志渡 , 武雄永田 , 健治石川
IPC分类号： H01L21/8242 , H01L21/3065 , H01L21/3205 , H01L21/336 , H01L21/768 , H01L21/8234 , H01L21/8246 , H01L27/08 , H01L27/088 , H01L27/10 , H01L27/105 , H01L27/108 , H01L29/78
CPC分类号： H01L21/823456 , H01L21/823468 , H01L27/1057 , H01L27/10805 , H01L27/10873 , H01L27/11507
摘要： A method for fabricating an electron device on a substrate includes the steps of forming a dummy film over the substrate such that the dummy film covers a device region of the substrate and an outer region of the substrate outside the device region, forming a dummy pattern by patterning the dummy film such that the dummy pattern has a first height in the device region and a second height smaller than the first height in the outer region, forming another film over the substrate such that the film covers the dummy pattern in the device region and in the outer region with a shape conformal to a cross-sectional shape of the dummy pattern, and applying an anisotropic etching process acting generally perpendicularly to the substrate such that a surface of the substrate is exposed in the device region and in the outer region.

7. 发明专利

JPS6193667A Charge coupled device 失效
标题翻译：电荷耦合器件
公开(公告)号：JPS6193667A
公开(公告)日：1986-05-12
申请号：JP21410384
申请日：1984-10-15
申请人： Hitachi Ltd
发明人： TSUKASAKI HISANOBU , MATSUMOTO SHUZO , KONDO KAZUO
IPC分类号： G11C27/04 , H01L21/339 , H01L27/105 , H01L29/76 , H01L29/762 , H01L29/768 , H01L29/772
CPC分类号： H01L27/1057 , H01L29/76833 , H01L29/76866
摘要： PURPOSE:To enable operation at low voltage by forming a floating diffusion layer between a BCCD and a SCCD and connecting both the BCCD and the SCCD through the floating diffusion layer. CONSTITUTION:A SCCD is used as a section adjacent to an output-section floating diffusion layer. Signal charges stored in potential under a gate such as one 15 move by the inversion of each driving pulse during an lapse to time t2 from t1, ad are stored in potential under a gate 18 at a time t=t2, OV is applied to the gate 15 at a time t=t2, and potential under the gate 15 reaches 6V. Signal charges are transferred to a floating diffusion region 2 at a time t=t3, converted into voltage signals, and extracted as output signals from an output terminal 32. Potential under a gate 19 is made deeper than that under the gate 18 and set at approximately 3V at that time, thus ensuring 6V obtained by subtracting potential 3V under the gate 19 from supply voltage 9V in the dynamic range of the floating diffusion region 2.
摘要翻译：目的：通过在BCCD和SCCD之间形成浮动扩散层，并通过浮动扩散层连接BCCD和SCCD两者，实现低电压工作。构成：SCCD用作与输出部分浮动扩散层相邻的部分。存储在门下的电位的信号电荷例如通过在经过t1之前的时间t2的每一个驱动脉冲的反转而移动的信号在时间t = t2处被存储在门18下方的电位中，OV被施加到门15在时间t = t2，栅极15下方的电位达到6V。信号电荷在时刻t = t3被转移到浮动扩散区域2，转换成电压信号，并作为输出端子32的输出信号提取。门19下方的电位比栅极18下方的电位更深，并设置在约3V，从而通过从浮动扩散区域2的动态范围内的电源电压9V中减去栅极19下的电位3得到6V。

8. 发明专利

JPS6127676A Analog image sensing memory using charge transfer 失效
标题翻译：使用充电传输的模拟图像感应存储器
公开(公告)号：JPS6127676A
公开(公告)日：1986-02-07
申请号：JP12729485
申请日：1985-06-13
申请人： Thomson Csf
发明人： JIYAN RIYUKU BERUJIE , RUI BURISO , IBON KAZOO
IPC分类号： G11B20/02 , G11C27/04 , H01L27/105 , H01L27/148
CPC分类号： H01L27/1057 , G11C27/04

9. 发明专利

JPS5925369B2 JPS5925369B2 - 失效
公开(公告)号：JPS5925369B2
公开(公告)日：1984-06-16
申请号：JP4113280
申请日：1980-03-28
申请人： Mitel Corp
发明人： ARAN AITOKEN
IPC分类号： H01L21/033 , H01L21/265 , H01L21/339 , H01L21/8234 , H01L21/8238 , H01L27/092 , H01L27/105 , H01L29/762
CPC分类号： H01L27/1057 , H01L21/033 , H01L21/8234 , H01L27/0927

10. 发明专利

JPS5925315B2 JPS5925315B2 - 失效
公开(公告)号：JPS5925315B2
公开(公告)日：1984-06-16
申请号：JP5637081
申请日：1981-04-16
申请人： Intaanashonaru Bijinesu Mashiinzu Corp
发明人： JON JOSEFU BAAN , JAN MARUKU FUEERU , IERANDEYUURU RANGANASA GOPARAKURISHUNA
IPC分类号： G11C27/04 , G11C19/28 , H01L21/339 , H01L27/105 , H01L29/762
CPC分类号： G11C19/287 , H01L27/1057

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