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1. 发明专利

JP2013069841A Semiconductor memory device and manufacturing method thereof 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：JP2013069841A
公开(公告)日：2013-04-18
申请号：JP2011207058
申请日：2011-09-22
申请人： Toshiba Corp , 株式会社東芝
发明人： FUJIKI JUN , FUKUZUMI YOSHIAKI , AOCHI HIDEAKI , FUJIWARA TOMOKO
IPC分类号： H01L21/8247 , H01L21/336 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of improving reliability and a reading speed, and a manufacturing method thereof.SOLUTION: A manufacturing method of a semiconductor memory device comprises the steps of: forming a laminate by alternately laminating a plurality of electrode films WL and interlayer insulating films 14; forming a plurality of through holes 18 extending in a lamination direction of the laminate; forming a charge accumulation film 23, an insulating film 24a, a first film 25 which uses germanium, and a second film 27 which uses aluminum inside the through holes; performing heat treatment for replacement to replace the first film and the second film and forming a semiconductor pillar SP by causing a growth of germanium on the side opposite to the insulating film of the second film; forming wiring above the laminate; and forming a gap 24b between the insulating film and the semiconductor pillar by selectively removing the replaced second film. An upper end of the semiconductor pillar is supported by the wiring formed above the laminate.
摘要翻译：要解决的问题：提供一种能够提高可靠性和读取速度的半导体存储器件及其制造方法。解决方案：半导体存储器件的制造方法包括以下步骤：通过交替层叠多个电极膜WL和层间绝缘膜14来形成层压体; 形成沿层叠体的层叠方向延伸的多个通孔18，形成电荷累积膜23，绝缘膜24a，使用锗的第一膜25和在通孔内使用铝的第二膜27; 进行热处理以替换第一膜和第二膜，并通过在与第二膜的绝缘膜相反的一侧引起锗的生长而形成半导体柱SP; 在层压板上方形成布线; 并且通过选择性地去除所取代的第二膜，在绝缘膜和半导体柱之间形成间隙24b。半导体柱的上端由形成在层叠体上方的布线支撑。版权所有（C）2013，JPO＆INPIT

2. 发明专利

JP2011096341A Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：JP2011096341A
公开(公告)日：2011-05-12
申请号：JP2009251892
申请日：2009-11-02
申请人： Toshiba Corp , 株式会社東芝
发明人： KATSUMATA RYUTA , AOCHI HIDEAKI , TANAKA HIROYASU , KITO TAKASHI , FUKUZUMI YOSHIAKI , KITO MASARU , KOMORI YOSUKE , ISHIZUKI MEGUMI , MATSUNAMI JUNYA , FUJIWARA TOMOKO , KIRISAWA RYOHEI , MIKAJIRI YOSHIMASA , OTA SHIGETO
IPC分类号： G11C29/04 , G11C16/02 , G11C16/04 , G11C29/56 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0483 , G11C16/06 , H01L27/11582 , H01L29/66833 , H01L29/7926
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory having high operation reliability. SOLUTION: The nonvolatile semiconductor memory is provided with a memory cell array and a control circuit. A laminate obtained by alternately laminating a plurality of insulating films and a plurality of electrode films is provided in the memory cell array. A through hole extending in the laminating direction is formed in the laminate, and silicon pillars are embedded therein. Between the electrode films and the silicon pillars, a charge accumulation film is provided. A memory cell is formed at each intersection of an electrode film and a silicon pillar. The control circuit writes a value "0" in all the memory cells during formatting, deletes the value "0" from all the memory cells, reads a value stored in the memory cell formed at the top of the laminate, determines that a delete error occurs in a memory cell from which the value "0" is read, and disables the memory cell. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供具有高操作可靠性的非易失性半导体存储器。解决方案：非易失性半导体存储器设置有存储单元阵列和控制电路。通过交替层叠多个绝缘膜和多个电极膜而获得的层叠体设置在存储单元阵列中。在层压体中形成沿层叠方向延伸的贯通孔，嵌入硅柱。在电极膜和硅柱之间，提供电荷蓄积膜。在电极膜和硅柱的每个交叉处形成存储单元。控制电路在格式化期间在所有存储单元中写入值“0”，从所有存储单元中删除值“0”，读取存储在叠层顶部形成的存储单元中的值，确定删除错误发生在读取值“0”的存储单元中，并禁用存储单元。版权所有（C）2011，JPO＆INPIT

3. 发明专利

JP2010225946A Nonvolatile semiconductor storage device, and method for manufacturing the same 有权
标题翻译：非挥发性半导体存储器件及其制造方法
公开(公告)号：JP2010225946A
公开(公告)日：2010-10-07
申请号：JP2009072950
申请日：2009-03-24
申请人： Toshiba Corp , 株式会社東芝
发明人： FUKUZUMI YOSHIAKI , KATSUMATA RYUTA , KITO TAKASHI , KITO MASARU , TANAKA HIROYASU , KOMORI YOSUKE , ISHIZUKI MEGUMI , MATSUNAMI JUNYA , FUJIWARA TOMOKO , AOCHI HIDEAKI , KIRISAWA RYOHEI , MIKAJIRI YOSHIMASA , OTA SHIGETO
IPC分类号： H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11582 , H01L21/223 , H01L21/265 , H01L27/11578 , H01L29/04 , H01L29/1037 , H01L29/16 , H01L29/42344 , H01L29/4916 , H01L29/66666 , H01L29/66833 , H01L29/7827 , H01L29/792 , H01L29/7926
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device, which is applicable to a hollow cylindrical semiconductor pillar, and provides a source drain diffusion layer having high position control in high concentration at low manufacturing costs, and also to provide a method for manufacturing the device.
SOLUTION: The device is provided with: a laminated structure ML having a plurality of insulating films 14 and a plurality of electrode films WL alternately laminated in a first direction; a selection gate electrode SG and an insulating layer 16 laminated on the laminated structure ML; the semiconductor pillar SP; a core portion 68; and a first conductive layer 18. The semiconductor pillar SP passes through the laminated structure ML, the selection gate electrode SG and the insulating layer 16 in the first direction, and has an annular cross-section when taken along a plane perpendicular to the first direction. The core portion 68 is embedded inside the semiconductor pillar SP, and retreats from the upper surface of the insulating layer 16. The first conductive layer 18 is provided on the core portion 68, while contacting with the core portion 68.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种可应用于中空圆柱形半导体柱的非易失性半导体存储装置，并且以低制造成本提供具有高浓度位置控制的源极漏极扩散层，并且还提供制造装置的方法。解决方案：该器件设置有：层叠结构ML，其具有多个绝缘膜14和沿第一方向交替层叠的多个电极膜WL; 层叠在层叠结构ML上的选择栅电极SG和绝缘层16; 半导体柱SP; 芯部68; 和第一导电层18.半导体柱SP沿着第一方向穿过叠层结构ML，选择栅电极SG和绝缘层16，并且当沿着垂直于第一方向的平面截取时具有环形横截面。芯部分68嵌入半导体柱SP内部，并从绝缘层16的上表面退回。第一导电层18设置在芯部68上，同时与芯部68接触。版权所有：（C）2011，JPO＆INPIT

4. 发明专利

JP2010205904A Method for manufacturing nonvolatile semiconductor memory device, and nonvolatile semiconductor memory device 审中-公开
标题翻译：用于制造非易失性半导体存储器件的方法和非易失性半导体存储器件
公开(公告)号：JP2010205904A
公开(公告)日：2010-09-16
申请号：JP2009049419
申请日：2009-03-03
申请人： Toshiba Corp , 株式会社東芝
发明人： FUKUZUMI YOSHIAKI , KATSUMATA RYUTA , KITO TAKASHI , KITO MASARU , TANAKA HIROYASU , KOMORI YOSUKE , ISHIZUKI MEGUMI , MATSUNAMI JUNYA , FUJIWARA TOMOKO , AOCHI HIDEAKI , KIRISAWA RYOHEI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11578 , H01L21/28282 , H01L27/11582
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a nonvolatile semiconductor memory device having high productivity by suppressing the number of film formation processes even in the case where the number of stacks increases, and to provide the nonvolatile semiconductor memory device.
SOLUTION: A nonvolatile semiconductor memory device includes: a stacked structural unit ML including a plurality of insulating films 14 alternately stacked with a plurality of electrode films WL: and semiconductor pillars SP piercing through the stacked structural unit in the stacked direction. A method for manufacturing the nonvolatile semiconductor memory device includes: forming a stacked unit ML0 including core material films 53 alternately stacked with sacrificial films 51 on a major surface of a substrate perpendicular to the first direction; forming trenches 71 in the stacked unit; embedding a filler 55 into the trenches; removing the sacrificial films to form a hollow structural unit ML1 including support sections 56 made of the filler and supporting the core material films on the substrate; and forming the stacked structural unit by stacking the insulating film and the electrode film on each surface of the core material films exposed by removing the sacrificial films.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决方案：即使在堆叠数量增加的情况下，通过抑制成膜处理次数来提供一种制造具有高生产率的非易失性半导体存储器件的方法，并提供非易失性半导体存储器件。解决方案：非易失性半导体存储器件包括：层叠结构单元ML，其包括交替层叠有多个电极膜WL的多个绝缘膜14以及沿堆叠方向穿过层叠结构单元的半导体柱SP。一种用于制造非易失性半导体存储器件的方法包括：在垂直于第一方向的衬底的主表面上形成包括与牺牲膜51交替层叠的芯材料膜53的堆叠单元ML0; 在堆叠单元中形成沟槽71; 将填料55嵌入沟槽中; 去除牺牲膜以形成包括由填料制成的支撑部分56的中空结构单元ML1，并将芯材膜支撑在基板上; 以及通过在除去牺牲膜而暴露的芯材膜的每个表面上堆叠绝缘膜和电极膜来形成层叠结构单元。版权所有（C）2010，JPO＆INPIT

5. 发明专利

JP2011035228A Nonvolatile semiconductor storage device and method for manufacturing the same 审中-公开
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：JP2011035228A
公开(公告)日：2011-02-17
申请号：JP2009181298
申请日：2009-08-04
申请人： Toshiba Corp , 株式会社東芝
发明人： KOMORI YOSUKE , AOCHI HIDEAKI , KATSUMATA RYUTA , KITO TAKASHI , FUKUZUMI YOSHIAKI , KITO MASARU , TANAKA HIROYASU , ISHIZUKI MEGUMI , FUJIWARA TOMOKO , KIRISAWA RYOHEI , MIKAJIRI YOSHIMASA , OTA SHIGETO
IPC分类号： H01L27/115 , H01L21/8247 , H01L29/788 , H01L29/792
CPC分类号： H01L29/792 , H01L27/11573 , H01L27/11578 , H01L27/11582 , H01L29/66833 , H01L29/7926
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device, reducing the resistance of a selection gate electrode and having high response characteristic in a selection gate transistor for selecting a semiconductor pillar, and also to provide a method for manufacturing the device. SOLUTION: The nonvolatile semiconductor storage device is equipped with: a lamination structure ML including a plurality of electrode films WL and a plurality of interelectrode insulating films 14 which are alternately laminated in a first direction; a selection gate electrode SG laminated on the lamination structure ML in the first direction; a semiconductor pillar SP pierced into the lamination structure ML and the selection gate electrode SG in the first direction; a storage part formed on an intersection part between respective electrode films WL and the semiconductor pillar SP; and a selection gate insulating film SGI formed between the semiconductor pillar SP and the selection gate electrode SG. The selection gage electrode SG has a first silicide layer 51 formed on the surface of the selection gate electrode SG, the surface which is vertical to the first direction of the selection gate. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种非易失性半导体存储装置，在用于选择半导体柱的选择栅极晶体管中降低选择栅电极的电阻并具有高响应特性，并且还提供一种制造器件的方法。解决方案：非易失性半导体存储装置配备有：层叠结构ML，其包括沿第一方向交替层叠的多个电极膜WL和多个电极间绝缘膜14; 在第一方向层压在层压结构ML上的选择栅电极SG; 半导体柱SP在第一方向上穿透层叠结构ML和选择栅电极SG; 形成在各个电极膜WL和半导体柱SP之间的交叉部分上的存储部件; 以及形成在半导体柱SP和选择栅电极SG之间的选择栅极绝缘膜SGI。选择量规电极SG具有形成在选择栅电极SG的表面上的与选择栅极的第一方向垂直的表面的第一硅化物层51。版权所有（C）2011，JPO＆INPIT

6. 发明专利

JP2010192569A Nonvolatile semiconductor memory device and method for manufacturing the same 审中-公开
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：JP2010192569A
公开(公告)日：2010-09-02
申请号：JP2009033759
申请日：2009-02-17
申请人： Toshiba Corp , 株式会社東芝
发明人： TANAKA HIROYASU , AOCHI HIDEAKI , KATSUMATA RYUTA , KITO MASARU , KITO TAKASHI , FUKUZUMI YOSHIAKI , KOMORI YOSUKE , ISHIZUKI MEGUMI , FUJIWARA TOMOKO , MATSUNAMI JUNYA , KIRISAWA RYOHEI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/792 , H01L27/11578 , H01L27/11582 , H01L29/66833
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device having an integrally processed three-dimensional stacked structure improved in integration: and to provide a method for manufacturing the same. SOLUTION: The nonvolatile semiconductor memory device includes: a semiconductor substrate 11; a stacked body ML provided on the semiconductor substrate, the stacked body having a plurality of electrode films WL and a plurality of insulating films 12 being alternately stacked; a first and second semiconductor pillars SP1 and SP2 provided inside a through-hole H0 penetrating through the stacked body in a stacking direction of the stacked body; and first and second charge accumulating layers CT2 and CT4 provided between the electrode film and the first and second semiconductor pillars respectively. The first through-hole includes a cross section of an oblate circle, and the first and second semiconductor pillars SP1 and SP2 face each other in the longitudinal axis direction of the oblate circle. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有整体改进的整体处理的三维堆叠结构的非易失性半导体存储器件，并提供其制造方法。解决方案：非易失性半导体存储器件包括：半导体衬底11; 设置在所述半导体基板上的层叠体ML，所述层叠体具有交替层叠的多个电极膜WL和多个绝缘膜12; 第一和第二半导体柱SP1和SP2，设置在贯穿层叠体的层叠体的堆叠方向的贯通孔H0的内部; 以及设置在电极膜和第一和第二半导体柱之间的第一和第二电荷累积层CT2和CT4。第一通孔包括扁圆形的横截面，并且第一和第二半导体柱SP1和SP2在扁圆的纵向轴线方向上彼此面对。版权所有（C）2010，JPO＆INPIT

7. 发明专利

JP2013187294A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2013187294A
公开(公告)日：2013-09-19
申请号：JP2012050403
申请日：2012-03-07
申请人： Toshiba Corp , 株式会社東芝
发明人： FUJIWARA TOMOKO , FUKUZUMI YOSHIAKI , AOCHI HIDEAKI
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/792 , H01L27/1157 , H01L27/11573 , H01L27/11582
摘要： PROBLEM TO BE SOLVED: To achieve relaxation of operating control and circuit layout design while improving charge holding characteristics.SOLUTION: A semiconductor memory device includes: a semiconductor substrate; a first layer that is formed above the semiconductor substrate; a first conductive layer, an inter-electrode insulating layer, and a second conductive layer that are stacked above the first layer; a block insulating layer that is formed on inner surfaces of a pair of through holes provided in the first conductive layer, the inter-electrode insulating layer, and the second conductive layer, and on an inner surface of a connection hole provided in the first layer; a charge storage layer that is formed on the block insulating layer; a second layer that is formed on the charge storage layer; and a semiconductor layer that is formed on the second layer. The second layer has a gap layer on the charge storage layer in the pair of through holes provided in the second conductive layer, and has a third conductive layer on the charge storage layer in the connection hole provided in the first layer.
摘要翻译：要解决的问题：在提高电荷保持特性的同时，实现操作控制和电路布局设计的放松。解决方案：半导体存储器件包括：半导体衬底; 形成在半导体衬底上的第一层; 层叠在第一层之上的第一导电层，电极间绝缘层和第二导电层; 形成在设置在第一导电层，电极间绝缘层和第二导电层中的一对通孔的内表面上的块绝缘层，以及设置在第一层中的连接孔的内表面 ; 形成在所述块绝缘层上的电荷存储层; 形成在电荷存储层上的第二层; 以及形成在第二层上的半导体层。第二层在设置在第二导电层中的一对通孔中的电荷存储层上具有间隙层，并且在设置在第一层中的连接孔中的电荷存储层上具有第三导电层。

8. 发明专利

JP2013026397A Shift register for memory and manufacturing method therefor 审中-公开
标题翻译：用于存储器和其制造方法的移位寄存器
公开(公告)号：JP2013026397A
公开(公告)日：2013-02-04
申请号：JP2011159082
申请日：2011-07-20
申请人： Toshiba Corp , 株式会社東芝
发明人： FUKUZUMI YOSHIAKI , KITO TAKASHI , FUJIWARA TOMOKO , KAWASAKI KAORI , AOCHI HIDEAKI
IPC分类号： H01L21/8247 , G11C27/04 , H01L21/336 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L21/84 , G11C19/00 , H01L27/10 , H01L27/11517 , H01L27/1203
摘要： PROBLEM TO BE SOLVED: To provide a highly reliable large capacity shift register for memory which can be manufactured with a small number of steps.SOLUTION: The shift register for memory includes first and second control electrodes extending in a first direction parallel with the principal surface of a substrate, and facing each other in a second direction perpendicular to the first direction. Furthermore, the register includes a plurality of first floating electrodes provided in one row on the first control electrode side between the first and second control electrodes. Furthermore, the register includes a plurality of second floating electrodes provided in one row on the second control electrode side between the first and second control electrodes. Furthermore, each of the first and second floating electrodes has a mirror asymmetrical plane shape for a plane perpendicular to the first direction.
摘要翻译：要解决的问题：提供一种高可靠性的大容量移位寄存器，用于可以用少量步骤制造的存储器。解决方案：用于存储器的移位寄存器包括在与基板的主表面平行的第一方向上延伸的第一和第二控制电极，并且在垂直于第一方向的第二方向上彼此面对。此外，寄存器包括设置在第一和第二控制电极之间的第一控制电极侧的一行中的多个第一浮置电极。此外，寄存器包括设置在第一和第二控制电极之间的第二控制电极侧的一行中的多个第二浮置电极。此外，第一和第二浮置电极中的每一个具有用于垂直于第一方向的平面的反射镜不对称平面形状。版权所有（C）2013，JPO＆INPIT

9. 发明专利

JP2013025838A Nonvolatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2013025838A
公开(公告)日：2013-02-04
申请号：JP2011158565
申请日：2011-07-20
申请人： Toshiba Corp , 株式会社東芝
发明人： IWAI HITOSHI , FUJIWARA TOMOKO , KITO TAKASHI , AOCHI HIDEAKI
IPC分类号： G11C16/02 , G11C16/04 , H01L21/336 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/3454 , G11C16/0483 , G11C16/06
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device which suppresses deterioration of data.SOLUTION: In the nonvolatile semiconductor storage device, a memory cell includes a semiconductor layer, a charge storage layer, and a conductive layer. In the memory cell, the semiconductor layer extends in a direction perpendicular to a semiconductor substrate and functions as a body of the memory cell, the charge storage layer is provided on the side face of the semiconductor layer and stores charges, and the conductive layer is provided so as to sandwich the semiconductor layer and the charge storage layer and functions as a gate of the memory cell. In the nonvolatile semiconductor storage device, a control circuit performs a first program operation and then performs a second program operation, and the first program operation is an operation for applying a first voltage to the body of the memory cell and applying a second voltage larger than the first voltage to the gate of the memory cell, and thereby shifting a threshold voltage of the memory cell to a positive direction, and the second program operation is an operation for floating the body of the memory cell and applying a third positive voltage to the gate of the memory cell.
摘要翻译：解决的问题：提供一种抑制数据劣化的非易失性半导体存储装置。解决方案：在非易失性半导体存储装置中，存储单元包括半导体层，电荷存储层和导电层。在存储单元中，半导体层在与半导体基板垂直的方向上延伸，作为存储单元的主体，电荷存储层设置在半导体层的侧面并存储电荷，导电层为被设置为夹住半导体层和电荷存储层，并且用作存储单元的栅极。在非易失性半导体存储装置中，控制电路进行第一编程动作，然后进行第二编程动作，第一编程动作是向存储单元的主体施加第一电压并施加大于第一电压到存储器单元的栅极，从而将存储单元的阈值电压移动到正方向，并且第二编程操作是用于使存储单元的主体浮动并向第一正电压施加第三正电压的操作存储单元的门。版权所有（C）2013，JPO＆INPIT

10. 发明专利

JP2012160222A Nonvolatile semiconductor memory device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2012160222A
公开(公告)日：2012-08-23
申请号：JP2011017709
申请日：2011-01-31
申请人： Toshiba Corp , 株式会社東芝
发明人： FUJIWARA TOMOKO , KITO TAKASHI , FUKUZUMI YOSHIAKI , AOCHI HIDEAKI
IPC分类号： G11C16/02 , G11C16/04 , H01L21/336 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11573 , G11C11/5628 , G11C16/0483 , G11C16/10 , H01L27/11582 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device for shortening a writing time and suppressing the increase in reading voltage.SOLUTION: A nonvolatile semiconductor memory device comprises a memory unit and a control unit. The memory unit has a laminated structure, a semiconductor pillar, a storage layer, an inner insulating film, an outer insulating film and a memory cell transistor. The control unit performs control of setting each threshold of the memory cell transistor to either positive or negative and performs control so that the width of distribution of m-th threshold (m is an integer of 1 or more which is smaller than n) having the same sign as the n-th threshold is set narrower than the width of distribution of the n-th threshold which is most distant from 0 volts among the respective thresholds.
摘要翻译：要解决的问题：提供一种用于缩短写入时间并抑制读取电压增加的非易失性半导体存储器件。解决方案：非易失性半导体存储器件包括存储器单元和控制单元。存储单元具有叠层结构，半导体柱，存储层，内绝缘膜，外绝缘膜和存储单元晶体管。控制单元执行将存储单元晶体管的每个阈值设置为正或负的控制，并进行控制，使得具有第m阈值（m为小于n的1以上的整数）的分布宽度与第n个阈值相同的符号被设定为比各个阈值中距离0伏最远的第n个阈值的分布宽度窄。版权所有（C）2012，JPO＆INPIT

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