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1. 发明专利

JP6320546B2 演算増幅回路有权
公开(公告)号：JP6320546B2
公开(公告)日：2018-05-09
申请号：JP2016551360
申请日：2014-09-29
申请人：三菱電機株式会社
发明人：中井貴之
IPC分类号： H03F3/45
CPC分类号： H01L27/0928 , H01L21/823892 , H01L27/092 , H01L27/0925 , H01L27/0927 , H03F3/3013 , H03F3/3018 , H03F3/45183 , H03F3/45224 , H03F2203/30006 , H03F2203/45006 , H03F2203/45281

2. 发明专利

JP3373618B2 Element separation method of semiconductor device 失效
公开(公告)号：JP3373618B2
公开(公告)日：2003-02-04
申请号：JP25732993
申请日：1993-10-14
申请人：ローム株式会社
发明人：規之下地
IPC分类号： H01L21/265 , H01L21/76 , H01L21/762 , H01L21/8238 , H01L27/092
CPC分类号： H01L21/823807 , H01L21/76218 , H01L27/0927

3. 发明专利

JPS6184051A Semiconductor element 失效
标题翻译：半导体元件
公开(公告)号：JPS6184051A
公开(公告)日：1986-04-28
申请号：JP20551884
申请日：1984-10-02
申请人： Oki Electric Ind Co Ltd
发明人： KITA AKIO
IPC分类号： H01L21/8234 , H01L21/8238 , H01L27/088 , H01L27/092 , H01L29/78
CPC分类号： H01L27/0927
摘要： PURPOSE:To achieve high integration of CMOS type IC by a method wherein N layers to be formed utilizing a gate electrode as a mask are laid between N layers or P layers to constitute an N or P channel MOSFET. CONSTITUTION:N and P channel MOSFET101, 102 are separated from each other on an N type Si substrate 1. A gate oxide film 9 and a gate electrode 5 are laminated on a P type impurity doped layer 2 while spacers 7 are arranged on both sidewalls of electrode 5. In the FET101, N layers 6 and N layers 8 adjoining thereto are formed in the substrate 1 below the spacers 7. On the other hand, in the other FET102, P layers 9 are formed adjoining to the layers 6. In such a constitution, in the FET101, hot carrier effect may be eased up utilizing the layers 6 and 8 respectively as source and drain making use of the spacers 7 while in the FET102, the layers 6 may be laid between channels and drains to avoid punch through action making high integration feasible.
摘要翻译：目的：为了实现CMOS型IC的高集成度，其中利用栅极作为掩模形成的N +层铺设在N +层或P +层之间以构成N或P沟道 MOSFET。构成：N沟道MOSFET101,102在N型Si衬底1上彼此分离。栅极氧化膜9和栅电极5层压在P型杂质掺杂层2上，而间隔物7被布置在两个侧壁上在FET101中，与衬垫1相邻的N +层6和N +层8形成在衬垫1的下方。另一方面，在另一个FET102中，P + 在这种结构中，在FET101中，利用层6和8分别作为使用间隔物7的源极和漏极，FET102中的层6可以在FET101中缓和热载流子效应，层6可以铺设在通道和排水沟之间，以避免穿透动作，从而实现高集成度。

4. 发明专利

JPS617032B2 JPS617032B2 - 失效
公开(公告)号：JPS617032B2
公开(公告)日：1986-03-03
申请号：JP13054978
申请日：1978-10-25
申请人： Hitachi Ltd
发明人： MEGURO SATOSHI
IPC分类号： H01L27/04 , H01L21/822 , H01L27/092 , H01L27/10
CPC分类号： H01L27/0927

5. 发明专利

JPS59107560A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路设备
公开(公告)号：JPS59107560A
公开(公告)日：1984-06-21
申请号：JP21682182
申请日：1982-12-13
申请人： Hitachi Ltd
发明人： MINATO OSAMU , MASUHARA TOSHIAKI , SASAKI TOSHIO , YAMAMOTO AKIRA
IPC分类号： H01L27/08 , H01L21/8238 , H01L27/092 , H01L29/78
CPC分类号： H01L27/0927
摘要： PURPOSE:To prevent the variation of characteristics due to microminiaturization, and to obtain a LSI of high performance by a method wherein a power supply circuit is set up to the CMOSIC by n type and p type channel FETS, first power supply voltage is applied from the outside, low output voltage is obtained and a main circuit on the same substrate is operated. CONSTITUTION:External supply voltage VC1 is applied to the n type substrate 202 through an n layer 226, and converted into VC2 by a circuit 5. p Wells 204, 206 are grounded through p layers 208, 210. An inverter is constituted by the p type FET by p layers 216, 218 and the n type FET by n layers 212, 214 in the well 204, and VC2 is applied to a drain 216. On the other hand, the circuit is formed by the n type FET by n layers 220, 222, 224, and VC2 is applied through a resistor 228. Channel length is lengthened in the FETs except the main circuit 6 at that time, and the variation of the characteristics of circuit 6 itself is prevented. Accordingly, the LSI of high performance with the high degree of integration can be realized by using the microminiaturized MOSFET.
摘要翻译：目的：为了防止由于微小型化导致的特性变化，并且通过其中通过n型和p型沟道FETS将电源电路设置到CMOSIC的方法获得高性能的LSI，从第一电源电压外部获得低输出电压，并且在同一基板上操作主电路。构成：外部电源电压VC1通过n +层226施加到n型衬底202，并由电路5转换成VC2。p阱204,206通过p +层208,210接地。逆变器由p +层216,218的p型FET和阱204中的n +层212,214构成，VC2被施加到漏极216。另一方面，电路由n +型FET由n + +层220,222,224形成，并且VC2通过电阻器228施加。此时，除了主电路6之外的FET中的沟道长度被延长，并且变化可以防止电路6本身的特性。因此，可以通过使用微型化的MOSFET来实现具有高集成度的高性能的LSI。

6. 发明专利

JPS595658A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路设备
公开(公告)号：JPS595658A
公开(公告)日：1984-01-12
申请号：JP11389982
申请日：1982-07-02
申请人： Hitachi Ltd
发明人： MIYAKE NORIO , IWABUCHI MASARU
IPC分类号： H01L29/78 , H01L21/82 , H01L27/092 , H01L27/118
CPC分类号： H01L27/0927
摘要： PURPOSE:To make it possible to perform high speed operation, by forming gate electrodes and their wirings by a common high concentration polycrystal silicon layer, using the layer as a wiring between both cells, thereby reducing the wiring resistance especially at a wiring channel part. CONSTITUTION:Each gate electrode of both MISFETs 1 and 2 is formed by a common poly Si layer 15 with high concentration (e.g. 10 -10 /cm ). Said poly Si itself is extended as a wiring 5 and used for connecting opposing cell regions. When CMOS is manufactured (especially in a 3mum process), phosphorus treatment is performed on the entire surface after the poly Si for the gate electrodes is deposited. As this time, the entire poly Si layer is made to have high impurity concentration (an N electrode). Therfore, when P type impurities for forming source and drain regions of a P channel MISFET, e.g. of boron, are implanted at the next process, N type conductivity is held at high concentration in the poly Si gate electrode of said MOSFET.
摘要翻译：目的：为了能够进行高速运转，通过利用普通的高浓度多晶硅层形成栅极电极及其配线，可以将该层作为两个电池之间的布线，从而降低布线通道部分的布线电阻。构成：两个MISFET 1和2的每个栅极由具有高浓度（例如10 <14> -10 15 / cm 3）的普通多晶硅层15形成。所述多晶硅本身作为布线5延伸并用于连接相对的单元区域。当制造CMOS（特别是3μm工艺）时，在沉积用于栅电极的多晶硅之后，在整个表面上进行磷处理。此时，使整个多晶硅层具有高杂质浓度（N电极）。因此，当用于形成P沟道MISFET的源极和漏极区域的P型杂质时，例如，的硼在下一个工艺中被注入，在所述MOSFET的多晶硅栅电极中以高浓度保持N型导电性。

7. 发明专利

JPS5756963A Mos device with channel stopping region ion implanted and method of producing same 失效
标题翻译：具有通道停放区域的MOS器件及其制造方法
公开(公告)号：JPS5756963A
公开(公告)日：1982-04-05
申请号：JP7636681
申请日：1981-05-20
申请人： Suupaatetsukusu Inc
发明人： ROBAATO RUISU CHIYAO
IPC分类号： G11C17/00 , G11C17/08 , H01L21/8246 , H01L27/092 , H01L27/112 , H01L29/06 , H01L29/78
CPC分类号： H01L29/0638 , H01L27/0927 , H01L27/112

8. 发明专利

JPS617034B2 JPS617034B2 - 失效
公开(公告)号：JPS617034B2
公开(公告)日：1986-03-03
申请号：JP14573379
申请日：1979-11-10
申请人： Tokyo Shibaura Electric Co
发明人： KONDO TAKEO
IPC分类号： H01L21/822 , H01L21/22 , H01L21/761 , H01L21/8238 , H01L27/04 , H01L27/092 , H01L29/08 , H01L29/78
CPC分类号： H01L27/0927 , H01L29/0847
摘要： PURPOSE:To increase the degree of integration by preventing the punch through that will be caused at the corner of the diffused layer without occupying margin and also without decreasing the impurity concentration of the substrate. CONSTITUTION:In the case the impurities are diffused in the semiconductor substrate, the extension of the diffusion at the corner depends largely on the ratio between the concentration of the surface of the impurity layer and the concentration of the substrate. It is especially large at the corner of a P-well layer of CMOS. Therefore, the sufficiently large margin has been given in the conventional devices and the degree of integration has been hampered. Now the configuration of a mask 4 is improved so that the corner 21 of an N layer 3 is diagonally cut out. In this constitution, since the distance between the P well 2 and the N layer 3 at the corner is broadened, said distances at the corner and the sides are uniformly averaged, and the punch through can be perfectly prevented. Since the distance between the N layer mask 4 and the P well mask 5 can be shortened, the IC can be advantageously miniaturized. In this constitution, the concentration of the impurities in the substrate need not be decreased.

9. 发明专利

JPS59111357A C-mos integrated circuit and usage thereof 失效
标题翻译： C-MOS集成电路及其应用
公开(公告)号：JPS59111357A
公开(公告)日：1984-06-27
申请号：JP22121782
申请日：1982-12-17
申请人： Nec Corp
发明人： YAMAZAKI TAKASHI , ANDOU TAKESHI
IPC分类号： H01L21/8238 , H01L27/02 , H01L27/092 , H01L29/78
CPC分类号： H01L27/0927 , H01L27/0203
摘要： PURPOSE:To shut out the electric noise generating between a digital circuit part and an analog circuit part by a method wherein a C-MOS integrated circuit is composed of the digital circuit part formed on a one-conductive type semiconductor substrate, and the isolation part having the reverse conductive type diffusion layer to be used for isolation of the circuit parts formed between analog circuit parts and an electrode to be connected to said diffusion layer. CONSTITUTION:The isolated part consisting of a P-well 2', a P type diffusion layer 4' and an electrode 6 is formed between the digital circuit part 10 and the analog circuit part 20. When a C-MOS integrated circuit is going to be used, the lowest potential to be used on the C-MOS integrated circuit is given to the electrode 6. If the electric noise generated on the digital circuit 10 is composed of a positive charge, it is absorbed by the P-well 2' and brought to outside by the electrode 6'. Also, if the electric noise is composed of a negative charge, it is repulsed by the depletion layer which will be formed in the vicinity of the P-well 2', and it cannot reach the analog circuit part 20.
摘要翻译：目的：为了通过其中C-MOS集成电路由形成在一导体型半导体衬底上的数字电路部分和隔离部分组成的方法来阻止数字电路部分和模拟电路部分之间的电噪声产生具有用于隔离形成在模拟电路部分和要连接到所述扩散层的电极之间的电路部分的反向导电型扩散层。构成：在数字电路部分10和模拟电路部分20之间形成由P阱2'，P型扩散层4'和电极6构成的隔离部分。当C-MOS集成电路要使用在C-MOS集成电路上使用的最低电位给电极6.如果在数字电路10上产生的电噪声由正电荷组成，则由P阱2' 并由电极6'带到外部。此外，如果电噪声由负电荷组成，则由在P阱2'附近形成的耗尽层排斥，并且不能到达模拟电路部20。

10. 发明专利

JPS5957469A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：JPS5957469A
公开(公告)日：1984-04-03
申请号：JP16750582
申请日：1982-09-28
申请人： Fujitsu Ltd
发明人： INABA TOORU , SHINGUU MASATAKA
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/78
CPC分类号： H01L27/0927
摘要： PURPOSE:To reduce the absolute value of threshold voltage as well as to enable to limit the number of contact holes by a method wherein a silicide layer is provided on a P type silicon gate electrode and an N type silicon gate electrode in such a manner that said P type and N type silicon gate electrodes are connected. CONSTITUTION:A P-well 12, an N source or drain region 13 and a P source or drain region 14 are arranged on an N type silicon substrate 11, an SiO2 film 15 is provided on the N type silicon substrate 11, and a P type polycrystalline silicon gate electrode 16 is provided on the SiO2 film located on the side of the P source or drain region 13. On the other hand, an N type polycrystalline silicon gate electrode 17 is provided on the SiO2 film 15 located on the side of the N source or drain region 14. Said P type and N type polycrystalline silicon electrodes are formed continuously on the SiO2 film 15 using a CVD method, a molybdenum silicide layer 18 is provided on said electrodes in such a manner that the P type and N type gate electrodes are connected and besides, a phosphosilicate glass layer 19 is provided on the molybdenum silicide layer 18.
摘要翻译：目的：为了降低阈值电压的绝对值，并且能够通过其中在P型硅栅电极和N型硅栅电极上设置硅化物层的方法来限制接触孔的数量，使得所述P型和N型硅栅电极连接。构成：在N型硅衬底11上配置P阱12，N +源极或漏极区13以及P +源极或漏极区14，在N型硅上设置SiO 2膜15 基板11和P型多晶硅栅电极16设置在位于P +源极或漏极区域侧的SiO 2膜上。另一方面，N型多晶硅栅电极17设置在位于N +源极或漏极区域14侧的SiO 2膜15.使用CVD法在SiO 2膜15上连续形成所述P型和N型多晶硅电极，将硅化钼层18设置在所述电极以P型和N型栅电极连接，此外，磷硅玻璃层19设置在硅化钼层18上。

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