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3. 发明专利

JPWO2013161891A1 チップオンウエハ接合方法及び接合装置並びにチップとウエハとを含む構造体有权
标题翻译：结构包括芯片上晶片接合方法和接合装置，并且所述芯片和晶片
公开(公告)号：JPWO2013161891A1
公开(公告)日：2015-12-24
申请号：JP2014512656
申请日：2013-04-24
申请人：須賀唯知 , 唯知須賀 , ボンドテック株式会社
发明人：須賀　唯知 , 唯知須賀 , 山内　朗 , 朗山内
IPC分类号： H01L21/60 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L25/0652 , B23K31/02 , B23K37/00 , B23K37/0408 , B23K2201/40 , H01L21/6836 , H01L22/10 , H01L23/10 , H01L23/562 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/08 , H01L24/09 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/73 , H01L24/74 , H01L24/742 , H01L24/743 , H01L24/75 , H01L24/80 , H01L24/81 , H01L24/83 , H01L24/94 , H01L24/95 , H01L25/105 , H01L25/50 , H01L2221/68327 , H01L2224/0384 , H01L2224/03845 , H01L2224/0401 , H01L2224/05009 , H01L2224/05611 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/06134 , H01L2224/0615 , H01L2224/06177 , H01L2224/08145 , H01L2224/08225 , H01L2224/09181 , H01L2224/1184 , H01L2224/11845 , H01L2224/13009 , H01L2224/13016 , H01L2224/13017 , H01L2224/13021 , H01L2224/13022 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/14134 , H01L2224/1415 , H01L2224/14177 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/17181 , H01L2224/27009 , H01L2224/2755 , H01L2224/27823 , H01L2224/2784 , H01L2224/27845 , H01L2224/29111 , H01L2224/29144 , H01L2224/29147 , H01L2224/29155 , H01L2224/32145 , H01L2224/32225 , H01L2224/33181 , H01L2224/73103 , H01L2224/74 , H01L2224/7501 , H01L2224/75101 , H01L2224/75102 , H01L2224/7525 , H01L2224/75251 , H01L2224/75252 , H01L2224/75283 , H01L2224/753 , H01L2224/75301 , H01L2224/7531 , H01L2224/75501 , H01L2224/75502 , H01L2224/7565 , H01L2224/75701 , H01L2224/75702 , H01L2224/75753 , H01L2224/75802 , H01L2224/75804 , H01L2224/75824 , H01L2224/75842 , H01L2224/7598 , H01L2224/80003 , H01L2224/8001 , H01L2224/80013 , H01L2224/80065 , H01L2224/8013 , H01L2224/80132 , H01L2224/80143 , H01L2224/80201 , H01L2224/80203 , H01L2224/8022 , H01L2224/8023 , H01L2224/80447 , H01L2224/8083 , H01L2224/80907 , H01L2224/81002 , H01L2224/8101 , H01L2224/81013 , H01L2224/81065 , H01L2224/8113 , H01L2224/81132 , H01L2224/81143 , H01L2224/81193 , H01L2224/81201 , H01L2224/81203 , H01L2224/8122 , H01L2224/8123 , H01L2224/81447 , H01L2224/81801 , H01L2224/81805 , H01L2224/8183 , H01L2224/81907 , H01L2224/83002 , H01L2224/8301 , H01L2224/83013 , H01L2224/83048 , H01L2224/83051 , H01L2224/83065 , H01L2224/83091 , H01L2224/8313 , H01L2224/83132 , H01L2224/83136 , H01L2224/83143 , H01L2224/83193 , H01L2224/83201 , H01L2224/83203 , H01L2224/8322 , H01L2224/8323 , H01L2224/83234 , H01L2224/83355 , H01L2224/83447 , H01L2224/83801 , H01L2224/8383 , H01L2224/83894 , H01L2224/83907 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06565 , H01L2225/1023 , H01L2225/1058 , H01L2924/01322 , H01L2924/10157 , H01L2924/10253 , H01L2924/3511 , H01L2224/81 , H01L2924/00012 , H01L2924/00014 , H01L2924/01047 , H01L2224/80 , H01L2224/83 , H01L2924/00
摘要：【課題】接合界面に樹脂などの望ましくない残存物を残さないようにして、チップとウエハとの間又は積層された複数のチップ間の電気的接続を確立し機械的強度を上げる、ウエハ上にチップを効率よく接合する技術を提供すること。【解決手段】金属領域を有するチップ側接合面を有する複数のチップを、複数の接合部を有する基板に接合する方法が、チップ側接合面の金属領域を、表面活性化処理し、かつ親水化処理するステップ(S1)と、基板の接合部を表面活性化処理し、かつ親水化処理するステップ(S2)と、表面活性化処理されかつ親水化処理された複数のチップを、それぞれ、チップの金属領域が基板の接合部に接触するように、表面活性化処理されかつ親水化処理された基板の対応する接合部上に取り付けるステップ(S3)と、基板と基板上に取り付けられた複数のチップとを含む構造体を加熱するステップ(S4)とを備える。【選択図】図1
摘要翻译：甲以免留下不希望的残余物，如键合界面的树脂，增加之间或多个芯片和晶片的堆叠芯片的之间所建立的机械强度的电连接，在晶片上以用于有效地接合所述芯片的技术。多个具有具有的金属区域，粘接到具有多个关节的底物的方法，所述芯片侧粘结表面的金属区域，处理过的表面活化，和亲水性的芯片侧粘结表面的芯片步骤（S1），以进行处理，该基板处理过的表面活化的接合处，并且步骤（S2）亲水性处理，将多个芯片被处理表面活化和分别亲水化，芯片如在与基板的接合部接触的金属区域，所述步骤（S3），用于安装在表面处理的激活，并且已被亲水化的基板，安装在基板上的多个芯片的相应接头和基板上和用于加热含有结构和步骤（S4）。点域1

4. 发明专利

JP5619542B2 半導体基板の処理方法及び半導体装置の製造方法有权
标题翻译：制造半导体衬底处理方法，所述的方法和半导体器件
公开(公告)号：JP5619542B2
公开(公告)日：2014-11-05
申请号：JP2010201023
申请日：2010-09-08
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/522
CPC分类号： H01L21/76898 , H01L23/481 , H01L2224/0401 , H01L2224/05 , H01L2224/11 , H01L2224/13 , H01L2224/13009 , H01L2224/14181 , H01L2225/06541

5. 发明专利

JP2014195041A Semiconductor device and semiconductor device manufacturing method 有权
标题翻译：半导体器件和半导体器件制造方法
公开(公告)号：JP2014195041A
公开(公告)日：2014-10-09
申请号：JP2013217624
申请日：2013-10-18
申请人： Shinko Electric Ind Co Ltd , 新光電気工業株式会社
发明人： ICHIKAWA SUMIHIRO , YAMANO KOJI
IPC分类号： H01L23/12
CPC分类号： H01L23/481 , H01L21/6836 , H01L21/76898 , H01L23/3128 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/16 , H01L25/0657 , H01L25/50 , H01L2221/68327 , H01L2221/6834 , H01L2224/02372 , H01L2224/02379 , H01L2224/03002 , H01L2224/03464 , H01L2224/03912 , H01L2224/0401 , H01L2224/05008 , H01L2224/05022 , H01L2224/05541 , H01L2224/05557 , H01L2224/05559 , H01L2224/05562 , H01L2224/05567 , H01L2224/05568 , H01L2224/0557 , H01L2224/05611 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/06181 , H01L2224/11464 , H01L2224/1147 , H01L2224/1181 , H01L2224/11849 , H01L2224/13005 , H01L2224/13006 , H01L2224/13009 , H01L2224/13014 , H01L2224/13017 , H01L2224/13018 , H01L2224/13021 , H01L2224/13022 , H01L2224/13025 , H01L2224/13076 , H01L2224/13082 , H01L2224/13083 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/14181 , H01L2224/16146 , H01L2224/16225 , H01L2224/16237 , H01L2224/17181 , H01L2224/2919 , H01L2224/2929 , H01L2224/293 , H01L2224/32145 , H01L2224/73104 , H01L2224/81191 , H01L2224/81203 , H01L2224/81815 , H01L2224/83102 , H01L2224/83191 , H01L2224/83192 , H01L2224/83193 , H01L2224/83856 , H01L2224/83862 , H01L2224/9205 , H01L2224/94 , H01L2225/06513 , H01L2225/06517 , H01L2225/06544 , H01L2225/06568 , H01L2924/01322 , H01L2924/12042 , H01L2924/15174 , H01L2924/181 , H01L2924/00014 , H01L2924/206 , H01L2224/11 , H01L2224/03 , H01L2924/00012 , H01L2924/01047 , H01L2924/0665 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which can improve electrical connection reliability.SOLUTION: A semiconductor chip 3 comprises: a semiconductor substrate 30 having through holes 30X penetrating between a first principal surface 30A and a second principal surface 30B; an insulation layer 31 formed so as to cover the second principal surface 30B of the semiconductor substrate 30 and having openings 31X at positions opposed to the through holes 30X, respectively; and through electrodes 32 formed on the through holes 30X and the openings 31X which are covered with an insulation film 33. Upper end faces of the through electrodes 32 exposed on the insulation layer 31 serve as pads when another semiconductor chip 4 is laminated on the semiconductor chip 3. The upper end faces of the through electrodes 32 are formed to be flush with a surface opposite to a surface contacting the semiconductor substrate 30 of the insulation layer 31.
摘要翻译：要解决的问题：提供一种可以提高电连接可靠性的半导体器件。解决方案：半导体芯片3包括：半导体衬底30，其具有穿过第一主表面30A和第二主表面30B之间的通孔30X; 形成为覆盖半导体衬底30的第二主表面30B并且在与通孔30X相对的位置处具有开口31X的绝缘层31; 并且通过形成在通孔30X上的电极32和被绝缘膜33覆盖的开口31X。暴露在绝缘层31上的贯通电极32的上端面在另一个半导体芯片4层叠在半导体上时用作焊盘贯通电极32的上端面形成为与与绝缘层31的半导体衬底30接触的表面相对的表面齐平。

6. 发明专利

JP2014523141A Electronic assembly including a die on a substrate having a heat spreader having an open window on the die 有权
公开(公告)号：JP2014523141A
公开(公告)日：2014-09-08
申请号：JP2014520275
申请日：2012-07-11
申请人：日本テキサス・インスツルメンツ株式会社 , テキサスインスツルメンツインコーポレイテッド
发明人：智横矢 , ローズシモンズマシューズマーガレット
IPC分类号： H01L23/34 , H01L23/12 , H01L23/32 , H01L23/36 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L23/36 , H01L23/4006 , H01L23/481 , H01L23/49827 , H01L23/50 , H01L25/0657 , H01L2224/0401 , H01L2224/05009 , H01L2224/06181 , H01L2224/13009 , H01L2224/73 , H01L2225/06517 , H01L2225/06541 , H01L2225/06548 , H01L2225/06572 , H01L2225/06589 , H01L2924/1461 , H01L2924/00
摘要：電子的アッセンブリ（１５０）が、ワークピース（１１０）、及び、基板（１０５）及び複数の基板貫通ビア（ＴＳＶ）（１１５）と、頂部側（１２１）と、その上にＴＳＶコネクタ（１１３）を有する底部側（１２２）とを含むＴＳＶダイ（１２０）を含む。ＴＳＶダイは、ワークピースに対してその頂部側でワークピース上に取り付けられる。内部開ウィンドウ（１３１）を有するヒートスプレッダ（１３０）が、ＴＳＶダイの底部側にある。ボンディング特徴（１６１）が、ＴＳＶコネクタに結合されるか又はＴＳＶコネクタ自体を含む。ボンディング特徴は、内部開ウィンドウから、ヒートスプレッダの頂部（１３２）の高さを上回る高さまで突出し、頂部ダイをそこにボンディングさせ得る。

7. 发明专利

JP2014013810A Substrate, manufacturing method for the same, semiconductor device and electronic apparatus 审中-公开
标题翻译：基板，其制造方法，半导体器件和电子设备
公开(公告)号：JP2014013810A
公开(公告)日：2014-01-23
申请号：JP2012150345
申请日：2012-07-04
申请人： Seiko Epson Corp , セイコーエプソン株式会社
发明人： YODA TAKESHI
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/12 , H01L23/522
CPC分类号： H01L23/481 , H01L21/76804 , H01L21/76898 , H01L2224/0401 , H01L2224/0557 , H01L2224/05572 , H01L2224/13009 , H01L2924/00014 , H05K1/024 , H01L2924/00012 , H01L2224/05552
摘要： PROBLEM TO BE SOLVED: To provide a substrate in which reliability of electrical and mechanical connection is improved.SOLUTION: A substrate, laminated structure, 10 includes: a first insulation layer 14 provided on a base substrate 12; a second insulation layer 15 provided on the first insulation layer 14; a third insulation layer 16 provided on the second insulation layer 15; and a pad electrode 17 provided on the third insulation layer 16. In the substrate 10, a hole that passes through the base substrate 12, the first insulation layer 14, the second insulation layer 15 and the third insulation layer 16 and reaches the pad electrode 17 from a second opposite side surface of the base substrate 12 is formed, and the substrate 10 has a fourth insulation layer 24 covering an inner wall of the hole and a conductor 32 that is connected to the pad electrode 17 and is covered with the fourth insulation layer 24 in the hole. A diameter of the first insulation layer 14 is larger than a diameter of the second insulation layer 15 in the hole. The first insulation layer 14 and the second insulation layer 15 are formed of different materials from each other, and the second insulation layer 15 and the third insulation layer 16 are formed of different materials from each other.
摘要翻译：要解决的问题：提供一种提高机电连接可靠性的基板。解决方案：基板层压结构10包括：设置在基底基板12上的第一绝缘层14; 设置在第一绝缘层14上的第二绝缘层15; 设置在第二绝缘层15上的第三绝缘层16; 以及设置在第三绝缘层16上的焊盘电极17.在基板10中，穿过基底12，第一绝缘层14，第二绝缘层15和第三绝缘层16并到达焊盘电极的孔形成从基底基板12的第二相对侧面的基板10，并且基板10具有覆盖孔的内壁的第四绝缘层24和连接到焊盘电极17并被第四绝缘层覆盖的导体32 绝缘层24在孔中。第一绝缘层14的直径大于孔中的第二绝缘层15的直径。第一绝缘层14和第二绝缘层15由彼此不同的材料形成，并且第二绝缘层15和第三绝缘层16由彼此不同的材料形成。

8. 发明专利

JP5389490B2 Method and apparatus for producing three-dimensional integrated circuit 有权
标题翻译：空值
公开(公告)号：JP5389490B2
公开(公告)日：2014-01-15
申请号：JP2009070769
申请日：2009-03-23
申请人：東京エレクトロン株式会社 , 国立大学法人東北大学
发明人：光正小柳 , 誉史福島 , 雅彦杉山
IPC分类号： H01L25/18 , H01L25/065 , H01L25/07
CPC分类号： H01L21/50 , H01L21/6835 , H01L21/76898 , H01L23/13 , H01L23/481 , H01L24/11 , H01L24/13 , H01L24/95 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L29/0657 , H01L2221/68318 , H01L2221/6834 , H01L2221/68354 , H01L2221/68368 , H01L2224/0401 , H01L2224/05008 , H01L2224/05009 , H01L2224/06182 , H01L2224/13009 , H01L2224/13025 , H01L2224/13099 , H01L2224/13109 , H01L2224/13111 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13184 , H01L2224/1403 , H01L2224/14181 , H01L2224/81193 , H01L2224/81801 , H01L2224/83005 , H01L2224/83143 , H01L2224/83193 , H01L2224/83896 , H01L2224/921 , H01L2224/95001 , H01L2224/95146 , H01L2225/06513 , H01L2225/06541 , H01L2924/0001 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/07802 , H01L2924/14 , H01L2924/15788 , Y10T156/1798 , H01L2924/00014 , H01L2924/00
摘要： There is provided a three-dimensional integrated circuit manufacturing method for temporarily attaching a chip to a transcription substrate, and securely detaching the chip from the transcription substrate when the chip is transferred to a supporting substrate. When a chip is temporarily attached to a transcription substrate, by evaporating a liquid existing between the chip and the transcription substrate, the solids of the chip and the transcription substrate can be attached to each other. Accordingly, the chip can be temporarily attached to the transcription substrate so as not to be deviated from its own position. Further, by setting adhesive strength between the chip and a supporting substrate to be higher than that between the chip and the transcription substrate, the chip can be securely detached from the transcription substrate when the chip is transferred from the transcription substrate to the supporting substrate.
摘要翻译：提供了一种用于将芯片临时附接到转录底物的三维集成电路制造方法，并且当芯片被转移到支撑衬底时，可靠地将芯片从转录衬底上分离。当芯片临时连接到转录底物时，通过蒸发芯片和转录底物之间的液体，芯片和转录底物的固体可以彼此附着。因此，芯片可以临时安装到转录基片上，以便不会偏离其本身的位置。此外，通过将芯片和支撑基板之间的粘合强度设定为高于芯片和转录基板之间的粘合强度，当芯片从转录基板转移到支撑基板时，可以将芯片从转录基板上牢固地分离。

9. 发明专利

JP2013187423A Semiconductor chip and manufacturing method of the same 审中-公开
标题翻译：半导体芯片及其制造方法
公开(公告)号：JP2013187423A
公开(公告)日：2013-09-19
申请号：JP2012052275
申请日：2012-03-08
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： MIYAZAKI TORU
IPC分类号： H01L21/60 , H01L21/3205 , H01L21/768 , H01L23/522
CPC分类号： H01L24/12 , H01L23/3128 , H01L23/3135 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/94 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/0557 , H01L2224/05572 , H01L2224/05644 , H01L2224/05647 , H01L2224/06181 , H01L2224/11462 , H01L2224/1181 , H01L2224/11849 , H01L2224/13009 , H01L2224/13082 , H01L2224/13083 , H01L2224/13111 , H01L2224/14181 , H01L2224/16146 , H01L2224/16225 , H01L2224/32245 , H01L2224/73253 , H01L2224/81815 , H01L2224/94 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/15311 , H01L2924/01028 , H01L2224/11 , H01L2224/03 , H01L2924/01047 , H01L2924/0103 , H01L2924/01083 , H01L2924/01029 , H01L2224/05552
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor chip which has an SnAg solder bump for TSV (Through Silicon Via) connection and which can achieve increase in melting point by Cu diffusion into the SnAg solder when stacking (connecting) the semiconductor chip while preventing Cu diffusion into the SnAg solder by reflow at the time of removing defects of the SnAg solder for TSV connection; and provide a manufacturing method of the semiconductor chip.SOLUTION: In a semiconductor chip 10 having a solder bump 16 for connection by a through-silicon via (TSV) technology, the solder bumps 16 is formed on a copper bump 13 on a TSV on a surface of the semiconductor chip 10 and composed of an alloy layer containing tin, silver and zinc.
摘要翻译：要解决的问题：提供一种具有用于TSV（通过硅通孔）连接的SnAg焊料凸块的半导体芯片，并且当堆叠（连接）半导体芯片同时防止Cu时，可以通过Cu扩散到SnAg焊料中来实现熔点的增加在去除用于TSV连接的SnAg焊料的缺陷时，通过回流扩散到SnAg焊料中; 并提供半导体芯片的制造方法。解决方案：在具有用于通过硅通孔（TSV）技术连接的焊料凸块16的半导体芯片10中，焊料凸块16形成在铜凸点13上，TSV上半导体芯片10的表面，由含有锡，银和锌的合金层构成。

10. 发明专利

JP5289830B2 Semiconductor device 有权
公开(公告)号：JP5289830B2
公开(公告)日：2013-09-11
申请号：JP2008149145
申请日：2008-06-06
申请人：ルネサスエレクトロニクス株式会社
发明人：信明高橋 , 雅宏小室 , 聡松井
IPC分类号： H01L23/522 , H01L21/3205 , H01L21/768 , H01L23/12
CPC分类号： H01L23/481 , H01L21/76898 , H01L24/11 , H01L24/13 , H01L2224/05571 , H01L2224/05573 , H01L2224/05624 , H01L2224/05684 , H01L2224/13009 , H01L2224/131 , H01L2224/13562 , H01L2224/1357 , H01L2224/13644 , H01L2224/13664 , H01L2224/17181 , H01L2924/00014

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