专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JPS61109141A Binary incrementer 失效
标题翻译：二进制器
公开(公告)号：JPS61109141A
公开(公告)日：1986-05-27
申请号：JP17779585
申请日：1985-08-14
申请人： Ibm
发明人： ABURAHAMU TORESU
IPC分类号： G06F7/50 , G06F7/505 , G06F7/508 , G06F9/32 , G06F12/00 , G06F12/02
CPC分类号： G06F7/5055 , G06F9/321

2. 发明专利

JP3916277B2 Read-only memory and computing device 失效
公开(公告)号：JP3916277B2
公开(公告)日：2007-05-16
申请号：JP34689796
申请日：1996-12-26
申请人：シャープ株式会社
发明人：洋二蟹江
IPC分类号： G06F17/14 , G11C16/02 , G06F7/48 , G06F7/50 , G06F7/505 , G06F7/52 , G06F7/523
CPC分类号： G06F7/5055 , G06F7/4824 , G06F7/523 , G06F17/147

3. 发明专利

JP3608970B2 Logic circuit 有权
公开(公告)号：JP3608970B2
公开(公告)日：2005-01-12
申请号：JP7058099
申请日：1999-03-16
申请人：富士通株式会社
发明人：康彦中島 , 洋片倉
IPC分类号： G06F7/50 , G06F7/02 , G06F7/42 , G06F7/501 , G06F7/505 , G06F7/506 , G06F7/508 , H03K17/693 , H03K19/0948 , H03K19/20
CPC分类号： G06F7/026 , G06F7/5055 , G06F7/506 , H03K17/693 , H03K19/20

4. 发明专利

JPS61138337A Counting circuit 失效
标题翻译：计数电路
公开(公告)号：JPS61138337A
公开(公告)日：1986-06-25
申请号：JP26022684
申请日：1984-12-10
申请人： Matsushita Electric Ind Co Ltd
发明人： TAKAGI SHINYA , SAKAMOTO HISAO
IPC分类号： H03K27/00 , G06F7/50 , G06F7/505 , G06F7/62
CPC分类号： G06F7/5055
摘要： PURPOSE:To attain the counting of many items with small circuit size by adding '1' to the output data of a read/write memory and storing the added result to the original address of the read/write memory. CONSTITUTION:An address generating circuit 4 outputs respective different addresses corresponding to respective items to be counted to an address bus 6 and simultaneously applies a trigger pulse 11 to a signal generating part 3. The signal generating part 3 set up a reading signal 10 to '1', the read/write memory 1 is turned to the reading status and inputs data stored in a specified address to an adding part 2 through a data bus and the adding part 2 adds '1' to the input data and outputs the added result to the bus 5. At that time, the memory 1 set up the reading signal 10 to '0' and the address generating part 4 continuously outputs the same address. If a writing signal 9 is set up to '1', the data on the bus 5 are stored in the same address of the memory 1. Thus, the contents stored in an address are counted up one by one every output of the data from the part 4.
摘要翻译：目的：通过向读/写存储器的输出数据添加“1”，将添加的结果存储到读/写存储器的原始地址，以达到小电路尺寸的多个项目的计数。构成：地址发生电路4将对应于要计数的各个项目的各个不同的地址输出到地址总线6，同时向信号产生部分3施加触发脉冲11.信号产生部分3将读取信号10设置为“ 1“，读/写存储器1转为读取状态，并通过数据总线将指定地址中存储的数据输入到加法部分2，加法部分2将”1“加到输入数据上，并输出相加结果此时，存储器1将读取信号10设置为“0”，并且地址生成部分4连续地输出相同的地址。如果写入信号9设置为“1”，则总线5上的数据被存储在存储器1的相同地址中。因此，存储在地址中的内容每个数据的输出逐个被逐个递增计数第4部分。

5. 发明专利

JPS5957343A High speed carrying system 失效
标题翻译：高速运输系统
公开(公告)号：JPS5957343A
公开(公告)日：1984-04-02
申请号：JP15400083
申请日：1983-08-23
申请人： Yokogawa Hewlett Packard Ltd
发明人： FUREDERITSUKU EI UEA
IPC分类号： G06F7/00 , G06F7/50 , G06F7/506 , G06F7/507 , G06F7/508 , G06F7/74
CPC分类号： G06F7/74 , G06F7/5055 , G06F7/508 , G06F2207/5063
摘要： PURPOSE: To attain high speed operation and cost reduction by connecting cells generating an intermediate carry signal in series for an adder, in a digital adder.
CONSTITUTION: Two ripple carry outputs Cout0(i) and Cout1(i) are generated in each block. A carry output Cout block (j) of the present block is generated by coupling the two carry outputs Cout to a carry input Cin block (j) inputted to the present block. In all blocks (j=0W2), two carry chins (Cout0-Cin0 and Cout1- Cin1) are propagated at the same time one after another. The block 0 generates first its carry output and propagates it to the block 1. Then only a delay for one stage of gate is required to skip each block by the carry.
COPYRIGHT: (C)1984,JPO&Japio
摘要翻译：目的：通过在数字加法器中连接产生中间进位信号的单元串联加法器来实现高速运算和降低成本。构成：在每个块中产生两个纹波进位输出Cout0（i）和Cout1（i）。通过将两个进位输出Cout耦合到输入到当前块的进位输入Cin块（j）来生成本块的进位输出Cout块（j）。在所有块（j = 0-2）中，两个进位下巴（Cout0-Cin0和Cout1-Cin1）一个接一个地同时传播。块0首先产生其进位输出并将其传播到块1.然后仅需要一级门的延迟来通过进位来跳过每个块。

7. 发明专利

JP4204482B2 Incrementor and method that can be fast calculated at zero detection 有权
公开(公告)号：JP4204482B2
公开(公告)日：2009-01-07
申请号：JP2004000578
申请日：2004-01-05
申请人：三星電子株式会社Samsung Electronics Co.,Ltd.
发明人：ヨハン権
IPC分类号： H03K19/21 , G06F7/38 , G06F7/50 , G06F7/505
CPC分类号： G06F7/5055

8. 发明专利

JP2004242292A Fast incrementer using zero detection, and increment method thereof 有权
公开(公告)号：JP2004242292A
公开(公告)日：2004-08-26
申请号：JP2004000578
申请日：2004-01-05
申请人： Samsung Electronics Co Ltd , 三星電子株式会社
发明人： KWON YO-HAN
IPC分类号： H03K19/21 , G06F7/38 , G06F7/50 , G06F7/505
CPC分类号： G06F7/5055
摘要： PROBLEM TO BE SOLVED: To provide a fast incrementer using zero detection, and an increment method thereof. SOLUTION: The incrementer performs a logic combination on an operand, first logic state inclusion information for each 4-bit group of the operand, flag information for each 4-bit group of the operand and a specified increment value, and generates the whole increment value by outputting 4 bits of the first logic state for each 4-bit group, 4 bits of the operand for each 4-bit group or 4 bits of the specified increment value for each 4-bit group. An exemplary embodiment of the present invention provides a fast incrementer having a simple logic circuit for zero detection with an MUX structure, which is capable of performing speedy calculation and occupies a small area of a microprocessor chip. COPYRIGHT: (C)2004,JPO&NCIPI

9. 发明专利

JPS57121736A Multiinput adder 失效
标题翻译： MULTIINPUT ADDER
公开(公告)号：JPS57121736A
公开(公告)日：1982-07-29
申请号：JP646581
申请日：1981-01-21
申请人： Nec Corp , Nippon Telegr & Teleph Corp
发明人： NIKAIDOU TADANOBU , NAKASHIMA TAKATOSHI , YAMAUCHI HIROKI , SATOU FUMIHIKO
IPC分类号： G06F7/509 , G06F7/50 , G06F7/505 , G06F7/508
CPC分类号： G06F7/5055
摘要： PURPOSE:To decrease the quantity of hardware required for adding a code extension term, by adding inverted information of each code bit, and a fixed data ''1'' instead of adding a code bit as it is as the code extension term. CONSTITUTION:All adders 2-7, 10, 11 and 14 add information inputted to input terminals 1, 2 and 3, and output the sum and the carry to an output terminal 4 and an output terminal 5, respectively. Also, half-adders 1, 8, 9, 12 and 13 add information inputted to input terminals 1, 2, and output the sum and the carry to the output terminal 4 and the output terminal 5, respectively. Subsequently, in each digit extending from the lowest digit of each code bit to the highest digit, in 4 binary numbers, ''1'' is supplied to 2 , 2 and 2 being digits except those which have a code bit, that is to say, 2 , 2 , 2 and 2 , and also to the lowest digit among the digits having a code bit, that is to say, 2 , as addition data.
摘要翻译：目的：减少添加代码扩展项所需的硬件数量，通过添加每个代码位的反相信息和固定数据“1”，而不是像代码扩展项一样添加代码位。构成：所有加法器2-7,10,11和14都添加输入到输入端子1,2和3的信息，并将和值和进位输出分别输出到输出端子4和输出端子5。此外，半加法器1,8,9,12和13添加输入到输入端子1,2的信息，并且将和和输入分别输出到输出端子4和输出端子5。随后，在从每个码位的最低位延伸到最高位的每个数字中，以4个二进制数字，“2”被提供给2 <3>，2 <4>和2 <7>是除了那些它们具有代码位，也就是说2 2，2 5，2 6和2 8，并且还具有代码位的数字中的最低位，也就是说， 2 <2>，作为附加数据。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式