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1. 发明专利

JP2007188931A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2007188931A
公开(公告)日：2007-07-26
申请号：JP2006003437
申请日：2006-01-11
申请人： Toshiba Corp , 株式会社東芝
发明人： TOMONO MORIYASU
IPC分类号： H01L21/822 , G01R31/28 , H01L21/66 , H01L27/04
CPC分类号： G01R31/31713 , G01R31/31721 , H01L24/06 , H01L2224/05554 , H01L2924/14 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which can withstand plural wafer test steps. SOLUTION: The semiconductor device is provided with a test objective circuit 1, a test non-objective circuit 2, a first pad group to be used for the test objective circuit 1, and a second pad group to be used for the test non-objective circuit 2. The first pad group includes at least a plurality of divided pads, and the second pad group is comprised of one pad, respectively. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种可以承受多个晶片测试步骤的半导体器件。
解决方案：半导体器件设置有测试对象电路1，测试非对象电路2，用于测试对象电路1的第一焊盘组和用于测试的第二焊盘组非目标电路2.第一焊盘组包括至少多个划分的焊盘，并且第二焊盘组分别由一个焊盘组成。版权所有（C）2007，JPO＆INPIT

2. 发明专利

JPH06342374A METHOD AND DEVICE FOR INTERRUPTION CONTROL OF MICROCOMPUTER 失效
公开(公告)号：JPH06342374A
公开(公告)日：1994-12-13
申请号：JP12970793
申请日：1993-05-31
申请人： TOSHIBA CORP
发明人： TOMONO MORIYASU
IPC分类号： G06F9/48 , G06F9/46
摘要： PURPOSE:To set an optional address of a program memory as an entry by switching the readout destination of the entry address to a 2nd storage means for copying when a 2nd or succeeding interruption is accepted from the same interruption factor. CONSTITUTION:This device is provided with a 1st storage means 103 which has a vector table 103A, etc., and a 2nd storage element 104 Which has dedicated memories, etc., corresponding to respective vectors. When each interruption factor is accepted for the 1st time, the entry address which is read out of the storage element 103 is copied to the storage element 104 and when the same factor is accepted next time, the entry read destination is switched to the storage element 104. The storage element 103 sets the optional address as the entry address. Entry addresses are read out of the storage element 104 at a time except in an initial entry read and a return address is stored in a stack. Consequently, the read time for the entry address at the time of interruption acceptance increases only in the 1st read.

3. 发明专利

JPH07182850A SEMICONDUCTOR STORAGE 失效
公开(公告)号：JPH07182850A
公开(公告)日：1995-07-21
申请号：JP32489593
申请日：1993-12-22
申请人： TOSHIBA CORP
发明人： TOMONO MORIYASU , MORITA KAZUHIKO
IPC分类号： G11C11/401 , G11C11/413
摘要： PURPOSE:To enable data field access without sacrificing a speed and a circuit scale like read modify write and bit field operation instructions. CONSTITUTION:A row address where a memory cell becoming an access object in a memory cell array 1 exists is set by a row address signal, and a column address is set by a column address signal, and further, the matter that any bit field in one word is accessed is specified by a mode address signal. That is, the mode address signal makes a circuit corresponding to the bit field becoming the access object in gate circuits 47-40 an open state. Then, only the bit field becoming the access object in the specified words is activated by the row and column address signals, and the read out/write access is executed through data input/output buffers 87-80 and input/output circuits 227-220 related to the memory cell of the word.

4. 发明专利

JPS6174419A Method and apparatus for data storage 失效
标题翻译：数据存储的方法和装置
公开(公告)号：JPS6174419A
公开(公告)日：1986-04-16
申请号：JP19707084
申请日：1984-09-20
申请人： Toshiba Corp
发明人： TOMONO MORIYASU , HIRAO SHIGEHARU
IPC分类号： G06F12/06 , G06F12/04 , G11C7/00 , H03M7/12 , H03M7/30
摘要： PURPOSE: To decrease the waste in a memory capacity by dividing data BCD at each prescribed digit when inverting and compressing a binary decimal data BCD into a binary data BIN and writing the result in a memory while applying inversion to reproduce the BCD into the BIN.
CONSTITUTION: An input latch circuit 1 divides an input data into, e.g., (n), in 3-digit 12-bit binary data BCD. The n-division data BCD is converted into a binary data BIN by compression circuits 4
1 ∼4
n respectively, in this case, into 10-bit. The n-set of data BIN (10-bit) is converted into n-set of BCD data by restoration circuits 5
1 ∼5
n , where 10-bit is restored into 12-bit. Then the restored n-set data BCD is coupled in an output latch circuit 3 and extracted as a decimal output data.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：通过在将二进制十进制数据BCD反相并将二进制十进制数据BCD压缩为二进制数据BIN并将结果写入存储器中并将结果写入存储器中以将BCD再现到BIN中时，通过在每个规定数字处划分数据BCD来减少存储器容量中的浪费。构成：输入锁存电路1将输入数据划分为例如（n）的3位12位二进制数据BCD。在这种情况下，分割数据BCD被分别由压缩电路41-4n转换成二进制数据BIN为10位。数据BIN（10位）的n组由恢复电路51-5n转换为n组BCD数据，其中10位恢复为12位。然后将恢复的n组数据BCD耦合在输出锁存电路3中并提取为十进制输出数据。

5. 发明专利

JP2003196084A SYSTEM HAVING READ MODIFYING WRITE UNIT 审中-公开
公开(公告)号：JP2003196084A
公开(公告)日：2003-07-11
申请号：JP2001391671
申请日：2001-12-25
申请人： TOSHIBA CORP
发明人： TOMONO MORIYASU
IPC分类号： G06F9/30 , G06F9/308 , G06F9/312 , G06F9/34 , G06F9/38 , G06F12/00 , G06F12/04
摘要： PROBLEM TO BE SOLVED: To improve throughput by processing a succeeding CPU command in parallel to read modifying write processing. SOLUTION: A processor has a CPU 1 for executing the command, a memory 2 for storing information, a BIU 3 for starting a read bus cycle, a write bus cycle, and a dummy bus cycle of none of these for the memory with the memory, and an RMWU 10 between the CPU 1 and the BIU 3. The RMWU ha a storage means 12 for storing a modifying condition outputted from the CPU 1, a means 13 for forming modifying data on the basis of this modifying condition, a storage means 14 for storing read data outputted from the BIU 3, an arithmetic operation means 15 for executing a modifying operation according to an arithmetic operation control signal on the basis of the read data from this storage means 14 and the modifying data from the modifying data forming means 13, and a storage means 17 for storing write data determined from write data from the CPU 1 and an arithmetic operation result of the arithmetic operation means 15. COPYRIGHT: (C)2003,JPO

6. 发明专利

JPH1115675A INTERRUPTION CONTROLLER AND CONTROL SYSTEM 失效
公开(公告)号：JPH1115675A
公开(公告)日：1999-01-22
申请号：JP16453897
申请日：1997-06-20
申请人： TOSHIBA CORP
发明人： MIYAKE MASAKAZU , WATANABE HIROYUKI , TOMONO MORIYASU
IPC分类号： G06F9/46 , G06F9/48 , G06F13/24 , G06F13/26
摘要： PROBLEM TO BE SOLVED: To improve interruption responsiveness and the flexibility of processing by reading the leading address of an interruption program from a vector holding part and outputting a vector access signal to outside. SOLUTION: At an interruption controller 10, an interruption request receiving part 11 receives plural interruption request signals #1 to #n and according to an activated interruption request signal, an interruption level signal 11A given priority (level) concerning interruption processing with respect to CPU 20 is outputted to CPU 20. A vector holding part 12 is connected with CPU 20 through a bus 30 and at the time of starting the interruption program by CPU 20, the leading address of the interruption-program corresponding to the received interruption request to CPU 20 through the bus 30. Then, at the same time of outputting a vector to the bus 30, a vector access signal 12A showing that the vector is read out is outputted to CPU 20.

7. 发明专利

JPH02130640A MICROCOMPUTER AND EVALUATOR CHIP, AND EMULATOR USING THEM 失效
公开(公告)号：JPH02130640A
公开(公告)日：1990-05-18
申请号：JP28543588
申请日：1988-11-11
申请人： TOSHIBA CORP
发明人： TOMONO MORIYASU , KOBAYASHI ATSUSHI
IPC分类号： G06F11/22 , G06F9/44 , H01L27/00
摘要： PURPOSE:To easily execute emulation by controlling a peculiar input/output port and a peripheral hardware according to a signal which is inputted from an external part through an interface terminal. CONSTITUTION:In an emulation mode, a CPU31 stops operation or stops the direct control of the peripheral hardware and a peculiar input/output port 33. Then, a common input/output port 33 is switched to an interface 34a. The peculiar input/output port 33 and a peripheral hardware 35 are controlled regardless of the CPU31 by the signal to be inputted from the external part through the interface 34a. The CPU31 of an evaluation chip executes the control of the peripheral hardware 35 and peculiar input/output port 33 through the interface terminal according to a program. Thus, the emulation of a computer 1 can be easily executed.

8. 发明专利

JP2001222426A INSTRUCTION CODE CONVERTING DEVICE AND INFORMATION PROCESSING SYSTEM AND INSTRUCTION CODE GENERATING METHOD 失效
公开(公告)号：JP2001222426A
公开(公告)日：2001-08-17
申请号：JP2000030948
申请日：2000-02-08
申请人： TOSHIBA CORP
发明人： TOMONO MORIYASU , SHODA TOMOAKI , ITAYA HIROSHI , SAITO TOMOTAKA
IPC分类号： G06F9/32 , G06F9/318
摘要： PROBLEM TO BE SOLVED: To reduce the capacity of a program memory for storing instruction by realizing the addition of the instruction without newly designing/altering a CPU, thereby improving code efficiency. SOLUTION: An address for accessing a compression instruction code is generated by shift-operating the address given from the outside part, and the compression instruction code accessed based on the address is expanded and converted into a non-compression instruction code corresponding to the compression instruction code.

9. 发明专利

JPH07191830A ARITHMETIC UNIT 失效
公开(公告)号：JPH07191830A
公开(公告)日：1995-07-28
申请号：JP32950593
申请日：1993-12-27
申请人： TOSHIBA CORP
发明人： TOMONO MORIYASU
IPC分类号： G06F7/505 , G06F7/50 , G06F7/507 , G06F7/57
摘要： PURPOSE:To provide the arithmetic unit which can parallelly execute plural kinds of arithmetic and can shorten arithmetic processing time. CONSTITUTION:Arithmetic data to be transferred through data buses d1L, d2L, D1H and d2H are divided and the divided data are parallelly and independently calculated by respectively different arithmetic circuits aL1 and aH2 or when the result of preceding arithmetic is required for following arithmetic, the arithmetic data of following arithmetic excepting for the result of preceding arithmetic are previously applied from registers R1-R4 to temporary registers xL3, yL4, xH5 and YH16 and prepared before the start of arithmetic.

10. 发明专利

JPS61139845A Arithmetic processor 失效
标题翻译：算术处理器
公开(公告)号：JPS61139845A
公开(公告)日：1986-06-27
申请号：JP26330784
申请日：1984-12-13
申请人： Toshiba Corp
发明人： TOMONO MORIYASU
IPC分类号： G06F11/00
CPC分类号： G06F11/0763
摘要： PURPOSE:To detect the runaway and the abnormal state of an external device in a wide range by providing the first flag whose state is changed in accordance with an input signal and the second flag whose state is changed when in accordance with the state of this first flag or the execution of a specific instruction. CONSTITUTION:A runaway/abnormality detecting circuit 37 consists of an input buffer 41 to which the signal inputted to a state input terminal 39 is supplied, a flag register 42 whose state is controlled in accordance with the output signal of the input buffer 41, a flag register 43 whose state is controlled by set and rest instructions, and an OR gate 44. The runaway of a microcomputer itself or the abnormal state of an external device 38 is detected on a basis of a control signal outputted from an instruction decoder 33 the reset signal outputted from a reset generator 36, and a signal corresponding to the operation state of the external device 38, and the detection signal is supplied to the reset generator 36 to initialize the operation as a system.
摘要翻译：目的：通过根据输入信号提供其状态改变的第一标志和状态根据该第一个状态的状态而改变的第二标志来检测在宽范围内的外部设备的失控和异常状态标志或执行特定指令。构成：失控/异常检测电路37包括输入到状态输入端子39的信号的输入缓冲器41，根据输入缓冲器41的输出信号控制其状态的标志寄存器42，标志寄存器43，其状态由设定和休息指令控制，以及或门44.微处理器本身的失控或外部设备38的异常状态是根据从指令解码器33输出的控制信号来检测的从复位发生器36输出的复位信号和对应于外部设备38的操作状态的信号，并且检测信号被提供给复位发生器36以初始化作为系统的操作。

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