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1. 发明专利

JP2013182961A Semiconductor manufacturing device and method of manufacturing semiconductor device 审中-公开
标题翻译：半导体制造装置及制造半导体器件的方法
公开(公告)号：JP2013182961A
公开(公告)日：2013-09-12
申请号：JP2012044803
申请日：2012-02-29
申请人： Toshiba Corp , 株式会社東芝
发明人： SASAKI HIROYUKI , MATSUYAMA HIDETO
IPC分类号： H01L21/285 , C23C16/08 , C23C16/455 , C23C16/507 , C23C16/509 , H01L21/28
CPC分类号： H01L21/02274 , C23C16/0263 , C23C16/0281 , C23C16/14 , C23C28/023 , H01L21/28512 , H01L21/32051
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor manufacturing device capable of forming a low-resistance tungsten film without being subject to the restriction of an underlayer material, and a method of manufacturing a semiconductor device including the tungsten film.SOLUTION: There is provided a semiconductor manufacturing device capable of forming a metal film, comprising: a processing chamber including a substrate provided inside and capable of performing processing; a gas supply part configured to supply a raw material gas of the metal film and a plasma generation gas to an inside of the processing chamber; a plasma generation part configured to generate a plasma of the plasma generation gas; and a bias generation part configured to cause ions generated by the plasma generation part to collide with the substrate.
摘要翻译：要解决的问题：提供能够形成低电阻钨膜而不受限于下层材料的半导体制造装置，以及制造包括钨膜的半导体器件的方法。解决方案：提供一种能够形成金属膜的半导体制造装置，包括：处理室，包括内部设置并能够进行处理的基板; 气体供给部，其构造为将所述金属膜的原料气体和等离子体产生气体供给到所述处理室的内部; 等离子体产生部件，被配置为产生等离子体产生气体的等离子体; 以及偏置产生部，被配置为使由等离子体产生部生成的离子与基板碰撞。

2. 发明专利

JP2010251572A Nonvolatile semiconductor storage device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2010251572A
公开(公告)日：2010-11-04
申请号：JP2009100339
申请日：2009-04-16
申请人： Toshiba Corp , 株式会社東芝
发明人： YAMASHITA SAYAKO , NAKAUCHI TAKAHIRO , SASAKI HIROYUKI , IRIE MASASHI , KIKUCHI NATSUKI
IPC分类号： H01L21/8247 , G11C16/04 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device of a charge-trap flash structure which makes a memory cell into a high integration degree.
SOLUTION: In the semiconductor storage device 50, a plurality of opening parts 5 where an element separation layer 2, a source electrode 3a, a source electrode 3b, a drain electrode 4a and a drain electrode 4b are etched and opened in pillar shapes are separately arranged on a first main face (surface) of a semiconductor substrate layer 1a as a ground line SUBL. A semiconductor substrate layer 1b, a laminated film 6 and a gate electrode 7 are buried in the opening part 5. The semiconductor substrate layer 1b is arranged on an inner side of the opening part 5 so that it is brought into contact with the semiconductor substrate layer 1a. The laminated film 6 formed of a tunnel oxide film, a charge accumulation film and a current interruption film is arranged on an inner side of the semiconductor substrate layer 1b. A gate electrode 7 is buried on an inner side of the laminated film 6. A memory transistor where a plurality of source layers 8 and drain layers 9 are arranged in the semiconductor substrate layer 1b in a vertical direction, and a channel is disposed in the vertical direction is laminated and formed.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：解决的问题：提供使存储单元成为高集成度的电荷捕捉闪存结构的非易失性半导体存储装置。解决方案：在半导体存储装置50中，将元件分离层2，源电极3a，源极电极3b，漏电极4a和漏极电极4b的多个开口部5蚀刻并在柱上打开形状分别设置在作为接地线SUBL的半导体衬底层1a的第一主面（表面）上。半导体衬底层1b，层叠膜6和栅极电极7被埋在开口部5中。半导体衬底层1b布置在开口部5的内侧，使其与半导体衬底接触层1a。由半导体衬底层1b的内侧设置由隧道氧化膜，电荷蓄积膜和电流中断膜形成的层叠膜6。栅极电极7埋设在层叠膜6的内侧。在半导体衬底层1b中沿垂直方向布置有多个源极层8和漏极层9的存储晶体管，并且沟道布置在垂直方向被层压并形成。版权所有（C）2011，JPO＆INPIT

3. 发明专利

JP2008177483A Semiconductor device and manufacturing method therefor 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2008177483A
公开(公告)日：2008-07-31
申请号：JP2007011504
申请日：2007-01-22
申请人： Toshiba Corp , 株式会社東芝
发明人： SONODA MASAHISA , SASAKI HIROYUKI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To suppress interferences among adjacent memory cells.
SOLUTION: A dummy contact UC is provided between drain contacts DC adjacent in X direction. Then, the data-holding characteristics of memory cell transistors Tm1 and Tm2 mutually adjacent and interposing the drain contacts DC in Y direction can be maintained, thereby interference between the memory cell transistors Tm1 and Tm2 can be suppressed.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：抑制相邻存储单元之间的干扰。解决方案：在X方向相邻的漏极接触DC之间提供虚拟接触UC。然后，可以维持相互相邻并且将漏极触点DC置于Y方向上的存储单元晶体管Tm1和Tm2的数据保持特性，从而可以抑制存储单元晶体管Tm1和Tm2之间的干扰。版权所有（C）2008，JPO＆INPIT

4. 发明专利

JP2006099912A Nonvolatile semiconductor memory apparatus and its data erasing method 有权
标题翻译：非易失性半导体存储器及其数据擦除方法
公开(公告)号：JP2006099912A
公开(公告)日：2006-04-13
申请号：JP2004287700
申请日：2004-09-30
申请人： Toshiba Corp , 株式会社東芝
发明人： WATABE HIROSHI , KATO HIDEO , KASAI TAKAMICHI , NARUGE KIYOMI , SASAKI HIROYUKI
IPC分类号： G11C16/02 , G11C16/04
CPC分类号： G11C16/3404
摘要： PROBLEM TO BE SOLVED: To provide a data erasing method of a nonvolatile semiconductor memory apparatus in which the occurrence of an infinitive loop in which erasure and write-in are repeated at the time of erasing data can be prevented and a products defect rate can be reduced. SOLUTION: Write-in is performed by applying voltage to a plurality of memory cells and write, a threshold value of the plurality of memory cells is set to voltage PV or more, after that, erasing is performed en bloc for the plurality of memory cells, the threshold value of the plurality of memory cells is set to voltage EV or less. Voltage being lower than voltage applied in the write-in is applied to each of memory cells having a lower threshold value than voltage OEV out of the plurality of memory cells, weak write-in is performed only once. Next, weak write-in is repeated until the threshold value becomes voltage OEV or more for memory cells having a lower threshold value than voltage OEV out of the plurality of memory cells. After that, when memory cells having higher value than voltage EV exist in the plurality of memory cells, operation is returned to operation in which the threshold value of the plurality of memory cells is set to voltage EV or less. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种非易失性半导体存储装置的数据擦除方法，其中可以防止在擦除数据时重复擦除和写入的不定期循环的出现以及产品缺陷率可以降低。解决方案：通过向多个存储单元施加电压并进行写入来执行写入，将多个存储单元的阈值设置为电压PV以上，之后，针对多个存储单元执行擦除的多个存储单元的阈值被设定为电压EV以下。低于写入时施加的电压的电压被施加到具有比多个存储器单元中的电压OEV低的阈值的每个存储器单元，弱写入仅执行一次。接下来，重复弱写入，直到阈值变为具有比多个存储器单元中的电压OEV低的阈值的存储单元的电压OEV或更多。此后，当多个存储单元中存在具有比电压EV高的值的存储单元时，操作返回到多个存储单元的阈值被设置为电压EV或更小的操作。版权所有（C）2006，JPO＆NCIPI

5. 发明专利

JPH05303096A 失效
公开(公告)号：JPH05303096A
公开(公告)日：1993-11-16
申请号：JP10774592
申请日：1992-04-27
申请人： TOSHIBA CORP , TOSHIBA ELECTRONIC ENG
发明人： KURAMOCHI OSAMU , SASAKI HIROYUKI
IPC分类号： G02F1/1337
摘要： PURPOSE:To enable the formation of uniform oriented films on electrodes having level differences by subjecting the level differences between the electrodes to an operation to fill the level differences to smooth the surfaces thereof, then forming the oriented films. CONSTITUTION:The transparent conductive electrodes 3, 4 consisting of, for example, ITO(indium tin oxide) are formed on the respective one main surface 1a, 2a side of a first substrate 1 and second substrate 2 which are glass substrates. The oriented films 5, 6 are respectively so formed as to cover these ITO electrodes 3, 4. Printing and baking of PI (polyimide) are first executed in the parts of the level differences 6a formed by the ITO patterns to bury the level differences 6a. After the level differences 6 are annihilated in such a manner, the printing and baking of the PI are executed again to form the oriented films 5, 6 having no level differences on the ITO electrodes 3, 4. As a result, the oriented films 5, 6 of the PI having a uniform film thickness are formed on the ITO electrodes 3, 4 having the level differences 6a and, therefore, the electrostatic breakdown thereof is prevented.

6. 发明专利

JPH0563208A NONVOLATILE SEMICONDUCTOR MEMORY AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH0563208A
公开(公告)日：1993-03-12
申请号：JP1239892
申请日：1992-01-27
申请人： TOSHIBA CORP
发明人： ARAKI HITOSHI , SASAKI HIROYUKI , KANEBAKO KAZUNORI
IPC分类号： H01L21/316 , H01L21/314 , H01L21/318 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PURPOSE:To provide a nonvolatile semiconductor memory having higher reliability concerning its charge holding characteristic and its manufacturing method. CONSTITUTION:A memory cell 100 is formed in the main surface region of a semiconductor board 10. An insulating film 26 between layers is formed on the board 10 so as to cover the memory cell 10. And a hole 28 is formed in the insulating film 26 up to the memory cell 100. an internal wiring layer 30 is electrically connected to the memory cell 100 through the hole 28. A protective film 32 is formed on the insulating film 26 so as to cover the internal wiring layer 30. And the protective film 32 is made out of material containing at least silicon and oxygen, and its refractive index is set in a range of 1.48 to 1.65. In this way, the protective film has a high screening effect on moving ions, water, etc., and makes it possible to increase the charge holding characteristic of the memory.

7. 发明专利

JP2010225806A NONVOLATILE SEMICONDUCTOR STORAGE DEVICE 审中-公开
公开(公告)号：JP2010225806A
公开(公告)日：2010-10-07
申请号：JP2009070824
申请日：2009-03-23
申请人： TOSHIBA CORP
发明人： NAKAUCHI TAKAHIRO , KIKUCHI NATSUKI , SASAKI HIROYUKI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device having a structure suitable for miniaturization. SOLUTION: The nonvolatile semiconductor storage device includes memory transistors 18 each including: a second conductivity-type first impurity diffusion layer 12 formed in a semiconductor substrate 11 along a bottom surface 11c within an inner surface 11b of the semiconductor substrate 11; a second conductivity-type second impurity diffusion layer 13 formed on a principal surface 11a of the semiconductor substrate 11 along a side surface 11d; a first gate electrode 15 formed on the side surface 11d through a first insulating film 14 formed on the inner surface 11b and reaching the principal surface 11a from the bottom surface 11c; and a second gate electrode 17 formed on the first gate electrode 15 through a second insulating film 16 and reaching the principal surface 11a from the bottom surface 11c, wherein a first side surface 11d1 on the first impurity diffusion layer 12 side and a second side surface 11d2 on the second impurity diffusion layer 13 side within the side surface 11d are located on different planes, and the second side surface 11d2 is located at a deeper position than the first side surface 11d1 in the depth direction of a channel 19 formed along the side surface 11d. COPYRIGHT: (C)2011,JPO&INPIT

8. 发明专利

JP2000200839A SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JP2000200839A
公开(公告)日：2000-07-18
申请号：JP37738398
申请日：1998-12-28
申请人： TOSHIBA CORP
发明人： SASAKI HIROYUKI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor memory device and a manufacturing method thereof, where the memory device is high in W/E(writing/erasing) reliability, and the source diffusion layer of a memory cell is protected against damage when a source wiring is formed in a self-aligned manner. SOLUTION: A semiconductor memory device is equipped with an element isolating insulating film 112 formed on the surface of a substrate, a plurality of memory cells which are each provided with a source diffusion layer 102 formed in a region isolated by the element isolation insulating film 112, and a wiring layer 113 which interconnects the source diffusion layers 102 of the memory cells adjacent to each other interposing the element isolation insulating film 112 between them is provided under the element isolation insulating film 112. In the manufacturing method of this semiconductor memory device, a source wiring layer is formed under a field oxide film by implantation of ions with a high acceleration energy without a field oxide film removing process. Therefore, the memory cell can be protected against damage caused by etching of an oxide film, so that a semiconductor non-volatile memory excellent in characteristics can be obtained.

9. 发明专利

JPS61134581A Heating furnace 失效
公开(公告)号：JPS61134581A
公开(公告)日：1986-06-21
申请号：JP25792184
申请日：1984-12-06
申请人： Toshiba Corp
发明人： NISHIMUTA TERUO , SASAKI HIROYUKI
IPC分类号： F27B9/36 , F27B9/06

10. 发明专利

JPH08102531A SEMICONDUCTOR STORAGE DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH08102531A
公开(公告)日：1996-04-16
申请号：JP23808494
申请日：1994-09-30
申请人： TOSHIBA CORP
发明人： SASAKI HIROYUKI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PURPOSE: To provide a semiconductor device which can prevent the deterioration of cell characteristic caused by insulation film etching and its manufacturing method. CONSTITUTION: In a semiconductor storage device with a memory cell of two- layer gate structure, a diffusion layer 7 as a wiring layer for mutually connecting each source diffusion layer 13 of memory cells which are adjacent to each other with an insulation film 8 for isolation therebetween is an impurity diffusion layer of the same conductivity as the source layer 13 and is formed below the insulation layer 8. In a manufacturing method of the above semiconductor memory, the diffusion layer 7 as a wiring layer is formed before the formation of the insulation film 8 and the insulation film 8 is formed on the diffusion layer 7. Thereafter, a control gate 12 is formed and a source diffusion layer 13 is formed by ion implantation using it as a mask.

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