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1. 发明专利

JP2010251572A Nonvolatile semiconductor storage device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2010251572A
公开(公告)日：2010-11-04
申请号：JP2009100339
申请日：2009-04-16
申请人： Toshiba Corp , 株式会社東芝
发明人： YAMASHITA SAYAKO , NAKAUCHI TAKAHIRO , SASAKI HIROYUKI , IRIE MASASHI , KIKUCHI NATSUKI
IPC分类号： H01L21/8247 , G11C16/04 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device of a charge-trap flash structure which makes a memory cell into a high integration degree.
SOLUTION: In the semiconductor storage device 50, a plurality of opening parts 5 where an element separation layer 2, a source electrode 3a, a source electrode 3b, a drain electrode 4a and a drain electrode 4b are etched and opened in pillar shapes are separately arranged on a first main face (surface) of a semiconductor substrate layer 1a as a ground line SUBL. A semiconductor substrate layer 1b, a laminated film 6 and a gate electrode 7 are buried in the opening part 5. The semiconductor substrate layer 1b is arranged on an inner side of the opening part 5 so that it is brought into contact with the semiconductor substrate layer 1a. The laminated film 6 formed of a tunnel oxide film, a charge accumulation film and a current interruption film is arranged on an inner side of the semiconductor substrate layer 1b. A gate electrode 7 is buried on an inner side of the laminated film 6. A memory transistor where a plurality of source layers 8 and drain layers 9 are arranged in the semiconductor substrate layer 1b in a vertical direction, and a channel is disposed in the vertical direction is laminated and formed.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：解决的问题：提供使存储单元成为高集成度的电荷捕捉闪存结构的非易失性半导体存储装置。解决方案：在半导体存储装置50中，将元件分离层2，源电极3a，源极电极3b，漏电极4a和漏极电极4b的多个开口部5蚀刻并在柱上打开形状分别设置在作为接地线SUBL的半导体衬底层1a的第一主面（表面）上。半导体衬底层1b，层叠膜6和栅极电极7被埋在开口部5中。半导体衬底层1b布置在开口部5的内侧，使其与半导体衬底接触层1a。由半导体衬底层1b的内侧设置由隧道氧化膜，电荷蓄积膜和电流中断膜形成的层叠膜6。栅极电极7埋设在层叠膜6的内侧。在半导体衬底层1b中沿垂直方向布置有多个源极层8和漏极层9的存储晶体管，并且沟道布置在垂直方向被层压并形成。版权所有（C）2011，JPO＆INPIT

2. 发明专利

JP2012069178A Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2012069178A
公开(公告)日：2012-04-05
申请号：JP2010210962
申请日：2010-09-21
申请人： Toshiba Corp , 株式会社東芝
发明人： MINEMURA YOICHI , TSUKAMOTO TAKAYUKI , SHIMOTORI TAKAFUMI , SUGANO YUJI , KIKUCHI NATSUKI , SATO MITSURU
IPC分类号： G11C13/00 , H01L27/10 , H01L27/105 , H01L45/00 , H01L49/00
CPC分类号： G11C5/063 , G11C13/0004 , G11C13/0007 , G11C13/0023 , G11C13/0069 , G11C29/025 , G11C29/028 , G11C2013/0083 , G11C2213/71
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device having a large number of writable times and high reliability.SOLUTION: A nonvolatile semiconductor memory device includes: a memory cell array including multiple first wires, multiple second wires which intersect with the multiple first wires, and multiple memory cells arranged at respective intersecting parts of the multiple first and second wires and each having an electrically re-writable variable resistive element which stores a resistance value as data in a nonvolatile manner; a first decoder connected to at least one end of the multiple first wires and selecting the first wire; at least a pair of second decoders connected to both ends of the multiple second wires and each of which selects the second wire in accordance with a distance between the first wire selected by the first decoder and each of the both ends of the multiple second wires; and a voltage application circuit applying a predetermined voltage to between the first wire and the second wire which are selected by the first decoder and the second decoder.
摘要翻译：要解决的问题：提供具有大量可写入时间和高可靠性的非易失性半导体存储器件。解决方案：非易失性半导体存储器件包括：存储单元阵列，包括多个第一布线，与多个第一布线相交的多条第二布线，以及布置在多条第一和第二布线各自相交部分的多个存储单元，具有以非易失性方式存储电阻值作为数据的电可重写可变电阻元件; 第一解码器，连接到所述多个第一布线的至少一端并选择所述第一布线; 至少一对第二解码器，连接到所述多个第二布线的两端，并且每个所述第二解码器根据由所述第一解码器选择的所述第一布线与所述多个第二布线的每一端之间的距离来选择所述第二布线; 以及施加预定电压到由第一解码器和第二解码器选择的第一线和第二线之间的电压施加电路。版权所有（C）2012，JPO＆INPIT

3. 发明专利

JP2013187506A Nonvolatile semiconductor memory device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2013187506A
公开(公告)日：2013-09-19
申请号：JP2012053760
申请日：2012-03-09
申请人： Toshiba Corp , 株式会社東芝
发明人： KIKUCHI NATSUKI , KITO MASARU
IPC分类号： H01L21/8247 , H01L21/336 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device that achieves downsizing and to provide a method of manufacturing the same.SOLUTION: A nonvolatile semiconductor memory device 1 includes, on a ground layer 12, a memory string in which a plurality of electrically rewritable memory cells are connected in series and a first resistance element 100. The first resistance element 100 has a plurality of first resistance bodies 110 that are connected in series in a first direction Y substantially parallel to a primary surface 12a of the ground layer 12. Each of the plurality of first resistance bodies 110 includes a pair of first semiconductor layer 120 extending in a Z direction substantially perpendicular to the primary surface 12a of the ground layer 12 and a second semiconductor layer 130 connected to bottom edges of the pair of first semiconductor layers 120.
摘要翻译：要解决的问题：提供一种实现小型化并提供其制造方法的非易失性半导体存储器件。解决方案：非易失性半导体存储器件1在接地层12上包括存储串，其中多个电可重写存储单元串联连接第一电阻元件100.第一电阻元件100具有多个第一电阻体110，其基本上平行于接地层12的主表面12a的第一方向Y串联连接。多个第一电阻体110中的每一个包括在基本上垂直于接地层12的主表面12a的Z方向上延伸的一对第一半导体层120和连接到该对第一半导体层的底部边缘的第二半导体层130 层120。

4. 发明专利

JP2011243265A Nonvolatile storage device and driving method thereof 有权
标题翻译：非易失存储器件及其驱动方法
公开(公告)号：JP2011243265A
公开(公告)日：2011-12-01
申请号：JP2010116499
申请日：2010-05-20
申请人： Toshiba Corp , 株式会社東芝
发明人： TSUKAMOTO TAKAYUKI , SHIMOTORI TAKAFUMI , SUGANO YUJI , MINEMURA YOICHI , KIKUCHI NATSUKI , SATO MITSURU
IPC分类号： G11C13/00 , H01L27/10 , H01L45/00 , H01L49/00
CPC分类号： H01L45/04 , G11C5/147 , G11C13/0007 , G11C13/0038 , G11C13/0064 , G11C13/0069 , G11C13/0097 , G11C2213/71 , G11C2213/72 , H01L45/145
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile storage device for which the controllability of operations is improved, and its driving method.SOLUTION: By an embodiment, the nonvolatile storage device including a memory unit MU and a control unit CU is provided. The memory unit includes first wiring WR1, second wiring WR2, and a memory cell MC which is provided on the crossing part of the first wiring and the second wiring and includes a resistance change layer VR where resistance is changed by at least one of a voltage applied and a current energized through the first wiring and the second wiring. The control unit is connected to the first wiring and the second wiring and supplies at least one of the voltage and the current to the resistance change layer. In the set operation of changing the resistance change layer from the first state of having a first resistance value to the second state of having a second resistance value lower than the first resistance value, the control unit increases the upper limit value of the current to be supplied to the first wiring on the basis of the change of the potential of the first wiring when applying a set operation voltage to the first wiring.
摘要翻译：要解决的问题：提供一种提高操作可控性的非易失性存储装置及其驱动方法。解决方案：通过一个实施例，提供了包括存储器单元MU和控制单元CU的非易失性存储设备。存储单元包括设置在第一布线和第二布线的交叉部分上的第一布线WR1，第二布线WR2和存储单元MC，并且包括电阻改变层VR，其中电阻由电压并通过第一布线和第二布线使电流通电。控制单元连接到第一布线和第二布线，并将电压和电流中的至少一个提供给电阻变化层。在将电阻变化层从具有第一电阻值的第一状态改变为具有低于第一电阻值的第二电阻值的第二状态的设定操作中，控制单元将电流的上限值增加为基于第一布线的电位的变化，向第一布线施加设定的工作电压到第一布线。版权所有（C）2012，JPO＆INPIT

5. 发明专利

JP2010225806A NONVOLATILE SEMICONDUCTOR STORAGE DEVICE 审中-公开
公开(公告)号：JP2010225806A
公开(公告)日：2010-10-07
申请号：JP2009070824
申请日：2009-03-23
申请人： TOSHIBA CORP
发明人： NAKAUCHI TAKAHIRO , KIKUCHI NATSUKI , SASAKI HIROYUKI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device having a structure suitable for miniaturization. SOLUTION: The nonvolatile semiconductor storage device includes memory transistors 18 each including: a second conductivity-type first impurity diffusion layer 12 formed in a semiconductor substrate 11 along a bottom surface 11c within an inner surface 11b of the semiconductor substrate 11; a second conductivity-type second impurity diffusion layer 13 formed on a principal surface 11a of the semiconductor substrate 11 along a side surface 11d; a first gate electrode 15 formed on the side surface 11d through a first insulating film 14 formed on the inner surface 11b and reaching the principal surface 11a from the bottom surface 11c; and a second gate electrode 17 formed on the first gate electrode 15 through a second insulating film 16 and reaching the principal surface 11a from the bottom surface 11c, wherein a first side surface 11d1 on the first impurity diffusion layer 12 side and a second side surface 11d2 on the second impurity diffusion layer 13 side within the side surface 11d are located on different planes, and the second side surface 11d2 is located at a deeper position than the first side surface 11d1 in the depth direction of a channel 19 formed along the side surface 11d. COPYRIGHT: (C)2011,JPO&INPIT

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