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1. 发明专利

JP2013182961A Semiconductor manufacturing device and method of manufacturing semiconductor device 审中-公开
标题翻译：半导体制造装置及制造半导体器件的方法
公开(公告)号：JP2013182961A
公开(公告)日：2013-09-12
申请号：JP2012044803
申请日：2012-02-29
申请人： Toshiba Corp , 株式会社東芝
发明人： SASAKI HIROYUKI , MATSUYAMA HIDETO
IPC分类号： H01L21/285 , C23C16/08 , C23C16/455 , C23C16/507 , C23C16/509 , H01L21/28
CPC分类号： H01L21/02274 , C23C16/0263 , C23C16/0281 , C23C16/14 , C23C28/023 , H01L21/28512 , H01L21/32051
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor manufacturing device capable of forming a low-resistance tungsten film without being subject to the restriction of an underlayer material, and a method of manufacturing a semiconductor device including the tungsten film.SOLUTION: There is provided a semiconductor manufacturing device capable of forming a metal film, comprising: a processing chamber including a substrate provided inside and capable of performing processing; a gas supply part configured to supply a raw material gas of the metal film and a plasma generation gas to an inside of the processing chamber; a plasma generation part configured to generate a plasma of the plasma generation gas; and a bias generation part configured to cause ions generated by the plasma generation part to collide with the substrate.
摘要翻译：要解决的问题：提供能够形成低电阻钨膜而不受限于下层材料的半导体制造装置，以及制造包括钨膜的半导体器件的方法。解决方案：提供一种能够形成金属膜的半导体制造装置，包括：处理室，包括内部设置并能够进行处理的基板; 气体供给部，其构造为将所述金属膜的原料气体和等离子体产生气体供给到所述处理室的内部; 等离子体产生部件，被配置为产生等离子体产生气体的等离子体; 以及偏置产生部，被配置为使由等离子体产生部生成的离子与基板碰撞。

2. 发明专利

JP2010121168A Plating apparatus, plating method, and method for manufacturing semiconductor device 审中-公开
标题翻译：电镀设备，制造方法和制造半导体器件的方法
公开(公告)号：JP2010121168A
公开(公告)日：2010-06-03
申请号：JP2008295603
申请日：2008-11-19
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUYAMA HIDETO , TOYODA KEI
IPC分类号： C25D7/12 , C25D5/08 , H01L21/288 , H01L21/3205
摘要： PROBLEM TO BE SOLVED: To provide a plating apparatus which can enhance the uniformity of film thickness in a plated film; a plating method therefor; and a method for manufacturing a semiconductor device which can reduce wiring failures.
SOLUTION: The plating apparatus 1 which is provided in one embodiment includes: a holder 3 that rotates a substrate W while holding the substrate W so that the plated surface W1 of the substrate W directs upward; a cathode 4 which comes in contact with a circumferential part W2 of the substrate W held by the holder 3; and a nozzle 6 which discharges a plating solution L toward the central part W3 of the substrate W held by the holder 3 and also functions as an anode.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种可以提高镀膜中膜厚均匀性的电镀装置; 电镀方法; 以及能够减少配线故障的半导体装置的制造方法。解决方案：在一个实施例中提供的电镀装置1包括：保持基板W同时保持基板W使得基板W的电镀表面W1向上引导的保持器3; 阴极4，其与由保持件3保持的基板W的周向部分W2接触; 以及将电镀液L朝向由保持件3保持的基板W的中心部W3排出并且也用作阳极的喷嘴6。版权所有（C）2010，JPO＆INPIT

3. 发明专利

JP2009026864A Method of manufacturing semiconductor device and semiconductor device 审中-公开
标题翻译：制造半导体器件和半导体器件的方法
公开(公告)号：JP2009026864A
公开(公告)日：2009-02-05
申请号：JP2007186959
申请日：2007-07-18
申请人： Toshiba Corp , 株式会社東芝
发明人： HOSHI FUMIO , MATSUYAMA HIDETO
IPC分类号： H01L21/768 , C23C16/08 , H01L21/28 , H01L21/285 , H01L21/306
CPC分类号： H01L21/76843 , H01L21/28556 , H01L21/76856 , H01L21/76865 , H01L21/76876 , H01L21/76877 , H01L21/76879 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device, by which resistance of a contact plug is made lower than before.
SOLUTION: The method of manufacturing the semiconductor device includes: a step (S102) of depositing an SiO
2 film on a semiconductor base; a step (S104) of forming a contact hole in the SiO
2 film; a step (S106) of depositing a Ti film in the contact hole; a step (S108) of nitriding the Ti film; a step (S110) of removing the TiN film deposited on a contact-hole sidewall; and a step (S114) of depositing a W film in the contact hole.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种制造半导体器件的方法，通过该方法使接触插头的电阻比以前更低。解决方案：制造半导体器件的方法包括：在半导体基底上沉积SiO 2 膜的步骤（S102）在SiO 2膜形成接触孔的步骤（S104）; 在所述接触孔中沉积Ti膜的步骤（S106）; 对Ti膜进行氮化的工序（S108）去除沉积在接触孔侧壁上的TiN膜的步骤（S110）; 以及在接触孔中沉积W膜的步骤（S114）。版权所有（C）2009，JPO＆INPIT

4. 发明专利

JP2010135672A Method of manufacturing semiconductor memory device 审中-公开
标题翻译：制造半导体存储器件的方法
公开(公告)号：JP2010135672A
公开(公告)日：2010-06-17
申请号：JP2008312067
申请日：2008-12-08
申请人： Toshiba Corp , 株式会社東芝
发明人： NOMURA KAYO , MATSUYAMA HIDETO
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11578 , H01L27/11575 , H01L27/11582
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor memory device, which prevents short circuit between electrode layers. SOLUTION: The method of manufacturing the semiconductor memory device includes: a step of forming a laminate in which multiple electrode layers WL and multiple insulation layers 17 are alternately laminated on a semiconductor substrate 11; a step of forming an insulation film 20 including a charge accumulation layer 22 on the sidewall of each hole formed in the laminate; a step of forming a semiconductor layer 19 in each hole so as to form a memory string MS by connecting multiple memory cells in the lamination direction correspondingly to the number of electrode layers WL; a step of forming a groove 41 in a portion in the vicinity of the memory string MS in the laminate; a step of forming a metal film 42 on the sidewall of the groove 41; a step of forming cap films 43 and 44 that cover the metal film 42 and fill the groove 41; and a step of performing heat treatment with the groove 41 filled with the cap films 43 and 44 so that the semiconductor constituting the electrode layers WL reacts with the metal film 42 to form a compound of both. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种防止电极层之间短路的半导体存储器件的制造方法。解决方案：半导体存储器件的制造方法包括：在半导体衬底11上交替层叠多个电极层WL和多个绝缘层17的叠层体的形成步骤; 在层叠体中形成的各孔的侧壁上形成包含电荷蓄积层22的绝缘膜20的工序; 在每个孔中形成半导体层19的步骤，以便通过相应于电极层WL的数量在层叠方向连接多个存储单元来形成存储器串MS; 在层叠体中的存储器串MS附近的部分形成槽41的工序; 在槽41的侧壁上形成金属膜42的步骤; 形成覆盖金属膜42并填充槽41的盖膜43和44的步骤; 以及用填充有盖膜43和44的槽41进行热处理的步骤，使得构成电极层WL的半导体与金属膜42反应以形成两者的化合物。版权所有（C）2010，JPO＆INPIT

5. 发明专利

JP2009231497A Semiconductor device and manufacturing method therefor 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2009231497A
公开(公告)日：2009-10-08
申请号：JP2008074417
申请日：2008-03-21
申请人： Toshiba Corp , 株式会社東芝
发明人： KITAMURA MASAYUKI , WADA JUNICHI , MATSUYAMA HIDETO
IPC分类号： H01L21/768 , C23C16/14 , H01L21/28 , H01L21/3205 , H01L23/52 , H01L23/522
CPC分类号： H01L21/76843 , H01L21/28518 , H01L21/28556 , H01L21/76846 , H01L21/76856 , H01L21/76862 , H01L21/76864 , H01L21/76873 , H01L2221/1089
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which suppresses the diffusion of a contact plug material into a substrate, and to provide a manufacturing method for the semiconductor device.
SOLUTION: The semiconductor device includes a Cu film 260 serving as a contact plug, electrically connected to a semiconductor substrate 200; a TiN film 242 of a columnar crystal structure located at least on the bottom-face side of the Cu film 260, in contact with the semiconductor substrate 200; a TiN amorphous film 244 located at least on the bottom-face side of the Cu film 260 in contact with the TiN film 242; a TiN film 246, which is located on the bottom-face side and the side face side of the Cu film 260, at least partially in contact with the amorphous film 244 and the Cu film 260, is made of the same material as the material of the TiN film 242, and has a columnar crystal structure, and an SiO
2 film 220 located on the side-face side of the Cu film 260.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供抑制接触插塞材料扩散到衬底中的半导体器件，并提供半导体器件的制造方法。解决方案：半导体器件包括电连接到半导体衬底200的用作接触插塞的Cu膜260; 至少位于Cu膜260的底面侧的与半导体衬底200接触的柱状晶体结构的TiN膜242; 至少位于与TiN膜242接触的Cu膜260的底面侧的TiN非晶膜244; 至少部分地与非晶膜244和Cu膜260接触的位于Cu膜260的底面侧和侧面侧的TiN膜246由与材料相同的材料制成的TiN膜242，并且具有柱状晶体结构和位于Cu膜260的侧面侧上的SiO 2 SB 2膜220.权利要求（C）2010，JPO和INPIT

6. 发明专利

JP2013067844A Film deposition apparatus 审中-公开
标题翻译：胶片沉积装置
公开(公告)号：JP2013067844A
公开(公告)日：2013-04-18
申请号：JP2011208635
申请日：2011-09-26
申请人： Toshiba Corp , 株式会社東芝
发明人： TAJI HIROKI , MATSUYAMA HIDETO
IPC分类号： C23C16/455
摘要： PROBLEM TO BE SOLVED: To provide a film deposition apparatus that can improve in-plane uniformity of a film thickness of a deposited film, for instance.SOLUTION: The film deposition apparatus for depositing a film on a substrate includes a stage, a shower head and a conductance adjustment wall. The stage is disposed inside a deposition chamber, has a substrate placed thereon and is operable to move upward and downward. The shower head has a planar width wider than that of the substrate, includes a plurality of holes in the surface thereof facing the stage and feeds a film deposition gas to a surface of the substrate through the plurality of holes. The conductance adjustment wall extends on a side of the stage from an outer edge of the shower head so as to adjust a gas conductance of the film deposition gas by the upward and downward movements of the stage on an outer side of the substrate. The shower head and the conductance adjustment wall are mutually integrated into one body.
摘要翻译：要解决的问题：提供例如可以提高沉积膜的膜厚度的面内均匀性的成膜装置。解决方案：用于在基板上沉积膜的成膜装置包括台，淋浴头和电导调节壁。该台设置在沉积室内，具有放置在其上的基板，并可操作以向上和向下移动。淋浴头具有比基板宽的平面宽度，其表面中的多个孔面向台面，并且通过多个孔将成膜气体供给到基板的表面。电导调节壁从淋浴头的外缘在舞台的一侧延伸，以便通过底座的外侧上的舞台的向上和向下运动来调节成膜气体的气体传导。淋浴头和电导调节壁相互整合成一体。版权所有（C）2013，JPO＆INPIT

7. 发明专利

JP2011179124A Method for production of component for vacuum film deposition apparatus 有权
标题翻译：用于生产真空膜沉积装置的组分的方法
公开(公告)号：JP2011179124A
公开(公告)日：2011-09-15
申请号：JP2011101344
申请日：2011-04-28
申请人： Toshiba Corp , Toshiba Electronic Engineering Corp , 東芝電子エンジニアリング株式会社 , 株式会社東芝
发明人： YABE YOICHIRO , NAKAMURA TAKASHI , SATO MICHIO , KOSAKA YASUO , KATADA TOMIO , WADA JUNICHI , SAKATA ATSUKO , KINOSHITA KAZUYA , MATSUYAMA HIDETO , WATANABE KOICHI
IPC分类号： C23C4/18 , C23C14/00 , C23C30/00
摘要： PROBLEM TO BE SOLVED: To stably and effectively prevent separation of a film deposition material deposited during the process for depositing a thin film with high internal stress in a vacuum film deposition apparatus, and to suppress degradation of productivity and increase in the film deposition cost when the apparatus is cleaned and the components are changed.
SOLUTION: There is provided a method of producing a component 1 for a vacuum film deposition apparatus for depositing the thin film of a single metal element selected from Ti, Zr, Hf, Nb, Ta, W, Ru, Pd, Ir, Pt, Ag, Au and In, or an alloy or compound containing the metal elements. The method includes: a step of forming, on the surface of a component body 2, a thermally-sprayed Cu film 3 having a thickness of ≥300 μm; an annealing step of heating, in a vacuum atmosphere, the component on the surface of which the thermally-sprayed Cu film 3 is formed; and a reducing step of reducing the component after the annealing step in a hydrogen atmosphere at a temperature lower than that of the annealing step.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：为了稳定有效地防止在真空成膜装置中沉积具有高内应力的薄膜的沉积过程中沉积的成膜材料的分离，并且抑制生产率的降低和膜的增加当清洁设备并改变组件时的沉积成本。解决方案：提供了一种用于沉积选自Ti，Zr，Hf，Nb，Ta，W，Ru，Pd，Ir的单一金属元素的薄膜的真空成膜装置的组分1的制备方法，Pt，Ag，Au和In，或含有金属元素的合金或化合物。该方法包括：在构件体2的表面上形成厚度≥300μm的热喷镀Cu膜3的工序; 退火步骤，在真空气氛中加热其表面上形成有热喷涂Cu膜3的部件; 以及还原步骤，在退火工序后，在低于退火工序的温度下，在氢气氛中还原成分。版权所有（C）2011，JPO＆INPIT

8. 发明专利

JP2010165760A Semiconductor device and method for manufacturing the semiconductor device 审中-公开
标题翻译：用于制造半导体器件的半导体器件和方法
公开(公告)号：JP2010165760A
公开(公告)日：2010-07-29
申请号：JP2009005318
申请日：2009-01-14
申请人： Toshiba Corp , 株式会社東芝
发明人： HATANO SHOSUKE , WADA JUNICHI , MATSUYAMA HIDETO
IPC分类号： H01L21/768 , H01L21/285 , H01L21/3205 , H01L23/52
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which suppresses wiring resistance between a wiring layer and a plug layer of a lower layer thereof, and simultaneously enhances an implanting property of a plug of the lower layer.
SOLUTION: This semiconductor device includes: Cu wiring 10; a Cu plug 20 coming into contact with the Cu wiring 10 on the lower layer side of the Cu wiring 10 for connection; BM films 240 which are disposed on the base and the side of the Cu plug 20, and have a barrier property to Cu; an Ru film 242 which is disposed selectively on the side of the Cu plug 20 of the Cu wiring 10 and the Cu plug 20 so as to interpose between the Cu plug 20 and the BM films 240, and has the higher wettability with respect to the conductive materials than the BM films 240; and BM films 244 which are disposed on the base of the Cu wiring 10 and the side of the Cu wiring 10 except for at least a portion where the Cu wiring 10 comes into contact with the Cu plug 20, and has the barrier property to Cu.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种抑制布线层和下层的插塞层之间的布线电阻的半导体器件，并且同时增强下层的插塞的植入特性。解决方案：该半导体器件包括：Cu布线10; Cu插头20与Cu布线10的下层侧的Cu布线10接触，用于连接; BM膜240，其设置在Cu插塞20的基部和侧面上，并且对Cu具有阻挡性; 选择性地设置在铜布线10的Cu插头20的侧面上的Ru膜242和Cu插塞20，以便插入在Cu插头20和BM膜240之间，并且相对于导电材料比BM薄膜240; 以及布置在Cu布线10的基部和Cu布线10的一侧的BM膜244，除了Cu布线10与铜插塞20接触的至少一部分之外，还具有Cu的阻挡性。版权所有（C）2010，JPO＆INPIT

9. 发明专利

JP2009026989A Semiconductor device, manufacturing method of the semiconductor device 审中-公开
标题翻译：半导体器件，半导体器件的制造方法
公开(公告)号：JP2009026989A
公开(公告)日：2009-02-05
申请号：JP2007189197
申请日：2007-07-20
申请人： Toshiba Corp , 株式会社東芝
发明人： NOMURA YOSHIYO , WADA JUNICHI , MATSUYAMA HIDETO , KITAMURA MASAYUKI
IPC分类号： H01L21/768
CPC分类号： H01L21/76877 , H01L21/76831 , H01L21/76843 , H01L21/76855 , H01L21/76867 , H01L21/76873 , H01L23/485 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method, capable of reducing the resistance of a contact plug, as compared with a conventional device, while preventing alloy reaction of Al and Cu.
SOLUTION: The semiconductor device is provided with an Al film 260 arranged on a substrate 200 which serves as a contact plug of a first stage; a high melting-point metal film 262, arranged by contacting with the Al film 260 as a contact plug of a second stage; an SiO
2 film 210 arranged on a side-surface side of the Al film 260 and the high melting-point metal film 262; a Cu film 264 arranged above the high melting-point metal film 262 as a wiring; an insulating film 220 arranged on a side surface side of the Cu film 264; and a barrier metal film 240, arranged at least between the Cu film 264, the SiO
2 film 210, and the insulating film 220.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供与常规装置相比能够降低接触塞的电阻的半导体器件及其制造方法，同时防止Al和Cu的合金反应。解决方案：半导体器件设置有布置在基板200上的Al膜260，其用作第一级的接触插塞; 高熔点金属膜262，通过与作为第二级的接触塞的Al膜260接触而布置; 布置在Al膜260和高熔点金属膜262的侧表面侧的SiO 2 膜210; 布置在高熔点金属膜262上方的Cu膜264作为布线; 设置在Cu膜264的侧面侧的绝缘膜220; 和至少布置在Cu膜264，SiO 2 膜210和绝缘膜220之间的阻挡金属膜240.（C）2009，JPO＆INPIT

10. 发明专利

JP2009004541A Manufacturing method of semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：JP2009004541A
公开(公告)日：2009-01-08
申请号：JP2007163686
申请日：2007-06-21
申请人： Toshiba Corp , 株式会社東芝
发明人： YAMADA NOBUHIDE , MATSUYAMA HIDETO , MIYAJIMA HIDESHI
IPC分类号： H01L21/316 , H01L21/3205 , H01L21/768 , H01L23/522
CPC分类号： H01L21/76831 , C23C18/1212 , H01L21/02164 , H01L21/02208 , H01L21/02271 , H01L21/02362 , H01L21/31612
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device for flattening a surface of a work part in an insulating film formed on a semiconductor substrate.
SOLUTION: Prescribed work is performed on the insulating film 24 formed on the semiconductor substrate. A first primary reactant to which a material containing Si content compound is made to react is supplied to the surface 28a of the work part in the insulating film 24. Dehydrate condensation is performed on the primary reactant. Thus, a silicone oxide film 30 is formed on the surface 28a of the work part.
COPYRIGHT: (C)2009,JPO&INPIT

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