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1. 发明专利

JP2010251572A Nonvolatile semiconductor storage device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2010251572A
公开(公告)日：2010-11-04
申请号：JP2009100339
申请日：2009-04-16
申请人： Toshiba Corp , 株式会社東芝
发明人： YAMASHITA SAYAKO , NAKAUCHI TAKAHIRO , SASAKI HIROYUKI , IRIE MASASHI , KIKUCHI NATSUKI
IPC分类号： H01L21/8247 , G11C16/04 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device of a charge-trap flash structure which makes a memory cell into a high integration degree.
SOLUTION: In the semiconductor storage device 50, a plurality of opening parts 5 where an element separation layer 2, a source electrode 3a, a source electrode 3b, a drain electrode 4a and a drain electrode 4b are etched and opened in pillar shapes are separately arranged on a first main face (surface) of a semiconductor substrate layer 1a as a ground line SUBL. A semiconductor substrate layer 1b, a laminated film 6 and a gate electrode 7 are buried in the opening part 5. The semiconductor substrate layer 1b is arranged on an inner side of the opening part 5 so that it is brought into contact with the semiconductor substrate layer 1a. The laminated film 6 formed of a tunnel oxide film, a charge accumulation film and a current interruption film is arranged on an inner side of the semiconductor substrate layer 1b. A gate electrode 7 is buried on an inner side of the laminated film 6. A memory transistor where a plurality of source layers 8 and drain layers 9 are arranged in the semiconductor substrate layer 1b in a vertical direction, and a channel is disposed in the vertical direction is laminated and formed.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：解决的问题：提供使存储单元成为高集成度的电荷捕捉闪存结构的非易失性半导体存储装置。解决方案：在半导体存储装置50中，将元件分离层2，源电极3a，源极电极3b，漏电极4a和漏极电极4b的多个开口部5蚀刻并在柱上打开形状分别设置在作为接地线SUBL的半导体衬底层1a的第一主面（表面）上。半导体衬底层1b，层叠膜6和栅极电极7被埋在开口部5中。半导体衬底层1b布置在开口部5的内侧，使其与半导体衬底接触层1a。由半导体衬底层1b的内侧设置由隧道氧化膜，电荷蓄积膜和电流中断膜形成的层叠膜6。栅极电极7埋设在层叠膜6的内侧。在半导体衬底层1b中沿垂直方向布置有多个源极层8和漏极层9的存储晶体管，并且沟道布置在垂直方向被层压并形成。版权所有（C）2011，JPO＆INPIT

2. 发明专利

JP2005101217A Static random access memory 有权
标题翻译：静态随机存取存储器
公开(公告)号：JP2005101217A
公开(公告)日：2005-04-14
申请号：JP2003332107
申请日：2003-09-24
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUZAWA KAZUYA , UCHIDA KEN , NAKAUCHI TAKAHIRO
IPC分类号： H01L29/417 , H01L21/8244 , H01L27/08 , H01L27/092 , H01L27/11 , H01L27/146 , H01L27/148
CPC分类号： H01L27/11 , H01L27/1104 , H01L27/1463 , Y10S257/903
摘要： PROBLEM TO BE SOLVED: To provide an SRAM cell exhibiting excellent soft error tolerance.
SOLUTION: The static random access memory comprises: a first complementary field effect transistor including a first electron conductivity type field effect transistor having a drain region making Schottky junction with a semiconductor substrate, and a first hole conductivity type field effect transistor sharing a drain region with the first electron conductivity type field effect transistor and having a gate electrode common with the first electron conductivity type field effect transistor; and a second complementary field effect transistor including a second electron conductivity type field effect transistor having a second drain region making Schottky junction with the semiconductor substrate, and a second hole conductivity type field effect transistor sharing a drain region with the second electron conductivity type field effect transistor and having a gate electrode common with the first electron conductivity type field effect transistor. The common gate electrode of the first and second complementary field effect transistors is connected with the shared drain region of opposing complementary field effect transistors.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供具有优异的软误差容限的SRAM单元。解决方案：静态随机存取存储器包括：第一互补场效应晶体管，其包括具有与半导体衬底形成肖特基结的漏极区的第一电子传导型场效应晶体管，以及共享漏极区域与第一电子传导型场效应晶体管并且具有与第一电子传导型场效应晶体管共同的栅电极; 以及第二互补场效应晶体管，其包括具有与半导体衬底形成肖特基结的第二漏极区的第二电子传导型场效应晶体管，以及共享具有第二电子传导型场效应的漏极区的第二空穴导电型场效应晶体管并具有与第一电子传导型场效应晶体管相同的栅电极。第一和第二互补场效应晶体管的公共栅电极与相对的互补场效应晶体管的共用漏极区域连接。版权所有（C）2005，JPO＆NCIPI

3. 发明专利

JP2008217914A Nonvolatile semiconductor memory device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2008217914A
公开(公告)日：2008-09-18
申请号：JP2007055056
申请日：2007-03-06
申请人： Toshiba Corp , 株式会社東芝
发明人： NAKAUCHI TAKAHIRO , AOKI MINORU , KONDO TOSHIYUKI , HARA NORIMASA , NARUGE KIYOMI
IPC分类号： G11C16/06
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device capable of reducing the deterioration amount of a tunnel oxide film and data erasure time. SOLUTION: This nonvolatile semiconductor memory device 100 is provided with: a nonvolatile memory cell 201 having a charge storage part on a tunnel insulating film; and a voltage adjusting circuit 203 for adjusting a writing voltage on the basis of the composite resistance value of a composite resistance element 401 which serially connects a first resistance element R404 of negative temperature characteristics where a resistance value declines with a temperature increase and a second resistance element R405 of positive temperature characteristics where a resistance value increases with a temperature increase to supply it to the drain electrode of the nonvolatile memory cell. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题：提供能够减少隧道氧化膜的劣化量和数据擦除时间的非易失性半导体存储器件。解决方案：这种非易失性半导体存储器件100具有：在隧道绝缘膜上具有电荷存储部分的非易失性存储单元201; 以及电压调整电路203，用于根据复合电阻元件401的复合电阻值来调整写入电压，复合电阻元件401使负温度特性的第一电阻元件R404串联连接，其中电阻值随温度升高而下降，第二电阻正温度特性的元件R405，其中电阻值随着温度升高而增加，以将其提供给非易失性存储单元的漏电极。版权所有（C）2008，JPO＆INPIT

4. 发明专利

JP2010118596A Nonvolatile semiconductor storage device and method of manufacturing same 审中-公开
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：JP2010118596A
公开(公告)日：2010-05-27
申请号：JP2008292027
申请日：2008-11-14
申请人： Toshiba Corp , 株式会社東芝
发明人： NAKAUCHI TAKAHIRO , KAWASAKI YASUNOBU
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device capable of stably holding a potential of a shield electrode arranged between the adjacent gate electrodes to relieve a proximity effect by the shield electrode, and a method of manufacturing the same. SOLUTION: The shield electrode 25 is arranged between the gate electrodes G1, G2 which are arranged adjacent to each other on a semiconductor substrate 1 and have a floating gate 11 and a control gate 16 via a gate sidewall insulating film 22. Then, at least a part of the shield electrode 25 is constituted of a silicide layer consisting of metal and silicon. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题：提供一种能够稳定地保持布置在相邻栅电极之间的屏蔽电极的电位以减轻屏蔽电极的接近效应的非易失性半导体存储装置及其制造方法。解决方案：屏蔽电极25布置在半导体衬底1上彼此相邻布置的栅极电极G1，G2之间，并且经由栅极侧壁绝缘膜22具有浮置栅极11和控制栅极16.然后屏蔽电极25的至少一部分由金属和硅构成的硅化物层构成。版权所有（C）2010，JPO＆INPIT

5. 发明专利

JP2006013250A Semiconductor storage device and manufacturing method thereof 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：JP2006013250A
公开(公告)日：2006-01-12
申请号：JP2004190299
申请日：2004-06-28
申请人： Toshiba Corp , 株式会社東芝
发明人： NAKAUCHI TAKAHIRO , KAWASAKI YASUNOBU , GOTO SHINSUKE
IPC分类号： H01L27/11 , H01L21/8244
摘要： PROBLEM TO BE SOLVED: To improve software error resistance without remarkable increment of cell area and cost as a complete CMOS type SRAM cell.
SOLUTION: The gate electrode of a first (second) MISFET for drive and load is formed of an integrated n-type polysilicon in separation from the gate electrode of a first (second) MISFET for transfer, and a first (second) resistance element is formed through control of impurity concentration within the n-type polysilicon. First and second resistance elements are respectively formed in the side of direction opposed to that of the first or second MISFET for drive in front of the gate of the first or second MISFET for load. A wiring from an output node of a second (first) inverter is connected to a contact electrode formed at the upper part of the n-type polysilicon as the first (second) resistance element. The first and second MISFETs for load have the n-type gate electrodes.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提高软件错误阻力，无需作为完整的CMOS型SRAM单元的单元面积和成本显着增加。解决方案：用于驱动和负载的第一（第二）MISFET的栅电极由与用于传输的第一（第二）MISFET的栅极分离的集成的n型多晶硅形成，并且第一（第二）通过控制n型多晶硅内的杂质浓度来形成电阻元件。第一和第二电阻元件分别形成在与用于负载的第一或第二MISFET的栅极前面驱动的第一或第二MISFET的相反方向的一侧。作为第一（第二）电阻元件，从第二（第一）反相器的输出节点的布线连接到形成在n型多晶硅的上部的接触电极。用于负载的第一和第二MISFET具有n型栅电极。版权所有（C）2006，JPO＆NCIPI

6. 发明专利

JP2008103019A Semiconductor memory device and its data writing method 审中-公开
标题翻译：半导体存储器件及其数据写入方法
公开(公告)号：JP2008103019A
公开(公告)日：2008-05-01
申请号：JP2006284525
申请日：2006-10-19
申请人： Toshiba Corp , 株式会社東芝
发明人： MURAKI KAZUHIKO , NARUGE KIYOMI , NAKAUCHI TAKAHIRO
IPC分类号： G11C16/02 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To prevent erroneous writing into a non-selection memory cell and to provide a semiconductor memory device having the improved integration degree. SOLUTION: The semiconductor memory device 100 includes: a plurality of bit lines; a plurality of word lines intersecting with the plurality of bit lines; a source line arranged between the predetermined number of word lines; first selection transistors connected to the bit lines; and second selection transistors connected to the source line. The device is also equipped with: memory cell units having memory cell columns connecting a plurality of electrical erasure type nonvolatile memory cells in series while one end is connected to the first selection transistor and a first control electrode is connected to the word line; and a transistor electrically connected in series between the memory cell at another end of the memory cell column and the second selection transistor, and on which an intermediate potential between a potential applied on the first control electrode of the memory cell at another end and a potential applied on a second control electrode of the second selection transistor is applied on a third control electrode, in the non-selected state of data writing operation of the memory cell at another end. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了防止对非选择存储单元的错误写入并提供具有改进的集成度的半导体存储器件。解决方案：半导体存储器件100包括：多个位线; 与所述多个位线相交的多个字线; 布置在预定数量的字线之间的源极线; 连接到位线的第一选择晶体管; 以及连接到源极线的第二选择晶体管。该装置还配备有具有存储单元列的存储单元单元，该存储单元列串联多个电擦除型非易失性存储单元，同时一端连接到第一选择晶体管，第一控制电极连接到字线; 以及晶体管串联电连接在存储单元列的另一端的存储单元和第二选择晶体管之间，并且其上施加在另一端的存储单元的第一控制电极上的电位和电位之间的中间电位施加在第二选择晶体管的第二控制电极上的第二控制电极被施加在另一端的存储单元的数据写入操作的未选择状态的第三控制电极上。版权所有（C）2008，JPO＆INPIT

7. 发明专利

JP2008052811A Nonvolatile semiconductor device 审中-公开
标题翻译：非线性半导体器件
公开(公告)号：JP2008052811A
公开(公告)日：2008-03-06
申请号：JP2006227510
申请日：2006-08-24
申请人： Toshiba Corp , 株式会社東芝
发明人： FUJII SAYAKO , NAKAUCHI TAKAHIRO , NARUGE KIYOMI
IPC分类号： G11C16/06 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor storage device wherein erroneous writing and erroneous erasure in a memory cell associated with minuteness of the memory cell are reduced. SOLUTION: The nonvolatile semiconductor device wherein a charge storage layer and a control gate layer are layered on a channel via an insulating film and memory cells MC11 to MC1n, ..., MCm1 to MCmn each having a diffusion layer forming a current path are disposed in a matrix shape sandwiching the channel and which has bit lines BL1 to BLn connected to the diffusion layers of the plurality of memory cells MC11 to MC1n, ..., MCm1 to MCmn is provided with transistors TR1 to TRn connected to the bit lines BL1 to BLn and discharging voltage applied to the diffusion layers of the memory cells MC11 to MCmn and having a prescribed value or more. Drains of the transistors TR1 to TRn are connected to the bit lines BL1 to BLn and sources thereof are grounded. Each of the transistors TR1 to TRn has a prescribed threshold and is carried out diode-connection. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体存储装置，其中与存储单元的细微关联的存储单元中的错误写入和错误擦除减少。解决方案：其中电荷存储层和控制栅极层经由绝缘膜在沟道上层叠的非易失性半导体器件以及具有形成电流的扩散层的存储单元MC11至MC1n，...，MCm1至MCmn 路径被布置成夹着通道的矩阵形状，并且具有连接到多个存储单元MC11至MC1n，...，MCm1至MCmn的扩散层的位线BL1至BLn设置有连接到该多路存储器单元的晶体管TR1至TRn 位线BL1〜BLn和施加到存储单元MC11〜MCmn的扩散层的放电电压并具有规定值以上。晶体管TR1至TRn的漏极连接到位线BL1至BLn，并且其源极接地。晶体管TR1〜TRn中的每一个具有规定的阈值，并进行二极管连接。版权所有（C）2008，JPO＆INPIT

8. 发明专利

JP2008004832A Nonvolatile semiconductor memory device and method for manufacturing the same 审中-公开
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：JP2008004832A
公开(公告)日：2008-01-10
申请号：JP2006174172
申请日：2006-06-23
申请人： Toshiba Corp , 株式会社東芝
发明人： NAKAUCHI TAKAHIRO , NARUGE KIYOMI
IPC分类号： H01L21/8247 , G11C16/04 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device that is excellent in write and read characteristics and is easy to manufacture; and to provide a method of manufacturing the same. SOLUTION: The nonvolatile semiconductor memory device has: a plurality of source/drain regions 11 formed approximately in parallel; a semiconductor substrate 1 having a depression 12 formed between the plurality of source/drain regions 11; an electric charge accumulation gate 3 formed in the depression 12 of the semiconductor substrate 1; and a plurality of conductive gates 6 that intersects the plurality of source/drain regions 11 and is arranged on the accumulation gate 3 with an insulating layer in between. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种写入和读取特性优异且易于制造的非易失性半导体存储器件; 并提供其制造方法。解决方案：非易失性半导体存储器件具有：大致平行形成的多个源极/漏极区域11; 具有形成在多个源极/漏极区域11之间的凹陷部分12的半导体衬底1; 形成在半导体衬底1的凹部12中的电荷积蓄门3; 以及多个与多个源极/漏极区域11相交的导电栅极6，并且在其间具有绝缘层而布置在积聚栅极3上。版权所有（C）2008，JPO＆INPIT

9. 发明专利

JP2006013328A Semiconductor apparatus 审中-公开
标题翻译： SEMICONDUCTOR APPARATUS
公开(公告)号：JP2006013328A
公开(公告)日：2006-01-12
申请号：JP2004191449
申请日：2004-06-29
申请人： Toshiba Corp , Toshiba Microelectronics Corp , 東芝マイクロエレクトロニクス株式会社 , 株式会社東芝
发明人： NAKAUCHI TAKAHIRO , NARUGE YASUO , KOBAYASHI HIDEYUKI , KOIKE NOBORU , KIZU TATSUTAKA , KONDO TOSHIYUKI , NOHARA HARUO , GOTO SHINSUKE , ITO SANAE , KONDO MASAKI , IRIE MASASHI
IPC分类号： H01L29/78 , H01L21/8238 , H01L21/8244 , H01L27/092 , H01L27/11
CPC分类号： H01L29/785
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor apparatus having a large parasitic capacitance in order to achieve a highly reliable semiconductor apparatus. SOLUTION: The semiconductor apparatus includes a semiconductor substrate 1 including a projected portion 1b extending in the first direction. A gate insulating film 11 is disposed on the upper surface of the projected portion and on a side surface along the first direction. A gate electrode 12 includes the first portion 12a and the second portion 12b. The first portion crosses the projected portion and is arranged on a gate insulating film on the upper surface of the projected portion. The second portion is disposed on the gate insulating film on the side surface of the projected portion and the length thereof in the first direction is longer than the length in the first direction for the first portion. A pair of source and drain regions 13 is formed on the surface of the projected portion to hold the lower region of the first portion of the gate electrode. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提供具有大的寄生电容的半导体装置，以便实现高度可靠的半导体装置。解决方案：半导体器件包括半导体衬底1，其包括在第一方向上延伸的突出部分1b。栅极绝缘膜11设置在突出部分的上表面和沿着第一方向的侧表面上。栅电极12包括第一部分12a和第二部分12b。第一部分与突起部分交叉并且布置在突出部分的上表面上的栅极绝缘膜上。第二部分设置在突出部分的侧表面上的栅极绝缘膜上，并且其第一方向上的长度比第一部分的第一方向上的长度长。在突出部分的表面上形成一对源极和漏极区域13，以保持栅电极的第一部分的下部区域。版权所有（C）2006，JPO＆NCIPI

10. 发明专利

JP2005217246A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2005217246A
公开(公告)日：2005-08-11
申请号：JP2004022913
申请日：2004-01-30
申请人： Toshiba Corp , 株式会社東芝
发明人： NOHARA HARUO , KOBAYASHI HIDEYUKI , NARUGE YASUO , NAKAUCHI TAKAHIRO
IPC分类号： H01L21/28 , H01L21/8244 , H01L27/11 , H01L29/423 , H01L29/49
摘要： PROBLEM TO BE SOLVED: To provide an SRAM which is excellent in soft error resistance.
SOLUTION: The semiconductor device has a gate electrode 15 formed of polysilicon, a salicide film 22 provided to the surface of the gate electrode and a contact 26 provided on the gate electrode. A region 14 wherein the salicide film 22 does not exist is provided to a periphery of the contact 26a including a portion in contact with the gate electrode.
COPYRIGHT: (C)2005,JPO&NCIPI

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