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    • 4. 发明专利
    • Substrate processing device and substrate processing method
    • 基板处理装置和基板处理方法
    • JP2012015451A
    • 2012-01-19
    • JP2010153096
    • 2010-07-05
    • Tokyo Electron Ltd東京エレクトロン株式会社
    • HONDA MASANOBUKUBOTA KAZUHIROOYA YOSHINOBUNISHINO MASA
    • H01L21/3065H05H1/46
    • H01L21/6719H01J37/18H01J37/32091H01J37/32633H01J37/32834H01L21/31116H01L21/31122H01L21/31138H01L21/31144
    • PROBLEM TO BE SOLVED: To provide a substrate processing device in which generation of particles in a processing chamber can be prevented, distribution of plasma can be prevented from being disturbed, and the adjustment range of exhaust air conductance can be expanded.SOLUTION: A substrate processing device 10 comprises a processing chamber 13 in which a wafer W is housed and subjected to plasma etching, an exhaust chamber 14 communicating with the processing chamber 13, an exhaust plate 15 which partitions the processing chamber 13 and the exhaust chamber 14 and prevents plasma in the processing chamber 13 from leaking into the exhaust chamber 14, and an upper electrode plate 28 arranged in the exhaust chamber 14. The exhaust plate 15 has a plurality of through holes, and the upper electrode plate 28 also has a plurality of through holes. The upper electrode plate 28 can contact with the exhaust plate 15 in parallel therewith and can separate therefrom.
    • 解决的问题:为了提供可以防止在处理室中产生颗粒的基板处理装置,可以防止等离子体的分布受到干扰,并且可以扩大排气导通的调节范围。 解决方案:基板处理装置10包括其中容纳晶片W并进行等离子体蚀刻的处理室13,与处理室13连通的排气室14,分隔处理室13的排气板15和 排气室14防止处理室13中的等离子体泄漏到排气室14中,以及布置在排气室14中的上电极板28.排气板15具有多个通孔,上电极板28 还具有多个通孔。 上电极板28可以与排气板15平行地接触并且可以与排气板15分离。 版权所有(C)2012,JPO&INPIT
    • 5. 发明专利
    • Plasma etching method, plasma etching apparatus, and storage medium
    • 等离子体蚀刻方法,等离子体蚀刻装置和存储介质
    • JP2010219491A
    • 2010-09-30
    • JP2009247725
    • 2009-10-28
    • Tokyo Electron Ltd東京エレクトロン株式会社
    • MOCHIKI HIROMASAOYA YOSHINOBUYAMAZAKI FUMIOHAGA TOSHIO
    • H01L21/3065H01L21/768
    • PROBLEM TO BE SOLVED: To provide a plasma etching method capable of achieving a sufficient organic film modifying effect by high-velocity electrons. SOLUTION: In forming a hole in an etching target film by plasma etching, a first condition of generating plasma within a processing container by turning on a plasma-generating high frequency power application unit, and a second condition of eliminating plasma within the processing container by turning off the plasma-generating high frequency power application unit are repeated alternately, and a negative direct-current voltage is applied from a first direct-current power supply such that an absolute value of the applied voltage during a period of the second condition is greater than that during a period of the first condition. COPYRIGHT: (C)2010,JPO&INPIT
    • 要解决的问题:提供能够通过高速电子实现足够的有机膜修饰效果的等离子体蚀刻方法。 解决方案:在通过等离子体蚀刻在蚀刻靶膜中形成孔时,通过接通等离子体产生高频功率施加单元在处理容器内产生等离子体的第一条件,以及在等离子体产生高频功率施加单元内消除等离子体的第二条件 交替地重复关闭等离子体产生高频电力应用单元的处理容器,并且从第一直流电源施加负的直流电压,使得在第二次的时间段期间施加的电压的绝对值 条件大于第一条件期间的条件。 版权所有(C)2010,JPO&INPIT
    • 6. 发明专利
    • Plasma etching method, plasma etching apparatus, and storage medium
    • 等离子体蚀刻方法,等离子体蚀刻装置和存储介质
    • JP2010171320A
    • 2010-08-05
    • JP2009014254
    • 2009-01-26
    • Tokyo Electron Ltd東京エレクトロン株式会社
    • HATTA KOICHIOYA YOSHINOBUOKAMOTO SUSUMUMOCHIKI HIROMASA
    • H01L21/3065H01L21/768H01L23/522
    • H01J37/32146H01J37/32091H01J37/32697
    • PROBLEM TO BE SOLVED: To provide a plasma etching method which can form holes with a high aspect ratio, by etching a film to be etched at a high etching rate and with proper formability. SOLUTION: In order to form holes in a film to be etched by plasma etching, there are a first condition for generating plasma in a treatment container by turning on a plasma generation high-frequency power applying unit, and applying a negative DC voltage from a DC power source to an upper electrode; and a second condition for extinguishing plasma in the treatment container by turning off the plasma generation high-frequency power applying unit, and applying a negative DC voltage from the DC power source to the upper electrode are applied alternately. In the first condition, etching is performed by positive ions in the plasma. In the second condition, negative ions are generated and supplied by means of the DC voltage into the holes so that positive charge in the holes is neutralized. COPYRIGHT: (C)2010,JPO&INPIT
    • 要解决的问题:为了提供可以形成具有高纵横比的孔的等离子体蚀刻方法,通过以高蚀刻速率和适当的成形性蚀刻待蚀刻的膜。 解决方案:为了通过等离子体蚀刻在待蚀刻的膜中形成孔,存在通过打开等离子体产生高频电力施加单元而在处理容器中产生等离子体的第一条件,并且施加负DC 从直流电源到上电极的电压; 并且交替地施加通过关闭等离子体产生高频电力施加单元来熄灭处理容器中的等离子体的第二条件,并且将来自DC电源的负DC电压施加到上电极。 在第一条件下,通过等离子体中的正离子进行蚀刻。 在第二种情况下,通过直流电压产生并提供负离子到孔中,使得空穴中的正电荷被中和。 版权所有(C)2010,JPO&INPIT
    • 7. 发明专利
    • Plasma processing method and plasma processing apparatus
    • 等离子体处理方法和等离子体处理装置
    • JP2012069921A
    • 2012-04-05
    • JP2011171005
    • 2011-08-04
    • Tokyo Electron Ltd東京エレクトロン株式会社
    • OYA YOSHINOBUTANABE AKIRAYASUDA YOSHINORI
    • H01L21/3065
    • H01J37/02H01J37/32091H01J37/32165H01J2237/3348
    • PROBLEM TO BE SOLVED: To optimize a plasma process for various requirements of microfabrication by enhancing the controllability of an RF bias function.SOLUTION: In order to apply high frequency waves RFsuitable for plasma generation of capacity coupling from a third high frequency power supply 66 to an upper electrode 46 (or a lower electrode 12) and to control the energy of ions impinging on a semiconductor wafer W from a plasma, the plasma processing apparatus applies two kinds of high frequency waves RF(0.8 MHz), RF(13 MHz) suitable for ion extraction from first and second high frequency power supplies 36, 38 while superimposing on a susceptor 12. In accordance with the specifications, conditions or recipe of the process, a control unit 88 controls the total power and the power ratio of both high frequency waves RF, RF.
    • 要解决的问题:通过提高RF偏置功能的可控性,优化用于微细加工的各种要求的等离子体处理。 解决方案:为了施加适用于从第三高频电源66到上电极46(或更低的)的等离子体产生电容耦合的高频波RF H 电极12),并且为了控制从等离子体入射到半导体晶片W上的离子的能量,等离子体处理装置应用两种高频波RF L1 (0.8MHz) RF L2 (13MHz),适用于从第一和第二高频电源36,38离子提取,同时叠加在基座12上。根据规格,条件或配方 该处理中,控制单元88控制高频波RF L1 ,RF L2 的总功率和功率比。 版权所有(C)2012,JPO&INPIT
    • 9. 发明专利
    • Plasma processing method
    • 等离子体处理方法
    • JP2010192668A
    • 2010-09-02
    • JP2009035344
    • 2009-02-18
    • Tokyo Electron Ltd東京エレクトロン株式会社
    • OYA YOSHINOBU
    • H01L21/3065H05H1/46
    • H01L21/31144H01J37/32027H01J37/32091H01L21/31116
    • PROBLEM TO BE SOLVED: To provide a plasma processing method, where not only etching but also electronic processing on a substrate are both carried out. SOLUTION: The plasma processing apparatus 10 includes a chamber 11 for accommodating a wafer (W) and generating plasma, a susceptor 12, which mounts the wafer (W) disposed in the chamber 11 and to which a high-frequency voltage for acquiring the plasma is applied, and an upper electrode 33 which is disposed opposite to the susceptor 12 in the chamber 11 and to which a negative DC voltage is applied. In the plasma processing apparatus 10, continuation of applying the high-frequency voltage for acquiring the plasma to the susceptor 12 during a predetermined time and stop of applying the high frequency voltage for acquiring the plasma to the susceptor 12 are repeated, while the negative DC voltage is applied to the upper electrode 33. COPYRIGHT: (C)2010,JPO&INPIT
    • 要解决的问题:提供一种等离子体处理方法,其中不仅进行蚀刻,而且进行基板上的电子处理。 解决方案:等离子体处理装置10包括用于容纳晶片(W)并产生等离子体的腔室11,其安装设置在腔室11中的晶片(W),基座12将高频电压 施加等离子体,以及在室11中与基座12相对设置并施加负的直流电压的上部电极33。 在等离子体处理装置10中,重复在预定时间内继续施加用于获取等离子体的高频电压到基座12,并且将用于获取等离子体的高频电压停止施加到基座12,而负的DC 电压施加到上电极33.版权所有(C)2010,JPO&INPIT
    • 10. 发明专利
    • Etching method
    • 蚀刻方法
    • JP2014011191A
    • 2014-01-20
    • JP2012144614
    • 2012-06-27
    • Tokyo Electron Ltd東京エレクトロン株式会社
    • TAKASHIMA RYUICHIOYA YOSHINOBU
    • H01L21/3065
    • H01L21/3088H01J37/32091H01J2237/334H01L21/3065H01L21/3081H01L21/3086H01L29/1608
    • PROBLEM TO BE SOLVED: To form an etching shape of high perpendicularity, by forming a metal mask of etching pattern having high perpendicularity, and then etching a semiconductor while using it as a mask.SOLUTION: A resist film patterned with a reversal pattern of an etching pattern is formed on a semiconductor (resist film formation step S100), the reversal pattern of the resist film is filled with a metal paste (metal paste filling step S200), the metal mask of an etching pattern is formed by removing the resist film while calcining the metal paste by heating control (metal mask formation step S300), and then the semiconductor is subjected to plasma etching by using that metal mask (etching step S400).
    • 要解决的问题:为了形成高垂直度的蚀刻形状,通过形成具有高垂直度的蚀刻图案的金属掩模,然后在将其用作掩模的同时蚀刻半导体。解决方案:图案化具有反转图案的抗蚀剂膜 在半导体(抗蚀剂膜形成步骤S100)上形成蚀刻图案,用金属膏(金属膏填充步骤S200)填充抗蚀剂膜的反转图案,通过除去抗蚀剂膜形成蚀刻图案的金属掩模 同时通过加热控制(金属掩模形成步骤S300)煅烧金属膏,然后通过使用该金属掩模对该半导体进行等离子体蚀刻(蚀刻步骤S400)。