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    • 5. 发明专利
    • Power semiconductor device
    • 功率半导体器件
    • JP2012199435A
    • 2012-10-18
    • JP2011063314
    • 2011-03-22
    • Toshiba Corp株式会社東芝
    • YABUSAKI MUNEHISAINOUE NAOYUKI
    • H01L29/78
    • PROBLEM TO BE SOLVED: To provide a semiconductor device having high withstanding voltage and low on-resistance.SOLUTION: A semiconductor device of an embodiment comprises a drift layer 1 of a first conductivity type, a first semiconductor layer 2 of the first conductivity type, a plurality of base layers 4 of a second conductivity type, a plurality of source layers 5 of the first conductivity type, a second semiconductor layer 3 and a gate electrode 7. The gate electrode includes a first part 7A and a second part 7B. The plurality of base layers include a first base layer 4A, a second base layer 4B adjacent to the first base layer 4A and a third base layer 4C adjacent to the first base layer in addition. The first part of the gate electrode extends in a first direction on the first semiconductor layer striding the first base layer and the second base layer. The second part of the gate electrode extends in a second direction on the first semiconductor layer striding the first base layer and the third base layer. The first part and the second part intersect at an intersection, and directly below the intersection, the second semiconductor layer reaching the drift layer is formed on a surface of the first semiconductor layer.
    • 要解决的问题:提供具有高耐压和低导通电阻的半导体器件。 解决方案:实施例的半导体器件包括第一导电类型的漂移层1,第一导电类型的第一半导体层2,第二导电类型的多个基极层4,多个源极层 第一导电类型的第一部分7A,第二半导体层3和栅极电极7.栅电极包括第一部分7A和第二部分7B。 多个基层包括第一基底层4A,与第一基底层4A相邻的第二基底层4B和与第一基底层相邻的第三基底层4C。 栅电极的第一部分在跨越第一基层和第二基层的第一半导体层上沿第一方向延伸。 栅电极的第二部分在跨越第一基极层和第三基极层的第一半导体层上沿第二方向延伸。 第一部分和第二部分在交叉点相交,并且在交叉点的正下方,到达漂移层的第二半导体层形成在第一半导体层的表面上。 版权所有(C)2013,JPO&INPIT
    • 6. 发明专利
    • Power module and mounting board
    • 电源模块和安装板
    • JP2005243713A
    • 2005-09-08
    • JP2004048241
    • 2004-02-24
    • Toshiba Corp株式会社東芝
    • MIYAKE EITAROINOUE NAOYUKI
    • H01L25/07H01L25/18
    • H01L2224/48091H01L2224/48472H01L2924/01322H01L2924/1301H01L2924/1305H01L2924/13055H01L2924/30107H01L2924/00014H01L2924/00
    • PROBLEM TO BE SOLVED: To provide a power module which operates with a stable high current with a reduced parasitic inductance concerning transient currents. SOLUTION: The power module mounts a plurality of semiconductor chips 18a-18d each flowing a main current between a first and second main electrodes in the interior. The module inside comprises insulation board structures (14a-14d), connection terminals disposed separately from each other on the insulation board structures (14a-14d) with inner connection terminals formed by bending first ends of the terminals away from the board structures (14a-14d) and bonding the bottoms of remaining parts to the insulation board structures (14a-14d), and short-circuit members 31h for electrically short-circuiting the inner connection terminals of the plurality of wiring boards 16a-16d. First main electrodes of corresponding semiconductor chips 18a-18d among the plurality of semiconductor chips 18a-18d are electrically independently connected to the plurality of wiring boards 16a-16d, respectively. COPYRIGHT: (C)2005,JPO&NCIPI
    • 要解决的问题:提供一种功率模块,其工作在稳定的大电流下,具有减小的瞬态电流的寄生电感。 解决方案:功率模块安装多个在内部的第一和第二主电极之间流过主电流的半导体芯片18a-18d。 内部的模块包括绝缘板结构(14a-14d),在绝缘板结构(14a-14d)上彼此分开设置的连接端子,内部连接端子通过使端子的第一端远离板结构(14a- 14d),将剩余部分的底部粘合到绝缘板结构(14a-14d),以及用于使多个布线板16a-16d的内部连接端子短路的短路部件31h。 多个半导体芯片18a-18d中的对应半导体芯片18a-18d的第一主电极分别电连接到多个布线板16a-16d。 版权所有(C)2005,JPO&NCIPI
    • 7. 发明专利
    • High withstand voltage semiconductor device
    • 高耐电压半导体器件
    • JP2003023158A
    • 2003-01-24
    • JP2001206924
    • 2001-07-06
    • Toshiba Corp株式会社東芝
    • HIYOSHI MICHIAKIHASEGAWA SHIGERUINOUE NAOYUKIHARADA TATSUO
    • H01L29/06H01L29/40H01L29/739H01L29/78
    • H01L29/405H01L29/7395
    • PROBLEM TO BE SOLVED: To prevent any adverse influence of parasitic currents running through a terminating region in a high withstand voltage semiconductor device having a reserved terminating configuration.
      SOLUTION: An IGBT chip is provided with an operation region R1 where an IGBT is arranged and an isolated region R2 and a terminating region R3 in the surrounding of the operation region R1. A P
      + type first diffusion layer 32 is formed in the surface of an N
      - type first base layer 12 across the operation region R1 and the terminating region R3. Then, a P
      - type second diffusion area 34 is formed so as to be overlapped with the first diffusion area 32, and to be extended in the terminating area R3. A first contact electrode 40 electrically connected to an emitter electrode 26 of the IGBT is brought into contact with the first diffusion layer 32 in the operation region R1. A second contact electrode 42 is brought into contact with the first diffusion region 32 in the terminating region R3. The first and second contact electrodes 40 and 42 are electrically connected through a connection electrode 41 arranged in the isolated region R2 to each other.
      COPYRIGHT: (C)2003,JPO
    • 要解决的问题:为了防止在具有保留的端接配置的高耐压半导体器件中通过端接区域的寄生电流的任何不利影响。 解决方案:IGBT芯片设置有布置IGBT的操作区域R1和操作区域R1周围的隔离区域R2和端接区域R3。 在N +型第一基极层12的表面上,跨越工作区域R1和端接区域R3形成P ++型的第一扩散层32。 然后,形成P +型第二扩散区域34,以便与第一扩散区域32重叠,并在端接区域R3中延伸。 电连接到IGBT的发射极26的第一接触电极40与操作区域R1中的第一扩散层32接触。 第二接触电极42与终止区域R3中的第一扩散区域32接触。 第一和第二接触电极40和42通过布置在隔离区域R2中的连接电极41彼此电连接。