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1. 发明专利

JP2007123784A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2007123784A
公开(公告)日：2007-05-17
申请号：JP2005317627
申请日：2005-10-31
申请人： Toshiba Corp , 株式会社東芝
发明人： WATANABE RYUTA , KOMODA YASUO , OISHI SHU , OKAYAMA YASUNORI
IPC分类号： H01L29/78 , H01L21/768 , H01L21/8238 , H01L21/8244 , H01L23/522 , H01L27/092 , H01L27/11 , H01L29/41 , H01L29/417
CPC分类号： H01L29/7833 , H01L27/11 , H01L27/1104 , H01L29/7843
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device whose drain current can be improved without increasing its area.
SOLUTION: The semiconductor device is provided with a semiconductor substrate 10, a gate electrode 18 which is formed on the semiconductor substrate 10 via a gate insulating film 16, n-type source-drain diffusion zones 24 which are formed in the semiconductor substrate 10 in regions positioned on both sides of the gate electrode 18, a tensile film 26 which is formed on both sides of the gate electrode 18 on the semiconductor substrate 10 and applies stress to a channel region of the gate electrode 18, and contacts 30 which are formed on the source-drain diffusion zones 24 by penetrating the tensile film 26 and are embedded with conductive material. In this case, the distance between the gate electrode 18 and a source contact 34 is larger than that between the gate electrode 18 and a drain contact 32.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种可以在不增加其面积的情况下改善漏极电流的半导体器件。解决方案：半导体器件设置有半导体衬底10，通过栅极绝缘膜16形成在半导体衬底10上的栅电极18，形成在半导体中的n型源极 - 漏极扩散区24 位于栅电极18的两侧的区域中的基板10，形成在半导体基板10上的栅极电极18的两侧并且向栅极电极18的沟道区域施加应力的拉伸膜26，以及触点30 其通过穿透拉伸膜26而形成在源极 - 漏极扩散区24上，并且嵌入导电材料。在这种情况下，栅电极18和源极触点34之间的距离大于栅电极18和漏极触点32之间的距离。（C）2007，JPO和INPIT

2. 发明专利

JPH0969609A BURIED ELEMENT ISOLATION SUBSTRATE AND ITS MANUFACTURING METHOD 失效
公开(公告)号：JPH0969609A
公开(公告)日：1997-03-11
申请号：JP22396395
申请日：1995-08-31
申请人： TOSHIBA CORP
发明人： NUMANO MASAKUNI , TSUCHIYA NORIHIKO , KUBOTA HIROYASU , HAYASHI YOSHIKI , MATSUSHITA YOSHIAKI , USHIKU YUKIHIRO , YAGISHITA JUNJI , INABA SATOSHI , TAKAHASHI MINORU , OKAYAMA YASUNORI
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/322 , H01L21/74 , H01L21/76 , H01L21/762 , H01L27/08
摘要： PROBLEM TO BE SOLVED: To reduce crystal defects generated in an element formation area when a buried element isolation method is used, by forming a high distortion layer, consisting of a heavily doped area, under a groove part in which an insulating material is buried, while isolated from the bottom of the groove part. SOLUTION: A groove is formed to a specified depth, for example, 1μm, from the surface of a semiconductor substrate 31, and an insulating material 32 is buried in the U groove, for forming an element isolation area, and a part between adjoining two element isolation areas 32 becomes an element formation area 33. A high distortion layer 34 is formed in the semiconductor substrate 31 under each element isolation area 32. When the depth of the grooves is 1μm, the desirable depth of the high distortion layer 34 is within 1.5μm from the surface. By this, the crystal defect generated in the periphery of the insulator buried layer is induced into the high distortion layer 34 by the stress based on the difference of thermal expansion between the semiconductor layer and the insulator layer. So that the crystal defect does not reach the element formation area 33 acting as an active layer. And, the depth of the high distortion layer is, form example, about 1,1-1.4 times deeper than the depth of the groove.

3. 发明专利

JP2008103644A Semiconductor device and production method thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2008103644A
公开(公告)日：2008-05-01
申请号：JP2006286915
申请日：2006-10-20
申请人： Toshiba Corp , 株式会社東芝
发明人： OKAYAMA YASUNORI
IPC分类号： H01L21/8238 , H01L21/28 , H01L27/092 , H01L29/423 , H01L29/49
CPC分类号： H01L21/823443 , H01L21/82345 , H01L21/823468 , H01L21/823835 , H01L21/823842 , H01L21/823864
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having a simple structure in which a FUSI gate electrode is selectively formed, and a production method thereof.
SOLUTION: The semiconductor device according to an aspect of the present invention comprises: a first electric field effect-type transistor including a first gate electrode provided on a semiconductor substrate through a gate insulating film and composed of a metal silicide, a first insulating film provided adjacent to the side face of the first gate electrode, and a first side wall containing the first insulating film; and a second electric field effect-type transistor including a second gate electrode provided on the semiconductor substrate through a gate insulating film and composed of a conductor film containing a polycrystalline silicon, a second insulating film provided adjacent to the side face of the second gate electrode, and a second side wall containing the second insulating film.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有选择性地形成FUSI栅电极的简单结构的半导体器件及其制造方法。解决方案：根据本发明的一个方面的半导体器件包括：第一电场效应型晶体管，包括通过栅极绝缘膜设置在半导体衬底上并由金属硅化物构成的第一栅电极，第一栅电极设置在与第一栅电极的侧面相邻的绝缘膜和包含第一绝缘膜的第一侧壁; 以及第二电场效应型晶体管，其包括通过栅极绝缘膜设置在所述半导体基板上并由包含多晶硅的导体膜构成的第二栅电极，与所述第二栅电极的侧面相邻设置的第二绝缘膜和包含第二绝缘膜的第二侧壁。版权所有（C）2008，JPO＆INPIT

4. 发明专利

JP2003332457A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2003332457A
公开(公告)日：2003-11-21
申请号：JP2003123705
申请日：2003-04-28
申请人： Toshiba Corp , 株式会社東芝
发明人： USHIKU YUKIHIRO , INABA SATOSHI , TAKAHASHI MINORU , YAGISHITA JUNJI , OKAYAMA YASUNORI , MATSUSHITA YOSHIAKI , KUBOTA HIROYASU , TSUCHIYA NORIHIKO , NUMANO MASAKUNI , HAYASHI YOSHIKI
IPC分类号： H01L21/76 , H01L21/8234 , H01L21/8238 , H01L21/8242 , H01L27/08 , H01L27/088 , H01L27/092 , H01L27/108 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device, preventing crystal defects caused by an embedded element isolation or introduction of impurities. SOLUTION: The semiconductor device is equipped with a semiconductor substrate and a MOS-type semiconductor element formed in the element region of the semiconductor substrate while at least one corner of the element region or the end parts of the same, which are superposed on a gate electrode, are given a concentration of impurities, which is lower than those of the element region. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供一种半导体器件，防止嵌入元件分离或引入杂质引起的晶体缺陷。解决方案：半导体器件配备有半导体衬底和形成在半导体衬底的元件区域中的MOS型半导体元件，而元件区域或其端部的至少一个角是重叠的在栅电极上给出的杂质浓度低于元件区域的浓度。版权所有（C）2004，JPO

5. 发明专利

JPH118298A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH118298A
公开(公告)日：1999-01-12
申请号：JP17128397
申请日：1997-06-13
申请人： TOSHIBA CORP
发明人： OKAYAMA YASUNORI , MATSUOKA FUMITOMO , ISHIMARU KAZUNARI
IPC分类号： H01L21/76 , H01L21/304 , H01L21/3205
摘要： PROBLEM TO BE SOLVED: To reduce scratches by providing a stopper film in a laminated structure that sandwiches, for example, an oxide film on an element formation region as a structure at planarizing. SOLUTION: A first deposited film 33, a second silicon oxide film 34, and a second deposited film 35 constitute a stopper film 3. Then, the second deposition film 35, the second silicon oxide film 34, and the first deposition film 33, the first silicon oxide film 2, and a semiconductor substrate 1 are successively etched, and a groove 5 where a bottom part reaches the inside of the semiconductor substrate 1 is formed. At that time, the depth of the groove 5 is set so that the breakdown voltage among wells becomes sufficiently large electrically, when an embedded element separation region is formed, and the stopper film 3 is a film for protecting the element formation region when flattening the irregularities of an embedded material, thus preventing damages due to scratches which are generated on the semiconductor substrate.

6. 发明专利

JP2005260217A Semiconductor device and manufacturing method of anti-fuse semiconductor device 有权
标题翻译：抗半导体器件的半导体器件及制造方法
公开(公告)号：JP2005260217A
公开(公告)日：2005-09-22
申请号：JP2005034472
申请日：2005-02-10
申请人： Toshiba Corp , 株式会社東芝
发明人： OKAYAMA YASUNORI
IPC分类号： H01L21/82 , H01L27/10
CPC分类号： H01L27/101 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having an anti-fuse section and a memory cell section with excellent programming characteristics and high reliability by securing a current difference before and after programming. SOLUTION: The semiconductor device has a gate insulating film formed on a semiconductor substrate and the anti-fuse section and memory cell section each provided with a MOSFET-type gate capacitor containing a gate electrode formed on the gate insulating film, the depletion rate of the gate electrode in the anti-fuse section is different from that of the gate electrode in the memory cell section, and the depletion rate of the gate electrode in the anti-fuse section is always set lower than that of the gate electrode in the memory cell section. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：通过在编程之前和之后确保电流差来提供具有抗熔丝部分和存储单元部分的半导体器件，其具有优异的编程特性和高可靠性。解决方案：半导体器件具有形成在半导体衬底上的栅极绝缘膜，并且反熔丝部分和存储单元部分均设置有形成在栅极绝缘膜上的包含栅电极的MOSFET型栅极电容器，反熔丝部分中的栅电极的速率与存储单元部分中的栅电极的速率不同，并且反熔丝部分中的栅电极的耗尽率总是设置为低于栅电极的耗尽率存储单元部分。版权所有（C）2005，JPO＆NCIPI

7. 发明专利

JPH11145458A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH11145458A
公开(公告)日：1999-05-28
申请号：JP30713897
申请日：1997-11-10
申请人： TOSHIBA CORP
发明人： OKAYAMA YASUNORI
IPC分类号： H01L21/28 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To prevent short circuits from occurring between a gate electrode and a diffused layer by bridging, to restrain a fine line effect, and to micronize a semiconductor device at the same time. SOLUTION: A semiconductor device is equipped with a gate electrode 207 composed of a silicon layer and a metal silicide layer formed on the surface of the silicon layer, a first insulating film spacer 208 formed on the side of the gate electrode 207, and a second insulating film spacer 211, wherein prif the thicknesses of the first insulating film spacer 208 and the second insulating film spacer 211 are represented by T1 and T2 respectively, T1 and T2 are so set between the two as to satisfy the relations, T1 +T2

8. 发明专利

JPH1187485A SEMICONDUCTOR DEVICE AND FABRICATION THEREOF 失效
公开(公告)号：JPH1187485A
公开(公告)日：1999-03-30
申请号：JP24283097
申请日：1997-09-08
申请人： TOSHIBA CORP
发明人： OKAYAMA YASUNORI , OTANI HIROSHI
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8238
摘要： PROBLEM TO BE SOLVED: To suppress occurrence of punch-through between a well layer and the source-drain diffusion layer of an element region where skirting is induced even upon occurrence of misalignment of well region by suppressing skirting of the trench side wall at the bottom of an isolation trench structurally. SOLUTION: When trenches 2a, 2b are made using RIE method by making oblique the intersection of an isolation region 2b, intersection angle of the trenches 2a, 2b is set such that the gap is intercepted by element regions 7, 8 spaced apart by the trench 2b when the oblique trench 2b is viewed from the direction perpendicular to the well boundary 5 while traversing the trench 2a from on element region 6 extended straightly in the longitudinal direction, thus minimizing the effect on the shape of the side wall of the trench 2a. According to the structure, skirting can be suppressed structurally on the other side of trench in the isolation region 2a even if the isolation trench 2b is present in one side wall of the isolation trench in the isolation region 2a adjacent to the well boundary.

9. 发明专利

JP2011187491A Semiconductor device and method of manufacturing semiconductor device 审中-公开
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：JP2011187491A
公开(公告)日：2011-09-22
申请号：JP2010048123
申请日：2010-03-04
申请人： Toshiba Corp , 株式会社東芝
发明人： OKAYAMA YASUNORI , YASUMOTO AKIHIRO
IPC分类号： H01L29/78 , H01L21/28 , H01L21/8234 , H01L27/088 , H01L29/423 , H01L29/49
CPC分类号： H01L29/78
摘要： PROBLEM TO BE SOLVED: To reduce a gate leak due to an impurity injected into a gate electrode.
SOLUTION: In a region in which a coverage of an active region where a gate electrode 14 is formed is ≥50% and an area thereof is ≥0.02 mm
2 , carbon 15 is introduced into a polycrystalline silicon film 14' and then phosphorus 16 is introduced into the polycrystalline silicon film 14', which is patterned to form the gate electrode 14 on a gate insulating film 13.
COPYRIGHT: (C)2011,JPO&INPIT

10. 发明专利

JP2006100599A Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2006100599A
公开(公告)日：2006-04-13
申请号：JP2004285461
申请日：2004-09-29
申请人： Toshiba Corp , 株式会社東芝
发明人： OKAYAMA YASUNORI , MIYANO KIYOTAKA , ISHIMARU KAZUNARI
IPC分类号： H01L27/092 , H01L21/225 , H01L21/28 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： H01L29/4232 , H01L21/823835 , H01L21/823842 , H01L29/665
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having an Si/SiGe gate electrode structure having appropriately controlled Ge concentration distribution and shape each in a pMOS and an nMOS suited for a fined CMOS semiconductor device.
SOLUTION: The semiconductor device comprises an insulating film formed on a semiconductor substrate; a first gate electrode that is formed on the insulating film and has germanium concentration that is high at an interface to the insulating film, and is low on a surface at the opposite side; and a second gate electrode that is formed on the insulating film, has nearly uniform germanium concentration in the electrode, and has an n-type impurity with a concentration of 6×10
20 atoms/cm
3 or higher.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种具有适当控制的Ge浓度分布和形状的Si / SiGe栅电极结构的半导体器件，每个都具有pMOS和适用于精细CMOS半导体器件的nMOS。解决方案：半导体器件包括形成在半导体衬底上的绝缘膜; 形成在所述绝缘膜上并且在与所述绝缘膜的界面处高的锗浓度并且在相对侧的表面上低的第一栅电极; 并且形成在绝缘膜上的第二栅电极在电极中具有几乎均匀的锗浓度，并且具有浓度为6×10 20原子/ cm 2的n型杂质/ 3 或更高。版权所有（C）2006，JPO＆NCIPI

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