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1. 发明专利

JPH04318962A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH04318962A
公开(公告)日：1992-11-10
申请号：JP5747691
申请日：1991-03-20
申请人： TEXAS INSTRUMENTS INC , HITACHI LTD
发明人： RIMU SHIYAMU BEN , CHIYAI TAI CHIYON , AMAMI MASAZUMI , ANJO ICHIRO , ARITA JUNICHI , TSUBOSAKI KUNIHIRO , ICHITANI MASAHIRO
IPC分类号： H01L23/50 , H01L23/28 , H01L23/29 , H01L23/31 , H01L23/495
摘要： PURPOSE: To provide a technology, wherein reliability of a semiconductor device can be improved. CONSTITUTION: For a semiconductor device sealed up with a mold resin, an insulating tape 4 which electrically insulates an inner lead, comprising a common inner lead 3a2 and plural signal inner leads 3a1 from a semiconductor chip 1 is extruded by a slight amount above the common inner lead 3a2 and the signal inner lead 3a1 . An occurrence of crack on a sealing-up resin and occurrence of a void within a narrow space between the inner lead and the semiconductor chip are prevented, for improved reliability of a semiconductor device.

2. 发明专利

JPH04291950A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH04291950A
公开(公告)日：1992-10-16
申请号：JP5747791
申请日：1991-03-20
申请人： HITACHI LTD , TEXAS INSTRUMENTS INC
发明人： ANJO ICHIRO , ARITA JUNICHI , TSUBOSAKI KUNIHIRO , ICHITANI MASAHIRO , RIMU SHIYAMU BEN , CHIYAI TAI CHIYON , AMAMI MASAZUMI
IPC分类号： H01L23/50
摘要： PURPOSE: To improve the reliability of a semiconductor device by adhering signal inner leads to a circuit-forming surface of a semiconductor chip through an insulating film, having the same-quality polyimide resin applied to both surfaces of an insulating tape base. CONSTITUTION: A plurality of signal inner leads 3A1 are adhered to a circuit- forming surface of a semiconductor chip 1, through an insulating film for electrically insulating the semiconductor chip 1, electrically connected to the chip 1 through bonding wires 5 and sealed with a mold resin 2A. In such a semiconductor device, an insulation film 4 has the same quality polyimide resin applied to the both sides of an insulating tape base and, e.g. is composed of a polyimide resin base of about 50μm and adhesives, contg. the same quality polyimide resin which is applied about 25μm thick to the both surfaces of the base.

3. 发明专利

JPH04291947A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH04291947A
公开(公告)日：1992-10-16
申请号：JP8145191
申请日：1991-03-20
申请人： HITACHI LTD , TEXAS INSTRUMENTS INC
发明人： ANJO ICHIRO , ARITA JUNICHI , TSUBOSAKI KUNIHIRO , ICHITANI MASAHIRO , RIMU SHIYAMU BEN , CHIYAI TAI CHIYON , AMAMI MASAZUMI , DAABUIN EDOWAAZU
IPC分类号： H01L23/29 , H01L21/8242 , H01L23/31 , H01L27/10 , H01L27/108
摘要： PURPOSE: To provide a technology for improving the reliability of a semiconductor device. CONSTITUTION: A semiconductor device is sealed with a mold resin and has a semiconductor chip, having a circuit forming surface onto which inner leads are adhered through an insulating tape 4 for insulating electrically from the semiconductor chip. This chip has a polyimide resin protective film. The protective film absorbs stresses due to the thermal expansion coefficient difference between the semiconductor chip and an insulating film for preventing the surface of the chip from being broken and hence improve the reliability of the semiconductor device. Circuit damages due to a filler in the seal resin can be prevented. The device can be shielded against α-rays from the outside.

4. 发明专利

JPH03173464A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH03173464A
公开(公告)日：1991-07-26
申请号：JP31240189
申请日：1989-12-01
申请人： HITACHI LTD , TEXAS INSTRUMENTS INC
发明人： ANJO ICHIRO , MURAKAMI HAJIME , MAIKERU EI RAMUSON , KEI GEIRU HAINE
IPC分类号： H01L23/50 , H01L23/495
摘要： PURPOSE: To improve cooling efficiency and at the same time simplify the structure of a lead for supporting a chip by forming a drawing lead, that is used for a purpose other than for drawing an electrical signal from an inner lead for common use integrated with the inner lead. CONSTITUTION: A large number of inner leads 3A1 for signal and two inner leads 3A2 for common use are provided in a lead frame. Also, a lead 3A21 for supporting a chip for adhering and fixing the main surface of a semiconductor chip is provided at a specific position of the lead 3A2 . In this manner, by adhering and fixing the main surface of the semiconductor chip by the lead 3A21 , the semiconductor chip is fixed firmly, so that the reliability and moisture resistance of a semiconductor device are enhanced. Also, a dummy lead 3C is provided at a position that corresponds to the center part of a short side, in a rectangular shape of the semiconductor chip of the lead 3A2 . The lead 3C is formed in one piece with the lead 3A2 , thus efficiently radiating heat of a heat generating part to the outside.

5. 发明专利

JP2009218390A Semiconductor device, and manufacturing method thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2009218390A
公开(公告)日：2009-09-24
申请号：JP2008060797
申请日：2008-03-11
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： TANIE HISAFUMI , MORIYA HIROSHI , ANJO ICHIRO , KUSANAGI YOSHITOMO , WATABE MITSUHISA
IPC分类号： H01L25/04 , H01L25/18
CPC分类号： H01L2224/16225 , H01L2224/73253
摘要： PROBLEM TO BE SOLVED: To provide a high-reliability and high-density semiconductor device. SOLUTION: Semiconductor packages 3 on lower tiers are directly mounted on a board 1 to be electrically connected thereto, semiconductor packages 2 on upper tiers are mounted on the board 1 through first spacers 4 to be electrically connected to the board, and the semiconductor packages 2 on the upper tiers and the semiconductor packagers 3 on the lower tiers are different in height from a principal surface of the board 1 and alternately arranged on a first principal surface of the board 1 and a second principal surface on the side opposite to the first principal surface without contacting one another. A part of a semiconductor element 7 constituting the semiconductor package 3 on the lower tier is arranged between a semiconductor element 7 constituting the semiconductor package 2 on the upper tier and the board 1, and a part of the first spacer 4 is arranged between the semiconductor element 7 constituting the semiconductor package 3 on the lower tier and the board 1. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供高可靠性和高密度的半导体器件。解决方案：下层的半导体封装3直接安装在板1上以与其电连接，上层的半导体封装2通过第一间隔件4安装在板1上，以电连接到板，并且上层的半导体封装2和下层的半导体封装器3的高度与板1的主表面高度不同，并且交替地布置在板1的第一主表面上，并且与第一主表面相反的一侧第一主表面没有彼此接触。构成下层的半导体封装3的半导体元件7的一部分配置在构成上层的半导体封装2的半导体元件7和基板1之间，第一间隔物4的一部分配置在半导体元件7构成下层的半导体封装3和板1.版权所有（C）2009，JPO＆INPIT

6. 发明专利

JP2005310837A Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005310837A
公开(公告)日：2005-11-04
申请号：JP2004122011
申请日：2004-04-16
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： WATANABE YUJI , TANIE HISAFUMI , HOSOKAWA KOJI , KATAGIRI MITSUAKI , ANJO ICHIRO
IPC分类号： H01L23/12 , H01L21/60 , H01L23/31 , H01L23/48 , H01L23/498 , H05K3/30 , H05K3/34
CPC分类号： H01L23/49816 , H01L23/3128 , H01L24/81 , H01L2224/81801 , H01L2924/15311 , H05K3/303 , H05K3/3436 , H05K2201/09781 , H05K2201/2036 , Y02P70/613
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which can restrain the breakdown of signal bumps. SOLUTION: The semiconductor device is provided with a semiconductor package 12 including lands allocated in the form of an array and a mounting substrate 11 having lands respectively joined via signal bumps to each land of the semiconductor package 12. Moreover, the semiconductor device also provided with lands 23A formed to one of a mounting substrate 11 and the semiconductor package 12, and dummy bumps 14 joined to the lands 23A. The dummy bumps 14 are not fixed to the other of the semiconductor package 12 and the mounting substrate 11. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供可以抑制信号凸块的击穿的半导体器件。解决方案：半导体器件设置有半导体封装12，其包括以阵列形式分配的焊盘，以及安装基板11，其具有分别经由信号凸块连接到半导体封装12的每个焊盘的焊盘。此外，半导体器件还设置有形成于安装基板11和半导体封装12之一的焊盘23A以及与焊盘23A接合的虚设凸块14。虚设凸块14不固定到半导体封装12和安装基板11中的另一个。版权所有（C）2006，JPO＆NCIPI

7. 发明专利

JP2003142531A METHOD OF MOUNTING SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：JP2003142531A
公开(公告)日：2003-05-16
申请号：JP2002300143
申请日：2002-10-15
申请人： HITACHI LTD
发明人： SUMIYA AKIRO , ANJO ICHIRO , ARITA JUNICHI , KAWAI SUEO , TSUBOSAKI KUNIHIRO , NISHI KUNIHIKO , OTSUKA KENICHI
IPC分类号： H01L23/12 , H01L21/60
摘要： PROBLEM TO BE SOLVED: To provide a technique permitting mounting without improper electrical connection even in the case when the warp of a package is caused, and the visual inspection of the mounting of a ball grid array semiconductor device. SOLUTION: In this mounting method, a ball grid array semiconductor device provided with a plurality of solder bumps on a plane opposite to a plane mounting a semiconductor chip of a substrate is mounted on a mounting substrate, and the central part of the substrate of the ball grid array semiconductor device is warped in such a manner as to project in the direction of the plane opposite to the plane mounting the semiconductor chip at the time of the reflow of solder, so as to electrically connect the electrode on the mounting substrate with the solder bumps.

8. 发明专利

JP2002319635A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD THEREFOR 失效
公开(公告)号：JP2002319635A
公开(公告)日：2002-10-31
申请号：JP2001124475
申请日：2001-04-23
申请人： HITACHI LTD
发明人： MIYAMOTO TOSHIO , ANJO ICHIRO , NISHIMURA ASAO , YAMAGUCHI YOSHIHIDE
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/82 , H01L21/822 , H01L21/8242 , H01L23/12 , H01L23/31 , H01L23/525 , H01L27/04 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To improve flexibility in the layout of re-wiring at a wafer level CSP which saves a defect, by disconnecting a fuse. SOLUTION: After the defect has been relieved by having the fuse irradiated with a laser beam, an organic passiation film (photosensitive polyimide resin film) 5 is filled inside a fuse opening hole part 11 and thereafter, the re-wiring 2, a bump land 2A, a top layer protective film 12 and a solder bump 14 are formed on the upper part of the organic passivation film 5. In the processes after the defect has been saved, in order to prevent the dispersion of the refreshing time of a memory cell, a baking processing for hardening an elastomer layer 10 and the top layer protective film 12 is conducted at a temperature

9. 发明专利

JP2002016180A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2002016180A
公开(公告)日：2002-01-18
申请号：JP2000333527
申请日：2000-10-27
申请人： HITACHI LTD
发明人： YAMAGUCHI YOSHIHIDE , TENMYO HIROYUKI , INOUE KOSUKE , DAIROKU NORIYUKI , HOZOJI HIROYUKI , MINAGAWA MADOKA , TSUNODA SHIGEHARU , ISADA NAOYA , ANJO ICHIRO , NISHIMURA ASAO , UJIIE KENJI , YAJIMA AKIRA
IPC分类号： H01L23/12 , H01L21/60
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device for enabling flip chip connection without the need of an underfill. SOLUTION: This semiconductor device is provided with a first insulation layer formed on a semiconductor element, a second insulation layer formed on the first insulation layer, a first external connection terminal arranged at the flat part of the second insulation layer and a second external connection terminal arranged at the inclined part of the second insulation layer.

10. 发明专利

JP2002016178A SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR 失效
公开(公告)号：JP2002016178A
公开(公告)日：2002-01-18
申请号：JP2000333528
申请日：2000-10-27
申请人： HITACHI LTD
发明人： YAMAGUCHI YOSHIHIDE , TENMYO HIROYUKI , INOUE KOSUKE , DAIROKU NORIYUKI , HOZOJI HIROYUKI , TSUNODA SHIGEHARU , ISADA NAOYA , MINAGAWA MADOKA , ANJO ICHIRO , NISHIMURA ASAO , UJIIE KENJI , YAJIMA AKIRA
IPC分类号： H01L23/29 , H01L21/56 , H01L21/60 , H01L23/12 , H01L23/31
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device for enabling flip chip connection without the need of an underfill. SOLUTION: This semiconductor device is provided with a semiconductor element, an insulation layer formed by mask-printing an insulation material containing particles on the semiconductor element and an external connection terminal formed on the insulation layer and electrically connected to an electrode provided on the semiconductor element.

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