专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2005268575A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2005268575A
公开(公告)日：2005-09-29
申请号：JP2004079791
申请日：2004-03-19
申请人： Elpida Memory Inc , Hitachi Ltd , Renesas Eastern Japan Semiconductor Inc , Renesas Technology Corp , エルピーダメモリ株式会社 , 株式会社ルネサステクノロジ , 株式会社ルネサス東日本セミコンダクタ , 株式会社日立製作所
发明人： TANIE HISAFUMI , KATAGIRI MITSUAKI , WATANABE YUJI , NAKAMURA ATSUSHI , SATO TOMOHIKO
IPC分类号： H05K1/02 , H01L21/56 , H01L21/60 , H01L23/12 , H01L23/31 , H01L23/48 , H01L25/065 , H01L25/10 , H01L25/18 , H05K1/11 , H05K3/34
CPC分类号： H05K1/111 , H01L21/563 , H01L23/3114 , H01L24/48 , H01L25/0657 , H01L25/105 , H01L2224/32225 , H01L2224/48091 , H01L2224/73203 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/06565 , H01L2924/00014 , H01L2924/01087 , H01L2924/15311 , H01L2924/181 , H05K2201/09281 , H05K2201/094 , H05K2201/10734 , Y02P70/611 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： PROBLEM TO BE SOLVED: To realize large capacity, high function, and space reduction by improving the reliability of a connection part between a semiconductor package and a mounting substrate to a thermal load in a semiconductor device.
SOLUTION: The semiconductor device 1 has the semiconductor package 2 and the mounting substrate 5 with a land 8 electrically connected to the semiconductor package 2 via a solder bump 4. A plurality of lines wherein a plurality of lands 8 are arranged are formed in the mounting substrate 5. At least one of the lands 8 constituting a line which is located in a nearest side to a main side constituting a semiconductor package outer edge has wiring 9 extending along the mounting substrate surface from the land 8. The wiring 9 is formed so that a connection part to the land 8 is positioned on a side close to a line which is orthogonal to the line at the center of the land 8 than a line connecting from the center of the land 8 to the center of the semiconductor package 2.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：通过将半导体封装和安装基板之间的连接部分的可靠性提高到半导体器件中的热负载来实现大容量，高功能和空间减小。解决方案：半导体器件1具有半导体封装2和安装基板5，其具有通过焊料凸块4电连接到半导体封装2的焊盘8.形成有多个焊盘8布置的多条线构成位于构成半导体封装外边缘的主要侧的最靠近的一行的焊盘8中的至少一个具有沿着安装基板表面从焊盘8延伸的布线9.布线9 形成为使得与焊盘8的连接部分位于靠近与焊盘8的中心处的线垂直的线的一侧，而不是从焊盘8的中心到半导体的中心连接的线包装2.版权所有（C）2005，JPO＆NCIPI

2. 发明专利

JP2005244143A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2005244143A
公开(公告)日：2005-09-08
申请号：JP2004055630
申请日：2004-03-01
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： TANIE HISAFUMI , KUNO NAE , OTA HIROYUKI , IKEDA HIROAKI , ANJO ICHIRO , KATAGIRI MITSUAKI , WATANABE YUJI
IPC分类号： H01L25/18 , H01L23/48 , H01L25/065 , H01L25/07 , H01L25/10
CPC分类号： H01L25/0657 , H01L23/481 , H01L24/48 , H01L2224/05573 , H01L2224/05647 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48472 , H01L2224/73204 , H01L2225/06513 , H01L2225/0652 , H01L2225/06541 , H01L2225/06589 , H01L2225/06593 , H01L2924/00014 , H01L2924/01019 , H01L2924/01079 , H01L2924/01087 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/15312 , H01L2924/181 , H01L2924/19041 , H01L2924/19105 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device where a temperature rise at the time of an operation can be reduced. SOLUTION: An interface chip 2 is laminated on a plurality of laminated semiconductor elements 1. An Si interposer 3 and a resin interposer 4 are arranged below a plurality of the semiconductor elements 1. The Si interposer 3 is arranged between the resin interposer 4, and a plurality of semiconductor elements 1 is thicker than the semiconductor element 1; and moreover has a coefficient of linear expansion which is smaller than that of the resin interposer 4 and larger than that of a plurality of the semiconductor elements 1. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供可以减少操作时的温度上升的半导体器件。解决方案：在多个层叠半导体元件1上层叠界面芯片2.在多个半导体元件1的下方配置有Si插入体3和树脂插入体4.Si中介层3配置在树脂插入体 4，多个半导体元件1比半导体元件1厚; 而且具有小于树脂插入件4的线膨胀系数，并且大于多个半导体元件1的线性膨胀系数。（C）2005，JPO＆NCIPI

3. 发明专利

JP2005310837A Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005310837A
公开(公告)日：2005-11-04
申请号：JP2004122011
申请日：2004-04-16
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： WATANABE YUJI , TANIE HISAFUMI , HOSOKAWA KOJI , KATAGIRI MITSUAKI , ANJO ICHIRO
IPC分类号： H01L23/12 , H01L21/60 , H01L23/31 , H01L23/48 , H01L23/498 , H05K3/30 , H05K3/34
CPC分类号： H01L23/49816 , H01L23/3128 , H01L24/81 , H01L2224/81801 , H01L2924/15311 , H05K3/303 , H05K3/3436 , H05K2201/09781 , H05K2201/2036 , Y02P70/613
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which can restrain the breakdown of signal bumps. SOLUTION: The semiconductor device is provided with a semiconductor package 12 including lands allocated in the form of an array and a mounting substrate 11 having lands respectively joined via signal bumps to each land of the semiconductor package 12. Moreover, the semiconductor device also provided with lands 23A formed to one of a mounting substrate 11 and the semiconductor package 12, and dummy bumps 14 joined to the lands 23A. The dummy bumps 14 are not fixed to the other of the semiconductor package 12 and the mounting substrate 11. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供可以抑制信号凸块的击穿的半导体器件。解决方案：半导体器件设置有半导体封装12，其包括以阵列形式分配的焊盘，以及安装基板11，其具有分别经由信号凸块连接到半导体封装12的每个焊盘的焊盘。此外，半导体器件还设置有形成于安装基板11和半导体封装12之一的焊盘23A以及与焊盘23A接合的虚设凸块14。虚设凸块14不固定到半导体封装12和安装基板11中的另一个。版权所有（C）2006，JPO＆NCIPI

4. 发明专利

JP2007305846A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2007305846A
公开(公告)日：2007-11-22
申请号：JP2006133663
申请日：2006-05-12
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： HOSOKAWA KOJI , WATANABE YUJI
IPC分类号： H01L25/10 , H01L25/11 , H01L25/18
CPC分类号： H01L23/4985 , H01L25/0657 , H01L2225/06517 , H01L2225/0652 , H01L2225/06555 , H01L2225/06572 , H01L2924/0002 , H01L2924/15311 , H01L2924/15331 , H01L2924/3511 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device by which resistance to mounting temperature cycle of upper and lower connecting terminals can be improved.
SOLUTION: The semiconductor device has a mother board 3, a lower stage package 2 which is stacked on the mother board 3, and an upper stage package 1 which is stacked on the lower stage package 2 through the upper and lower connecting terminals 11. A marginal part 50 of a peripheral border region of an interposer 6 of the lower stage package 2 which is overlapped by the upper and lower connecting terminals 11 is in immediate contact with the mother board 3.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够提高上下连接端子的安装温度循环的耐受性的半导体装置。解决方案：半导体器件具有母板3，堆叠在母板3上的下级封装2和通过上下连接端子层叠在下级封装2上的上级封装1 与上下连接端子11重叠的下层包装2的插入件6的外围边界区域的边缘部分50与母板3立即接触。（C） 2008年，JPO＆INPIT

5. 发明专利

JP2013157433A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2013157433A
公开(公告)日：2013-08-15
申请号：JP2012016408
申请日：2012-01-30
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： WATANABE YUJI
IPC分类号： H01L23/12 , H01L25/10 , H01L25/11 , H01L25/18
CPC分类号： H01L24/97 , H01L24/73 , H01L2224/16225 , H01L2224/32225 , H01L2224/48227 , H01L2224/48465 , H01L2224/49175 , H01L2224/73204 , H01L2224/73265 , H01L2224/97 , H01L2924/15311 , H01L2924/15321 , H01L2924/181 , H01L2924/1815 , H01L2924/00012 , H01L2224/85 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that allows suppressing an increase in size of the device and improving reliability.SOLUTION: A semiconductor device 1 includes: a wiring substrate 10; a semiconductor chip 2 mounted on one surface of the wiring substrate 10; a ball-shaped connection electrode 3 mounted on a region, on which the semiconductor chip 2 is not mounted, of the one surface of the wiring substrate 10 and for electrically connecting the semiconductor device 1 to the outside; and an insulating resin layer 7 formed on the substantially entire surface of the one surface of the wiring substrate 10, covering the entirety of the semiconductor chip 2, and partially covering the connection electrode 3 so that the connection electrode 3 is exposed from a surface of the insulating resin layer 7.
摘要翻译：要解决的问题：提供一种允许抑制装置的尺寸增加并提高可靠性的半导体装置。解决方案：半导体装置1包括：布线基板10; 安装在布线基板10的一个表面上的半导体芯片2; 安装在其上未安装半导体芯片2的区域上的球形连接电极3，并且将半导体器件1电连接到外部; 以及形成在布线基板10的一个表面的大致整个表面上的绝缘树脂层7，覆盖整个半导体芯片2，并且部分地覆盖连接电极3，使得连接电极3从绝缘树脂层7。

6. 发明专利

JP2010153466A Wiring board 审中-公开
标题翻译：接线板
公开(公告)号：JP2010153466A
公开(公告)日：2010-07-08
申请号：JP2008327641
申请日：2008-12-24
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： WATANABE YUJI
IPC分类号： H01L21/56 , H01L23/12
CPC分类号： H05K3/284 , H01L21/561 , H01L21/565 , H01L23/3128 , H01L23/49827 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/97 , H01L2224/05554 , H01L2224/32225 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/49171 , H01L2224/73265 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/07802 , H01L2924/10162 , H01L2924/15311 , H01L2924/181 , H05K1/0271 , H05K3/0052 , H05K3/0097 , H05K2201/09063 , H05K2203/1316 , H01L2224/85 , H01L2924/00012 , H01L2924/00 , H01L2224/45015 , H01L2924/207
摘要： PROBLEM TO BE SOLVED: To prevent a wiring board from being strained owing to thermal expansion resulting from heating in molding by a transfer mold, stress generated by being clamped between an upper die and a lower die of a molding die, etc. SOLUTION: There is provided the wiring board 1A which is arranged in the cavity of the molding die in a state in which semiconductor chips are mounted on a plurality of product formation parts 7, and in which a sealing body covering the plurality of product formation parts together is formed, wherein two or more slits 8 are formed in an area which abuts on the molding die. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了防止布线板由于通过转印模具的模制加热而导致的热膨胀而变形，通过夹在模具的上模和下模之间产生的应力等解决方案：在半导体芯片安装在多个产品形成部件7上的状态下，设置布置在成型模具的空腔中的布线板1A，并且其中覆盖多个形成产品形成部分，其中在邻接成型模具的区域中形成有两个或更多个狭缝8。版权所有（C）2010，JPO＆INPIT

7. 发明专利

JP2012094592A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2012094592A
公开(公告)日：2012-05-17
申请号：JP2010238648
申请日：2010-10-25
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： WATANABE YUJI
IPC分类号： H01L23/34 , H01L23/12 , H01L23/28
CPC分类号： H01L23/3677 , B29C45/14065 , B29C45/14655 , B29C45/14827 , B29C2045/14663 , H01L21/565 , H01L21/566 , H01L23/3121 , H01L23/3128 , H01L23/4334 , H01L24/45 , H01L24/48 , H01L24/97 , H01L25/0657 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/48228 , H01L2224/48465 , H01L2224/73203 , H01L2224/73204 , H01L2224/73265 , H01L2224/85207 , H01L2224/92247 , H01L2224/97 , H01L2225/06506 , H01L2225/0651 , H01L2225/06562 , H01L2225/06589 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01038 , H01L2924/01079 , H01L2924/014 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2224/83 , H01L2224/85 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a structure for preventing generation of failures caused by deformation of a heat radiation plate.SOLUTION: A semiconductor device 10 has: a substrate; a semiconductor chip mounted on the substrate; a sealing body 13 sealing the semiconductor chip on the substrate; and a plurality of heat radiation plates 14 buried in the sealing body 13 at intervals so that the respective one surfaces are exposed to exterior and located on the same plane. In addition, a method of manufacturing the semiconductor device 10 includes the following steps of: arranging the substrate and the plurality of heat radiation plates 14 in a mold so as to be opposed to each other; and injecting a melted sealing resin into between those to seal the chip onto the substrate and integrate the plurality of heat radiation plates 14 with the sealing resin.
摘要翻译：要解决的问题：提供一种用于防止由放热板的变形引起的故障的产生的结构。解决方案：半导体器件10具有：衬底; 安装在基板上的半导体芯片; 将半导体芯片密封在基板上的密封体13; 以及间隔地埋在密封体13中的多个散热板14，使得各个表面暴露于外部并位于同一平面上。另外，制造半导体器件10的方法包括以下步骤：将基板和多个散热板14布置在模具中以彼此相对; 并将熔融的密封树脂注入到将芯片密封到基板上的熔融密封树脂之间，并将多个散热板14与密封树脂相结合。版权所有（C）2012，JPO＆INPIT

8. 发明专利

JPH10200018A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURING METHOD 失效
公开(公告)号：JPH10200018A
公开(公告)日：1998-07-31
申请号：JP344797
申请日：1997-01-13
申请人： HITACHI LTD
发明人： YAMAGUCHI EIJI , WATANABE YUJI
IPC分类号： H01L23/12 , H01L21/56 , H01L23/02 , H01L23/29
摘要： PROBLEM TO BE SOLVED: To improve heat-radiation characteristics and connection-reliability of a heat radiation member jointed to a semiconductor element, by covering a semiconductor element supported on an element mounting substrate with a heat radiation member, and, when resin-sealing the joint part between the semiconductor element and the element mounting substrate, supplying a sealing resin through a through hole of a heating member. SOLUTION: A semiconductor element 1 is supported on an element mounting substrate 2, and a joint part 4 between the semiconductor element 1 and the element mounting substrate 2 is sealed up with a sealing resin 5. Further, a heat radiation member 6 where, comprising a recessed part 6a where an element joint part 6b jointed to a rear surface 1a of the semiconductor element 1, a through hole 6c whose one end is opened near the element joint part 6b of the recessed part 6a with the other end opened outside is provided, is provided. When the sealing-resin 5 is supplied to the joint part 4 between the semiconductor element 1 and the element mounting substrate 2, the sealing resin 5 is supplied through the through hole 6c. The heat radiation member 6, for example, is formed by press-working with aluminum or aluminum alloy.

9. 发明专利

JPH08195463A RESIN SEALED SEMICONDUCTOR DEVICE AND LEAD FRAME BEING EMPLOYED IN PRODUCTION THEREOF 失效
公开(公告)号：JPH08195463A
公开(公告)日：1996-07-30
申请号：JP495395
申请日：1995-01-17
申请人： HITACHI LTD
发明人： NOSE FUJIAKI , WATANABE YUJI , SAITO YOSHIKI , KIKUCHI TAKU , HOZOJI HIROYUKI , HONDA ATSUSHI
IPC分类号： H01L21/56 , H01L23/50
摘要： PURPOSE: To enhance heat dissipation efficiency and the thermal reliability of a resin sealed semiconductor device. CONSTITUTION: The resin sealed semiconductor device comprises a tab suspension lead, a tab 2C integrated with the tab suspension lead, a semiconductor pellet 1 mounted on the pellet mounting face of the tab 2C, and an inner lead 2A connected electrically with the outer terminal of the semiconductor pellet 1, all of which are sealed with a resin sealing body 4. Thickness t1 of the tab 2C is set thicker than the thickness t2 of the inner lead 2A and the rear surface of the tab 2C, facing the pellet mounting face, is exposed from the surface of the resin sealing body 4. The lead frame comprises the inner lead 2A integrated with a frame body, the tab 2C, and the tab suspension lead, wherein the thickness t1 of the tab 2C is set thicker than the thickness t2 of the inner lead 2A.

10. 发明专利

JPH09139457A SEMICONDUCTOR DEVICE AND LEAD FRAME USED FOR THE MANUFACTURE OF THE DEVICE 失效
公开(公告)号：JPH09139457A
公开(公告)日：1997-05-27
申请号：JP29636395
申请日：1995-11-15
申请人： HITACHI LTD
发明人： WATANABE YUJI , KIKUCHI TAKU , HOZOJI HIROYUKI
IPC分类号： H01L23/28 , H01L21/56 , H01L23/50
摘要： PROBLEM TO BE SOLVED: To improve reflow-crack resistance of surface-mount semiconductor device. SOLUTION: A semiconductor device is comprised of a molded-resin package 2, a lead 3 extending inside an outside the package 2, die pads 5 sealed in the package 2, a semiconductor chip 4 fixed on the die pads 5 through die bonding material 6, and connecting means which connects the ends of the lead 3 and electrodes of the semiconductor chip 4. Die pads 5 consist of several bonding portions 7 facing parts of the semiconductor chip 4 and narrow coupling portions 8 which interconnect the bonding portions 7. The semiconductor chip 4 is fixed to the bonding portions 7 through die bonding material 6. Four bonding portions 7 are provided in positions corresponding to the four corners of the semiconductor chip 4. The surface of the semiconductor chip 4 bonded through the bonding portions 7 occupies about 20 to 30% of the whole surface of the semiconductor chip 4.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式