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1. 发明专利

JP2009194143A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2009194143A
公开(公告)日：2009-08-27
申请号：JP2008033008
申请日：2008-02-14
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： KOYAMA HIROSHI , TSUNODA SHIGEHARU , AMANO YASUO , MATSUSHIMA NAOKI , YAMAGUCHI MASAHIRO , SAWAYAMA EMI
IPC分类号： H01L23/12
CPC分类号： H01L25/0657 , H01L23/5387 , H01L24/48 , H01L24/50 , H01L24/93 , H01L2224/0401 , H01L2224/05644 , H01L2224/78313 , H01L2225/06579 , H01L2924/00014 , H01L2924/01006 , H01L2924/01015 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/15311 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： PROBLEM TO BE SOLVED: To provide a wiring pattern for realizing the ultrasonic bonding of a flexible board and a base board, without the dispersion of a bonding strength, without having to depend on the wiring pattern for the base board. SOLUTION: Deformations of wirings 11 on the base board 12 are adjusted in ultrasonic bonding, the dispersions of joining properties at each electrode are eliminated, by equalizing relative rigidities at each wiring, and a semiconductor laminated package having a high reliability on connections can be realized. When the direction of ultrasonic vibration runs parallel with the direction of extending the wirings, the wirings extended from the lower sections of the electrodes restrain the deformations of jointing sections, and loss of ultrasonic energy is suppressed; and the differences in the relative rigidities of the jointing sections are reduced, by thinning line widths in long wirings and thickening them in short wirings. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了提供用于实现柔性板和基板的超声波接合的布线图案，而不需要依赖于基板的布线图案而不会发生接合强度的分散。解决方案：在超声波接合中调整基板12上的布线11的变形，通过均衡各布线的相对刚性以及在连接上具有高可靠性的半导体层叠封装来消除每个电极处的接合性能的分散可以实现。当超声波振动方向与电线延伸方向平行时，从电极下部延伸的布线限制接合部分的变形，抑制超声能量的损失; 并且通过在长布线中减少线宽并且在短布线中使它们变厚，减小了接合部的相对刚度的差异。版权所有（C）2009，JPO＆INPIT

2. 发明专利

JP2000195986A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JP2000195986A
公开(公告)日：2000-07-14
申请号：JP37032698
申请日：1998-12-25
申请人： HITACHI LTD
发明人： HOZOJI HIROYUKI , TSUNODA SHIGEHARU , SERIZAWA KOJI , SAEKI JUNICHI
IPC分类号： H05K1/18 , H01L21/60 , H01L23/12
摘要： PROBLEM TO BE SOLVED: To make the terminals of a semiconductor device difficult to deform before the mounting and make them relax its mounting stress after the mounting, by connecting with its respective electrodes arranged in an area-array form annular terminals for connecting with the electrodes of a mounting board its respective electrodes arranged in an area-array form. SOLUTION: A semiconductor element 1 is mounted on a circuit board 2 for connecting it electrically with the circuit board 2 by bonding wires 3. On the back surface of the circuit board 2 to its surface of mounting thereon the semiconductor element 1, electrodes 4 used for the connection with a mounting board whereon the semiconductor device is mounted are provided to connect them via solders 5 with terminals 6 formed into annular shape. Furthermore, for protecting the semiconductor element 1 and the connecting portions of the bonding wires 3 with the board 2, the semiconductor element mounting surface of the board 2 is coated with a sealing resin 7, etc. As the metal for forming the annular terminals 6, alloys can be utilized wherein one kind of gold, silver, lead, and so forth or two or more kinds of them are mixed with an alloy made of iron/nickel, and the foregoing alloys subjected to an suitable plating with satisfactory wettable solders can be also utilized.

3. 发明专利

JPH11186453A BGA TYPE SEMICONDUCTOR DEVICE AND MOUNTING STRUCTURAL BODY FOR THE DEVICE 失效
公开(公告)号：JPH11186453A
公开(公告)日：1999-07-09
申请号：JP35790997
申请日：1997-12-25
申请人： HITACHI LTD
发明人： HOZOJI HIROYUKI , TSUNODA SHIGEHARU , SAEKI JUNICHI , KANEMITSU NOBUYA , HARUTA AKIRA , SATO TOSHIYA , TANAKA TADAYOSHI , NAGAI AKIRA
IPC分类号： H01L21/60 , H01L23/12
摘要： PROBLEM TO BE SOLVED: To provide a BGA type semiconductor device whose mounting on a mounting substrate or whose repair work can be easily attained, and the mounting structural body. SOLUTION: A BGA type semiconductor device is provided with a flexible substrate 2 whose surface is provided with a wiring pattern 10, and whose central part is opened; semiconductor element 6 arranged in an opening 2b of the flexible substrate 2, and whose surface is provided with an electrode 6a connected with a wiring pattern 10; resin 8 for sealing the surface of the semiconductor element 6 and a terminal area with the electrode 6a in the wiring pattern 10; and a metallic board-shaped body 1 with a difference in level corresponding to a difference in height between the back face of the semiconductor element 6 and the back face of the flexible substrate 2, which is provided with a central high plate-shaped part 1a and a surrounding low plate-shaped part 1b bonded with adhesive between each back face, and an opening at the difference in level part for connecting the central high plate-shaped part 1a with the surrounding plate-shaped part 1b or at the neighboring part of the difference in level part.

4. 发明专利

JPH1022435A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH1022435A
公开(公告)日：1998-01-23
申请号：JP17247096
申请日：1996-07-02
申请人： HITACHI LTD
发明人： TAKAHASHI MASAAKI , OGAWA TOSHIO , YAMADA KAZUJI , AIDA MASAHIRO , KAMIMURA NORITAKA , SUZUKI KAZUHIRO , KOKADO HIROYOSHI , OGINO MASAHIKO , ISHII TOSHIAKI , SAEKI JUNICHI , TSUNODA SHIGEHARU , ENDO TSUNEHIRO , SHIGEMURA TATSUYA , KUMAZAWA TETSUO , NAKATSU KINYA
IPC分类号： H01L21/56 , H01L23/50 , H01L23/52
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and manufacture thereof which enable sufficient improvement in insulating property. SOLUTION: A portion 22 to be an input/output terminal of a lead frame 2 connected with an electronic component, such as, a semiconductor chip 4, is bent and arranged in an upper mold 91 (c). After the portion 22 is resin-sealed, it is pulled up to be an input/output terminal (e), thereby enabling formation of an input/output terminal on the upper surface of a resin layer by a transfer mold method. Thus, even though transfer mold sealing of a thermosetting resin is carried out, a semiconductor device having an input/output terminal on a surface of a base board opposite to a heat sink surface may be easily provided. Therefore, a semiconductor device in which the dielectric strength between the input/output terminal and a cooling fin is significantly improved and which may be applied to a semiconductor module for electric power, such as, an inverter device, may be easily provided.

5. 发明专利

JPH09181107A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH09181107A
公开(公告)日：1997-07-11
申请号：JP1221797
申请日：1997-01-27
申请人： HITACHI LTD
发明人： SAEKI JUNICHI , KANEDA AIZO , TSUNODA SHIGEHARU , YOSHIDA ISAMU , NISHI KUNIHIKO
IPC分类号： B29C45/26 , B29C45/02 , B29C45/14 , B29L31/34 , H01L21/56
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device allowing compatibility of production efficiency and quality improvement. SOLUTION: On a metal mold consisting of a plurality of pots 2 for pressure- supplying, for instance, molding resin, an interconnection path 10 interconnecting the pots 2 and a plurality of cavities 5, 7, 9 arranged in series, a lead frame 11 whereon a plurality of tabs mounting semiconductor chips are arranged in the length-to-width directions respectively. Then, resin is thrown into the pots 2 and the pots 2 are pressed by a plurality of plungers 17 so as to inject resin into the cavities 5, 7, 9 inside a metal mold. In this way, productivity of resin-molded semiconductors and sharp improvement in the product quality can be made compatible.

6. 发明专利

JPH07283256A RESIN SEALING METHOD OF SEMICONDUCTOR PART 失效
公开(公告)号：JPH07283256A
公开(公告)日：1995-10-27
申请号：JP6830794
申请日：1994-04-06
申请人： HITACHI LTD
发明人： SAEKI JUNICHI , YOSHII MASAKI , OJI KAZUYA , TSUNODA SHIGEHARU , YOSHIDA ISAMU , IMURA KENICHI , SUMIYA AKIRO
IPC分类号： B29C45/33 , B29C45/14 , B29C45/38 , B29L31/34 , H01L21/56
摘要： PURPOSE:To provide a technique capable of ensuring the reliability of a product and enhancing a sealing operation in efficiency in a resin sealing process wherein the one side of a circuit board mounted with a semiconductor is sealed up with resin by a mold. CONSTITUTION:A mold is composed of an upper mold 8, a lower mold 10, and a slide block 11 which slides on a prescribed part of the lower mold 10. A circuit board 1 is fixed to the slide block 11, and a gate is formed on the upper mold 8 so as not, to come into contact with the circuit board 1. After an injection of rosin is finished, the slide block 11 and a product ejector pin 25 of the lower die 10 are moved interlocking with each other, whereby the above purpose can be attained. By this setup, the reliability of a product can be ensured, and a molding operation can be improved in efficiency.

7. 发明专利

JPH06320574A POSITION ANALYZING DEVICE FOR INSERT STRUCTURE IN RESIN SEALING MOLDING MACHINE, METHOD AND APPARATUS FOR CONTROLLING POSITION OF INSERT STRUCTURE IN RESIN SEALING MOLDING MACHINE, INSERT STRUCTURE RESIN SEAL PART AND PRODUCTION THEREOF 失效
公开(公告)号：JPH06320574A
公开(公告)日：1994-11-22
申请号：JP422694
申请日：1994-01-19
申请人： HITACHI LTD
发明人： OJI KAZUYA , SAEKI JUNICHI , TSUNODA SHIGEHARU , YOSHIDA ISAMU , NISHI KUNIHIKO , ARITA JUNICHI
IPC分类号： B29C45/02 , B29C45/14 , B29C45/17 , B29C45/26 , B29C45/76 , B29K105/20 , B29L31/34 , H01L21/56
摘要： PURPOSE:To produce a good insert structure by analyzing the displacement of the insert structure in a cavity to hold the insert structure to a prescribed position. CONSTITUTION:Since the position of an insert structure I is calculated at respective times when the mold having the insert structure I set thereto is clamped, the transfer to a resin 7 is started, the inflow of the resin 7 into a cavity 11 is started and the filling of the cavity 11 with the resin 7 is completed, the displacement mechanism of the structure I can be clearly analyzed. Therefore, a measure to prevent the displacement of the structure I can be obtained and the structural planning and conditional setting of the structure I and the mold can be rationally performed.

8. 发明专利

JPH0679096B2 失效
公开(公告)号：JPH0679096B2
公开(公告)日：1994-10-05
申请号：JP24639385
申请日：1985-11-05
申请人： HITACHI LTD
发明人： HYOSHI YASUO , SATO HIDEMI , KANEDA AIZO , TSUNODA SHIGEHARU
IPC分类号： G02B6/13 , G02B6/12

9. 发明专利

JPS63113506A MANUFACTURE OF THIN FILM DIFFRACTION GRATING 失效
公开(公告)号：JPS63113506A
公开(公告)日：1988-05-18
申请号：JP25823386
申请日：1986-10-31
申请人： HITACHI LTD
发明人： SATO HIDEMI , HIYOSHI YASUO , KANEDA AIZO , TSUNODA SHIGEHARU
IPC分类号： G02B6/122 , G02B6/124
摘要： PURPOSE:To realize a high stabilization by a high diffraction efficiency by forming a chalcogenide glass layer on a substrate, radiating an electron beam onto a metallic thin film formed on said layer and forming periodically a metallic diffusion layer to a desired depth from an interface which comes into contact with the metallic thin film, and providing a refractive index distribution. CONSTITUTION:A chalcogenile glass layer 3 is formed on a substrate 1, a metallic thin film 4 is formed on said layer, and by radiating an electron beam 5 onto said film, a metallic diffusion layer is formed periodically extending over a desired depth from an interface which comes into contact with the metallic thin film of the chalcogenide glass layer, and a refractive index distribution is provided. A refractive index of the substrate is 3.4-3.5, 3.3-3.6, 2.1-2.6 and 1.3-2.0, in case of silicon, a semiconductor or GaAs, etc., an optical crystal of LiNbO3, etc., and silica compound glass, respectively, and a refractive index of the chalcogenide glass layer is 2.1-3.1. When the refractive index of the substrate which comes into contact with the chalcogenide glass is smaller than that of the chalcogenide glass, light can be confined in the chalcogenide glass being a waveguide layer.

10. 发明专利

JPS6126225B2 JPS6126225B2 - 失效
公开(公告)号：JPS6126225B2
公开(公告)日：1986-06-19
申请号：JP6335884
申请日：1984-04-02
申请人： Hitachi Ltd
发明人： KANEDA AIZO , TSUNODA SHIGEHARU , OOTSUKI KEIZO , NAKAGAWA TAKASHI , AOKI MASAYOSHI
IPC分类号： H01L23/28 , B29C45/14 , B29C45/37 , H01L21/56
CPC分类号： B29C45/372 , B29C45/14655 , H01L21/565 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2924/1815 , H01L2924/00014 , H01L2924/00
摘要： PURPOSE:To prevent the generation of cracks by a method wherein the semiconductor pellet connected to a lead frame is sealed by the resin having a satin surface, thereby enabling to reduce mold-releasing force. CONSTITUTION:The whole surface of the cavity 8b, consisting of a top force 1b and a bottom force 2b which will be used to resin-seal a semiconductor plastic package, consists of a smoothly-formed uneven satin surface. The semiconductor pellet 10, which is mounted on a lead frame 9 and connected to the lead frame 9 by a gold wire 11, is arranged in the cavity 8b, fused resin is filled in the cavity 8b and hardened there.

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