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1. 发明专利

JP2013045780A Semiconductor device and manufacturing method of the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2013045780A
公开(公告)日：2013-03-04
申请号：JP2011180096
申请日：2011-08-22
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： MINAGAWA MADOKA , ISADA NAOYA , SAKAMA ISAO , SAGAWA SHIGERU , SHIBATA DAISUKE
IPC分类号： H01L23/00 , G06K19/07 , G06K19/077
CPC分类号： H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/92125 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To inhibit discharge from a chip back face at the time of mounting a semiconductor chip, and inhibit discharge from a back face, end faces, edges and vertexes of a semiconductor against charging after completion of the mounting thereby to reduce damages of the semiconductor.SOLUTION: A semiconductor device manufacturing method comprises a dicing process of forming a hardened resin layer on a back face of a semiconductor chip to provide a structure protruding from a semiconductor. By bonding the semiconductor chip and wiring in this state, electrostatic discharges, which penetrate the semiconductor chip is prevented. In addition, an underfill resin wets up to the protruded part to cover a back face, end faces, edges and vertexes of the semiconductor thereby to prevent electrostatic discharges.
摘要翻译：要解决的问题：为了在安装半导体芯片时抑制从芯片背面的放电，并且在安装完成之后禁止半导体的背面，端面，边缘和顶点与充电的放电以减少半导体的损坏。解决方案：半导体器件制造方法包括在半导体芯片的背面上形成硬化树脂层的切割工艺，以提供从半导体突出的结构。通过在这种状态下结合半导体芯片和布线，可以防止穿透半导体芯片的静电放电。此外，底部填充树脂直到突出部分润湿以覆盖半导体的背面，端面，边缘和顶点，从而防止静电放电。版权所有（C）2013，JPO＆INPIT

2. 发明专利

JP2009093507A Rfid tag 审中-公开
标题翻译： RFID标签
公开(公告)号：JP2009093507A
公开(公告)日：2009-04-30
申请号：JP2007265071
申请日：2007-10-11
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： ISADA NAOYA , DAIROKU NORIYUKI
IPC分类号： G06K19/10 , B42D15/10 , G06K19/07 , G06K19/077
CPC分类号： G06K19/07749 , G06K19/07775 , G06K19/07779 , G06K19/07798
摘要： PROBLEM TO BE SOLVED: To intercept radio communication between an RFID chip and an external terminal positively when a seal type RFID tag including the RFID chip is peeled from an adherend for protecting information stored in an RFID chip and ensuring its genuineness, while ensuring solidity when the RFID tag is put on the adherend. SOLUTION: In the seal type RFID tag which includes the RFID chip fixed to the mounting surface of a base member having an adhesive layer applied thereto and which is put on the adherend by using the adhesive layer, an antenna formed on the main surface of the RFID chip is embedded in the adhesive layer together with the RFID chip, and adhesive bonding strength between the antenna and the adhesive layer is made greater than joining strength between the antenna and the RFID chip. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：当包括RFID芯片的密封型RFID标签从用于保护存储在RFID芯片中的信息的被粘物体剥离并确保其真实性时，可以肯定地拦截RFID芯片和外部终端之间的无线电通信，同时确保将RFID标签放在被粘物上时的牢固性。解决方案：在包括RFID芯片的密封型RFID标签中，固定到具有施加到其上的粘合剂层的基底构件的安装表面并且通过使用粘合剂层放置在被粘物上的RFID标签，形成在主体上的天线 RFID芯片的表面与RFID芯片一起嵌入粘合剂层中，并且天线和粘合剂层之间的粘合强度大于天线和RFID芯片之间的接合强度。版权所有（C）2009，JPO＆INPIT

3. 发明专利

JP2008217384A Circuit chip, manufacturing method thereof, and rfid circuit device on which the circuit chip is mounted 审中-公开
标题翻译：电路芯片及其制造方法以及安装电路芯片的RFID电路装置
公开(公告)号：JP2008217384A
公开(公告)日：2008-09-18
申请号：JP2007053615
申请日：2007-03-05
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： DAIROKU NORIYUKI , ISADA NAOYA
IPC分类号： G06K19/077 , G06K19/07
摘要： PROBLEM TO BE SOLVED: To suppress the occurrence of breakage or fracture of a circuit chip by a "microcrack of an outer edge of a substrate" that is liable to occur in a circuit chip (semiconductor chip) cut out from a semiconductor wafer by dicing or the like. SOLUTION: The principal surface of a semiconductor substrate of a circuit chip is formed in such a manner that the direction that the contour extending in the principal surface changes only through a curved line so that the occurrence of a ridge-like line on the lateral side of the semiconductor substrate is suppressed, and an impact made to the principal surface and the lateral side of the semiconductor substrate is dispersed over the whole semiconductor substrate. A dry-etching method is used for the process to cut out the semiconductor substrates from the semiconductor wafer to suppress a slant of the lateral side. The shape of the structure and the arrangement of an electrical circuit formed on the principal surface of the semiconductor substrate and electrodes to be connected to the electrical circuit are optimized adapting to the shape of the principal surface. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题为了通过在从半导体切出的电路芯片（半导体芯片）中容易发生的“基板的外边缘的微裂纹”来抑制电路芯片的断裂或断裂的发生通过切片等进行晶片化。解决方案：电路芯片的半导体衬底的主表面以这样一种方式形成，使得在主表面上延伸的轮廓的方向仅通过曲线改变，使得出现脊状线半导体衬底的侧面被抑制，并且对半导体衬底的主表面和横向侧的冲击分散在整个半导体衬底上。干蚀刻方法用于从半导体晶片切出半导体衬底以抑制侧面倾斜的工艺。在半导体衬底的主表面上形成的电路的结构形状和电路的布置以及要连接到电路的电极的最优化适应于主表面的形状。版权所有（C）2008，JPO＆INPIT

4. 发明专利

JP2007042087A Rfid tag and production method therefor 审中-公开
标题翻译： RFID标签及其生产方法
公开(公告)号：JP2007042087A
公开(公告)日：2007-02-15
申请号：JP2006180602
申请日：2006-06-30
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： INOUE KOSUKE , HONMA HIROSHI , ODAJIMA HITOSHI , ISADA NAOYA , UEDA KIE
IPC分类号： G06K19/077 , B42D15/10 , G06K19/07
摘要： PROBLEM TO BE SOLVED: To supply a high-reliability RFID tag wherein an antenna and a bump electrode of an RFID chip are connected without using an anisotropic conductive sheet or the like and wherein excellent electric conduction is established between them, at low cost. SOLUTION: In this RFID tag having the antenna formed by electroconductive paste containing an electroconductive filler such as silver flake on a substrate, and the RFID chip connected to the antenna, after hardening a pattern of the antenna shaped by the electroconductive paste, the bump electrode of the RFID chip is brought into contact with the antenna, and they are heated to connect the RFID chip to the antenna by thermoplastic resin contained in the electroconductive paste. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种高可靠性RFID标签，其中RFID芯片的天线和突起电极连接而不使用各向异性导电片等，并且在它们之间建立良好的导电，低成本。解决方案：在具有由基板上含有银薄片等导电性填充剂的导电性胶料形成的天线的RFID标签和连接于天线的RFID芯片之后，在通过导电性糊料形成的天线的图形硬化后， RFID芯片的突起电极与天线接触，并且它们被加热以将RFID芯片与包含在导电浆料中的热塑性树脂连接到天线。版权所有（C）2007，JPO＆INPIT

5. 发明专利

JP2006294824A Multilayer semiconductor device 有权
标题翻译：多层半导体器件
公开(公告)号：JP2006294824A
公开(公告)日：2006-10-26
申请号：JP2005112902
申请日：2005-04-08
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： KATAGIRI MITSUAKI , SHIBAMOTO MASAKUNI , HARA ATSUSHI , AOKI KOICHIRO , ISADA NAOYA , KIKUCHI SHUJI , TANIE HISAFUMI
IPC分类号： H01L25/18 , H01L25/065 , H01L25/07
CPC分类号： H01L25/0657 , H01L24/50 , H01L2225/06527 , H01L2225/06551 , H01L2225/06579 , H01L2924/01005 , H01L2924/01006 , H01L2924/01023 , H01L2924/01033 , H01L2924/01082 , H01L2924/15311 , H01L2924/3011
摘要： PROBLEM TO BE SOLVED: To provide a multilayer semiconductor device which is provided with a base substrate, a semiconductor chip and an interposer substrate suitable for high speed signal transmission, and can secure a sufficient noise resistance performance and wiring efficiency.
SOLUTION: The multilayer semiconductor device is provided with the base substrate 11 in which terminal strings 31 and 32 where a plurality of connection terminals are arranged in a straight line are formed at ends, and which has a wiring pattern where a plurality of connection terminals and an outer terminal 16 are electrically connected; semiconductor chips 13 which are laminated on the base substrate 11 and have a pad string 33 where a plurality of pads are arranged in the straight line; and the interposer substrate 14 where a wiring layer comprising a plurality of wirings which electrically connect the pads of the pad string 33 and the connection terminals of the terminal strings 31 and 32, and are arranged in parallel and in equal length. The pad string 33 and the terminal strings 31 and 32 are mounted almost parallel.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种多层半导体器件，其设置有适用于高速信号传输的基底基板，半导体芯片和内插基片，并且可以确保足够的抗噪声性能和布线效率。解决方案：多层半导体器件设置有基底基板11，其中多个连接端子以直线布置的端子串31和32形成在端部，并且具有布线图案，其中多个连接端子和外部端子16电连接; 半导体芯片13，其层叠在基底基板11上，并且具有在直线上排列有多个焊盘的焊盘串33; 以及插入器基板14，其中布线层包括电连接焊盘串33的焊盘和端子串31和32的连接端子并且平行且相等长度布置的多个布线。焊盘串33和端子串31和32几乎平行地安装。版权所有（C）2007，JPO＆INPIT

6. 发明专利

JP2005039017A Method for manufacturing semiconductor device and wiring board 审中-公开
标题翻译：制造半导体器件和接线板的方法
公开(公告)号：JP2005039017A
公开(公告)日：2005-02-10
申请号：JP2003199382
申请日：2003-07-18
申请人： Hitachi Ltd , Hitachi Maxell Ltd , 日立マクセル株式会社 , 株式会社日立製作所
发明人： TENMYO HIROYUKI , KOYAMA HIROSHI , ISADA NAOYA , NARIZUKA YASUNORI , KISHIMOTO SEIJI , YAMASHITA YUJI
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/768 , H01L23/12 , H01L23/522
CPC分类号： H01L2224/11
摘要： PROBLEM TO BE SOLVED: To suppress generation of gas from an organic insulating film generated in a manufacturing process of a wafer level CSP. SOLUTION: A method for manufacturing a semiconductor device includes a step of constituting two insulating films (photosensitive polyimide resin film 5 and uppermost layer protective film 12) sandwiching Cu wiring 2 of photosensitive resin insulating material. The uppermost layer protective film 12 uses a material (a low temperature cured resin) cured at a lower temperature than the photosensitive polyimide resin film 5 of a lower layer so that a curing time temperature may not exceed a temperature when the photosensitive polyimide resin film 5 of the lower layer is cured. Thus, since the generation of the gas from the photosensitive polyimide resin film 5 of the lower layer is suppressed when the uppermost layer protective film 12 is cured, a failure can be reduced in which the gas is stored in an interface between a Cu wiring 2 and the photosensitive polyimide film 5 to cause bulging to occur. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：抑制在晶片级CSP的制造过程中产生的有机绝缘膜产生气体。解决方案：半导体器件的制造方法包括：构成夹着感光性树脂绝缘材料的Cu布线2的两个绝缘膜（感光性聚酰亚胺树脂膜5和最上层保护膜12）的工序。最上层保护膜12使用在比下层的感光性聚酰亚胺树脂膜5低的温度下固化的材料（低温固化树脂），使得固化时间温度不超过感光性聚酰亚胺树脂膜5 的下层被固化。因此，当最上层保护膜12固化时，由于下层的感光性聚酰亚胺树脂膜5的气体的产生被抑制，所以能够降低在Cu配线2 和感光性聚酰亚胺膜5发生凸起。版权所有（C）2005，JPO＆NCIPI

7. 发明专利

JP2003031724A Semiconductor module 有权
标题翻译：半导体模块
公开(公告)号：JP2003031724A
公开(公告)日：2003-01-31
申请号：JP2001240076
申请日：2001-08-08
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： HOZOJI HIROYUKI , TSUNODA SHIGEHARU , YAMAGUCHI YOSHIHIDE , TENMYO HIROYUKI , ISADA NAOYA
IPC分类号： H01L23/12 , H01L25/04 , H01L25/18
CPC分类号： H01L2224/73204
摘要： PROBLEM TO BE SOLVED: To provide the semiconductor module of high production efficiency improved in the reliability of a connection with an external wafer. SOLUTION: This semiconductor module is provided with a wiring board 2 on which wiring 3 is formed, a semiconductor device 1 electrically connected with wiring formed on the wring board, and an external connecting terminal 5 which is arranged on the side of the wiring board packaging the semiconductor device for a connecting portion with the outside electrically connected with wiring and between the wiring board and the external connecting terminal. An insulating resin layer 10 thicker than the semiconductor device is formed.
摘要翻译：要解决的问题：提供高生产效率的半导体模块，提高与外部晶片的连接的可靠性。解决方案：该半导体模块设置有布线板2，布线3形成在其上，半导体器件1与形成在绞合板上的布线电连接，外部连接端子5布置在布线板封装用于与外部的连接部分的半导体器件与布线电连接，并且在布线板和外部连接端子之间。形成比半导体器件厚的绝缘树脂层10。

8. 发明专利

JP2002093947A SEMICONDUCTOR DEVICE, ITS MANUFACTURING METHOD AND MOUNTING STRUCTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2002093947A
公开(公告)日：2002-03-29
申请号：JP2000284374
申请日：2000-09-19
申请人： HITACHI LTD
发明人： YAMAGUCHI YOSHIHIDE , TENMYO HIROYUKI , INOUE KOSUKE , DAIROKU NORIYUKI , HOZOJI HIROYUKI , TSUNODA SHIGEHARU , ISADA NAOYA , MINAGAWA MADOKA , ANJO ICHIRO , NISHIMURA ASAO , UJIIE KENJI , YAJIMA AKIRA
IPC分类号： H01L23/29 , H01L21/56 , H01L21/60 , H01L23/12 , H01L23/31 , H01L23/485
摘要： PROBLEM TO BE SOLVED: To realize a semiconductor device, enabling the flip-chip connection not needing the underfill. SOLUTION: The semiconductor device comprises a semiconductor element having a plurality of circuit electrodes and a circuit surface covered with a protective film, a stress relaxing layer which is formed on the protective film of the semiconductor element circuit surface with the circuit electrodes exposed and made of a cured thermoplastic resin with slopes at the edges, a wiring layer of a plurality of wirings which are connected respectively to the circuit electrodes and electrically conductively laid from the circuit electrodes to desired spots on the stress relaxing layer via the edges of this layer, a surface protective film thereon and outer connection terminals.

9. 发明专利

JP2002016179A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2002016179A
公开(公告)日：2002-01-18
申请号：JP2000333526
申请日：2000-10-27
申请人： HITACHI LTD
发明人： YAMAGUCHI YOSHIHIDE , TENMYO HIROYUKI , INOUE KOSUKE , DAIROKU NORIYUKI , HOZOJI HIROYUKI , MINAGAWA MADOKA , TSUNODA SHIGEHARU , ISADA NAOYA , ANJO ICHIRO , NISHIMURA ASAO , UJIIE KENJI , YAJIMA AKIRA
IPC分类号： H01L23/12 , H01L21/60
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device for enabling flip chip connection without the need of an underfill. SOLUTION: This semiconductor device is provided with a semiconductor element, an insulation layer formed on the semiconductor element and an external connection terminal formed on the insulation layer and electrically connected to an electrode provided on the semiconductor element. In an area from the edge of the insulation layer to a flat part where the thickness of the insulation layer is almost the same, the kind of the wiring pattern of wiring for a power source or the wiring for grounding and the kind of the wiring pattern for the wiring for signals are different.

10. 发明专利

JPH10242343A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH10242343A
公开(公告)日：1998-09-11
申请号：JP4186397
申请日：1997-02-26
申请人： HITACHI LTD
发明人： YOSHIDA ISAMU , ISADA NAOYA , TSUNODA SHIGEHARU , MIYANO ICHIRO , YAMAKURA HIDEO
IPC分类号： B29C45/40 , B29C45/02 , B29L31/34 , H01L21/56 , H01L23/28
摘要： PROBLEM TO BE SOLVED: To seal even a thin semiconductor device with resin by a low-cost mold and then release it from the die by a method wherein a cushioning material is adhered to the semiconductor device and leads and the semiconductor device are electrically connected and then the semiconductor device is so resin- sealed that the cushioning material may be exposed. SOLUTION: A runner to supply resin thorough is formed between an upper mold 1 and a lower mold 2 and gates 4 are formed at the ends of the runner to form a cavity 5 for forming a semiconductor device. In the cavity 5, a lead frame 6 is located and a semiconductor device 7 is electrically connected to the lead frame 6 by means of bumps 8. Then, a cushioning material 9 is fixed to the semiconductor device 7, being brought into contact with the bottom face of the cavity 5. At the bottom face of the cavity 5 under the suctioning material 9, ejector pins 10 to be used when releasing the device from the mold after resin-sealed are installed. When the device is released from the mold, the cushioning material 9 absorbs a shock from the ejector pins 10 and thereby a defective molding which means the cracking of the semiconductor device 7 can be prevented.

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