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1. 发明专利

JP2014022030A Magnetic memory device 审中-公开
标题翻译：磁记忆装置
公开(公告)号：JP2014022030A
公开(公告)日：2014-02-03
申请号：JP2013142385
申请日：2013-07-08
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： KIM CHAN-KYUNG , CHA SOO-HO , KANG DONG-SEOK , PARK CHEOLWOO , SOHN DONG HYUN , RI JUNSO , KIM HYE JIN
IPC分类号： G11C11/15 , H01L21/8246 , H01L27/105 , H01L29/82 , H01L43/08
CPC分类号： G11C11/165 , G11C5/025 , G11C5/04 , G11C7/1009 , G11C7/1054 , G11C7/1057 , G11C7/1081 , G11C7/222 , G11C11/161 , G11C11/1653 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C11/5607 , G11C13/047 , G11C29/022 , G11C29/028 , G11C29/50008
摘要： PROBLEM TO BE SOLVED: To provide a magnetic memory device, a memory module with the same attached to it, and a memory system.SOLUTION: A magnetic memory device (MRAM) comprises a magnetic memory cell that switches between at least two states in accordance with a magnetization direction, and comprises an interface part that provides various interface functions. A memory module comprises: a module board; at least one or more MRAM chips mounted on the module board; and also a buffer chip mounted on the module board and configured to manage the operation of the MRAM chip. A memory system comprises a memory controller configured to communicate with the MRAM, and transmits or receives an electric-photo conversion signal or photo-electric conversion signal through an optical connection device connected between the MRAM and the memory controller.
摘要翻译：要解决的问题：提供一种磁存储器件，与其相连的存储器模块和存储器系统。解决方案：磁存储器件（MRAM）包括磁存储器单元，其在至少两个状态之间切换具有磁化方向，并且包括提供各种界面功能的接口部分。存储器模块包括：模块板; 安装在模块板上的至少一个或多个MRAM芯片; 以及安装在模块板上并被配置为管理MRAM芯片的操作的缓冲芯片。存储器系统包括被配置为与MRAM通信的存储器控制器，并且通过连接在MRAM和存储器控制器之间的光学连接装置来发送或接收电光转换信号或光电转换信号。

2. 发明专利

JP2012094239A Semiconductor memory device and semiconductor memory system 审中-公开
标题翻译：半导体存储器件和半导体存储器系统
公开(公告)号：JP2012094239A
公开(公告)日：2012-05-17
申请号：JP2011231744
申请日：2011-10-21
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： KIM SU-AH , PARK CHEOLWOO , KO KOZEN , YU HAK-SOO
IPC分类号： G11C11/4097 , G11C11/407 , G11C11/41
CPC分类号： G11C7/18 , G11C7/06 , G11C2207/002 , G11C2207/005
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device in which coupling between bit lines or coupling between word lines can be reduced.SOLUTION: The semiconductor memory device includes: a plurality of memory cell blocks 110_1 to 110_8 including a first region SMCB1 including a first memory cell connected to a first bit line BL12, and a second region SMCB2 including a second memory cell connected to a second bit line BL22; a plurality of bit line sense amplifiers 120_1 to 120_6 connected to the first memory cell or the second memory cell of a corresponding memory cell block; and a plurality of connection parts 130_1 to 130_8 for connecting the first bit line to a corresponding bit line sense amplifier, and connecting the second bit line to the corresponding bit line sense amplifier through global bit lines GBL1 to GBL8.
摘要翻译：要解决的问题：提供一种可以减少位线之间的耦合或字线之间的耦合的半导体存储器件。解决方案：半导体存储器件包括：包括第一区域SMCB1的多个存储单元块110_1至110_8，第一区域SMCB1包括连接到第一位线BL12的第一存储器单元和第二区域SMCB2，第二区域SMCB2包括连接到第二位线BL22; 连接到相应存储单元块的第一存储单元或第二存储单元的多个位线读出放大器120_1至120_6; 以及用于将第一位线连接到对应的位线读出放大器的多个连接部分130_1至130_8，以及通过全局位线GBL1至GBL8将第二位线连接到相应的位线读出放大器。版权所有（C）2012，JPO＆INPIT

3. 发明专利

JP2012094240A Resistive memory device, initializing method thereof, and electronic device having resistive memory device 有权
标题翻译：电阻式存储器件，其初始化方法以及具有电阻存储器件的电子器件
公开(公告)号：JP2012094240A
公开(公告)日：2012-05-17
申请号：JP2011234774
申请日：2011-10-26
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： PARK CHEOLWOO , BAEK IN-GYU , SOHN DONG HYUN , KO KOZEN
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/00 , G11C2013/0083 , G11C2213/71 , G11C2213/79
摘要： PROBLEM TO BE SOLVED: To provide a resistive memory device.SOLUTION: A resistive memory device includes a first pad for supplying a first voltage supplied from an initializing device to a first plate, a second pad for supplying a second voltage supplied from the initializing device to a second plate, a first transistor having a gate, a drain, and a source connected to the first plate, a first memory resistor connected between a bit line BL1 and the drain of the first transistor, a second transistor having a gate, a drain, and a source connected to the second plate, and a second memory resistor connected between the bit line and the drain of the second transistor.
摘要翻译：要解决的问题：提供一种电阻式存储器件。解决方案：电阻式存储器件包括用于将从初始化器件提供的第一电压提供给第一板的第一焊盘，用于将从初始化器件提供的第二电压提供给第二板的第二焊盘，具有连接到第一板的栅极，漏极和源极，连接在位线BL1和第一晶体管的漏极之间的第一存储器电阻，具有栅极，漏极和源极的第二晶体管，连接到第二晶体管的第二晶体管板和连接在第二晶体管的位线和漏极之间的第二存储电阻。版权所有（C）2012，JPO＆INPIT

4. 发明专利

JP2006196161A Semiconductor memory device with arrangement of energy saving word line enable signal line, and method for arranging the same 有权
标题翻译：具有节能字线使能信号线的安排的半导体存储器件及其装置的方法
公开(公告)号：JP2006196161A
公开(公告)日：2006-07-27
申请号：JP2006004186
申请日：2006-01-11
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： JUNG DAE-HEE , PARK CHEOLWOO , RI JUNSO
IPC分类号： G11C11/401 , G11C11/407 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： G11C8/08
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device and a method for arranging the word line enable signal lines.
SOLUTION: This semiconductor memory device has a word line enable driver arranged in a row decoder area outside a memory array area, and the word line enable signal line formed with a top layer among three metal layers. Moreover, the respective word line enable signal lines are coupled to only sub-word line drivers on one side of both memory cell arrays horizontally arranged. Accordingly, the word line enable signal line is arranged "in an L shape". Therefore, since the length of the word line enable signal line is short and the word line enable signal line is formed with low resistance metal of the top layer, the load of the word line enable signal line becomes small.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种用于布置字线使能信号线的半导体存储器件和方法。解决方案：该半导体存储器件具有布置在存储器阵列区域外的行解码器区域中的字线使能驱动器，并且在三个金属层之中形成有顶层的字线使能信号线。此外，相应的字线使能信号线仅在水平布置的两个存储单元阵列的一侧上被耦合到只有子字线驱动器。因此，字线使能信号线被配置为“L字形”。因此，由于字线使能信号线的长度短，字线使能信号线由顶层的低电阻金属形成，所以字线使能信号线的负载变小。版权所有（C）2006，JPO＆NCIPI

5. 发明专利

JP2010263211A Laminated memory element 审中-公开
标题翻译：层压记忆元件
公开(公告)号：JP2010263211A
公开(公告)日：2010-11-18
申请号：JP2010103594
申请日：2010-04-28
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： AHN SEUNG-EON , KIM HO-JUNG , PARK CHEOLWOO , KANG SANG-BOM , CHOI HYUNHO
IPC分类号： H01L27/10 , H01L21/8242 , H01L21/8246 , H01L21/8247 , H01L27/00 , H01L27/105 , H01L27/108 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C5/025 , G11C5/02 , G11C8/10 , G11C13/0004 , G11C13/0023 , G11C13/0028 , G11C2213/71 , G11C2213/72
摘要： PROBLEM TO BE SOLVED: To provide a laminated memory element which is readily subjected to high integration. SOLUTION: The laminated memory element has a substrate, a plurality of memory groups each including at least one memory layer laminated on the substrate mutually, a plurality of X decoder layers which intervene between adjacent two memory groups among the plurality of memory groups, and a plurality of Y decoder layers which intervene alternately with the plurality of X decoder layers between the adjacent two memory groups. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供容易进行高集成度的层叠记忆元件。解决方案：层叠存储元件具有基板，多个存储器组，每个存储器组包括至少一个层叠在基板上的存储层，多个X个解码器层，其在多个存储器组中相邻的两个存储器组之间进行干预以及与相邻的两个存储器组之间的多个X个解码器层交替地插入的多个Y个解码器层。版权所有（C）2011，JPO＆INPIT

6. 发明专利

JP2010232653A Stacked memory device 审中-公开
标题翻译：堆叠存储器件
公开(公告)号：JP2010232653A
公开(公告)日：2010-10-14
申请号：JP2010057450
申请日：2010-03-15
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： AHN SEUNG-EON , KIM HO-JUNG , PARK CHEOLWOO , KANG SANG-BOM , CHOI HYUNHO
IPC分类号： H01L27/10 , H01L21/8242 , H01L21/8246 , H01L25/065 , H01L25/07 , H01L25/18 , H01L27/105 , H01L27/108
CPC分类号： G11C5/025 , G11C5/02 , G11C13/0023 , G11C2213/71 , H01L24/48 , H01L24/49 , H01L25/0657 , H01L25/18 , H01L2224/48091 , H01L2224/49 , H01L2225/06506 , H01L2225/0651 , H01L2924/00014 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： PROBLEM TO BE SOLVED: To provide three-dimensionally stacked, multilayer-structured memory devices easy to upgrade a degree of integration. SOLUTION: The stacked memory device is provided with: a substrate; a plurality of memory layers stacked one over another on the substrate and divided into a plurality of groups; a plurality of inter-decoders, each inter-decoder electrically connected to a memory layer within each group and disposed between the memory layers within the each group; and at least one pre-decoder electrically connected to the plurality of inter-decoders and disposed between the plurality of inter-decoders. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供易于升级一体化的三维堆叠的多层结构的存储器件。解决方案：堆叠式存储器件设置有：衬底; 多个存储层，其在所述基板上层叠并分割成多组; 多个解码器，每个解码器电连接到每个组内的存储器层并且设置在每个组内的存储器层之间; 以及至少一个预解码器，其电连接到所述多个解码器并且设置在所述多个解码器之间。版权所有（C）2011，JPO＆INPIT

7. 发明专利

JP2013242957A Magnetic random access memory 审中-公开
标题翻译：磁性随机存取存储器
公开(公告)号：JP2013242957A
公开(公告)日：2013-12-05
申请号：JP2013099097
申请日：2013-05-09
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： KIM CHAN-KYUNG , KANG DONG-SEOK , KIM HYE JIN , PARK CHEOLWOO , SOHN DONG HYUN , RI JUNSO , KANG SANG-BEOM , HYUNG-ROK OH , CHA SOO-HO
IPC分类号： G11C11/15
CPC分类号： G11C11/165 , G06F12/0246 , G11C11/161 , G11C11/1653 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1693
摘要： PROBLEM TO BE SOLVED: To provide a magnetic random access memory (MRAM).SOLUTION: This invention relates to a magnetic random access memory (MRAM), and a memory module and a memory system including the MRAM. The MRAM includes magnetic memory cells configured to change between at least two states according to a magnetization direction, and a mode register supporting a plurality of operational options of the MRAM. The memory module includes a module board and at least one MRAM chip mounted on the module board, and further includes a buffer chip mounted on the module board and managing an operation of the MRAM chip. The memory system includes a memory controller communicating with the MRAM, in which an electric to optical conversion signal or an optical to electric conversion signal is communicated through an optical link device which is linked between the MRAM and the memory controller.
摘要翻译：要解决的问题：提供一种磁性随机存取存储器（MRAM）。本发明涉及一种磁性随机存取存储器（MRAM），以及一种存储器模块和包括MRAM的存储器系统。 MRAM包括配置为根据磁化方向在至少两个状态之间变化的磁存储器单元和支持MRAM的多个操作选项的模式寄存器。存储器模块包括模块板和安装在模块板上的至少一个MRAM芯片，并且还包括安装在模块板上的缓冲芯片，并管理MRAM芯片的操作。存储器系统包括与MRAM通信的存储器控制器，其中通过连接在MRAM和存储器控制器之间的光学链路装置传送电光转换信号或光电转换信号。

8. 发明专利

JP2012089137A Semiconductor device, memory module including semiconductor device, memory system, and operation method for memory system 审中-公开
标题翻译：半导体器件，包含半导体器件的存储器模块，存储器系统和用于存储器系统的操作方法
公开(公告)号：JP2012089137A
公开(公告)日：2012-05-10
申请号：JP2011230618
申请日：2011-10-20
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： PARK CHEOLWOO , JUN YOUNG-HYUN , CHOI JOO-SUN , KO KOZEN
IPC分类号： G06F12/00
CPC分类号： G11C29/808 , G06F2213/0038 , G11C11/40618 , G11C11/40622 , G11C11/40626 , G11C2211/4062
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device, a memory module including the semiconductor device, a memory system, and an operation method for the memory system.SOLUTION: There are provided a semiconductor device that uses an operation policy suitable for a large-capacity memory, a memory module including the semiconductor device, a memory system, and an operation method for the memory system. The memory module includes: plural dynamic memory devices each having a memory cell array with plural areas, and driving the plural areas in response to a command; and a DRAM management unit placed on the module, coupled to the plural dynamic memory devices, and including a memory device operation parameter saving circuit for saving a memory device operation parameter relating to each area so as to affect operation of each of the plural areas in response to the command.
摘要翻译：要解决的问题：提供一种半导体器件，包括半导体器件的存储器模块，存储器系统和用于存储器系统的操作方法。解决方案：提供了一种半导体器件，其使用适合于大容量存储器的操作策略，包括半导体器件的存储器模块，存储器系统和用于存储器系统的操作方法。存储模块包括：多个动态存储装置，每个具有多个区域的存储单元阵列，并且响应命令驱动多个区域; 以及DRAM管理单元，放置在模块上，耦合到多个动态存储器件，并且包括存储器件操作参数保存电路，用于保存与每个区域相关的存储器件操作参数，以便影响每个区域中的每个区域的操作回应命令。版权所有（C）2012，JPO＆INPIT

9. 发明专利

JP2006114221A Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：JP2006114221A
公开(公告)日：2006-04-27
申请号：JP2006011280
申请日：2006-01-19
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： PARK CHEOLWOO , CHO KENJUN , KIM CHULL-SOO , KIN MEIKO , LEE SEUNG-HUN , LEE SI-YEOL , RI KOTETSU , KIM TAE-JIN , CHOI YUN-HO
IPC分类号： G11C11/401 , G11C7/00 , G11C7/10 , G11C11/403 , G11C11/406 , G11C11/407 , G11C11/4076 , G11C11/408 , G11C11/409
CPC分类号： G11C7/1018 , G11C7/1045 , G11C7/1072 , G11C7/222 , G11C7/225 , G11C11/406 , G11C11/40618 , G11C11/4076 , G11C11/408 , G11C11/4082 , G11C11/4087 , G11C2207/2281
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory capable of accessing data in a memory cell array at a high speed in synchronization with an external system clock. SOLUTION: The semiconductor memory which receives an external clock is provided with a plurality of memory banks operable in an active cycle or a precharge cycle indicating a reading cycle or a writing cycle, a means for latching the logical level of a received row address strobe signal in response to the rising or falling edge of the external clock, an input means for an external address to select one of the memory banks, and a means for receiving the latched logical level and an address from the address input means, outputting an activation signal to the selected memory bank when the logical level is a first logical level, and outputting an inactivation signal to the unselected memory bank in the active cycle to operate in the precharge cycle. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种与外部系统时钟同步地能够以高速访问存储单元阵列中的数据的半导体存储器。解决方案：接收外部时钟的半导体存储器设置有多个存储器组，其可以在指示读取周期或写入周期的活动周期或预充电周期中操作，用于锁存接收到的行的逻辑电平的装置响应于外部时钟的上升沿或下降沿的地址选通信号，用于选择存储体之一的外部地址的输入装置，以及用于从地址输入装置接收锁存的逻辑电平和地址的装置，输出当所述逻辑电平为第一逻辑电平时，将所述激活信号发送到所述选择的存储体，并且在所述激活周期中将所述未选择的存储体输出到所述预选电池周期中。版权所有（C）2006，JPO＆NCIPI

10. 发明专利

JP2005100652A Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：JP2005100652A
公开(公告)日：2005-04-14
申请号：JP2005001938
申请日：2005-01-06
申请人： Samsung Electronics Co Ltd , 三星電子株式会社
发明人： PARK CHEOLWOO , CHO KENJUN , KIM CHULL-SOO , KIN MEIKO , LEE SEUNG-HUN , LEE SI-YEOL , RI KOTETSU , KIM TAE-JIN , CHOI YUN-HO
IPC分类号： G11C11/401 , G11C7/00 , G11C7/10 , G11C11/403 , G11C11/406 , G11C11/407 , G11C11/4076 , G11C11/408 , G11C11/409
CPC分类号： G11C7/1018 , G11C7/1045 , G11C7/1072 , G11C7/222 , G11C7/225 , G11C11/406 , G11C11/40618 , G11C11/4076 , G11C11/408 , G11C11/4082 , G11C11/4087 , G11C2207/2281
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory capable of accessing data in a memory cell array at a high speed in synchronism with an external system clock. SOLUTION: The semiconductor memory to which an external clock is inputted is provided with: a plurality of memory banks operated at an active cycle indicating a read or write cycle, or a precharge cycle; a means for latching the logical level of an inputted row address strobe signal in response to the rising or falling edge of the external clock; an external address input means for selecting one of the memory banks; and a means for receiving the latched logical level and an address from the address input means, and outputting, when the logical level is at a first logical level, an activating signal to the selected memory bank to operate it at the active cycle, and outputting a nonactivating signal to the unselected memory bank to operate it at the precharge cycle. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种与外部系统时钟同步地能够以高速访问存储单元阵列中的数据的半导体存储器。
解决方案：输入外部时钟的半导体存储器具有：以指示读或写周期或预充电循环的活动周期操作的多个存储体; 用于响应于外部时钟的上升沿或下降沿来锁存输入的行地址选通信号的逻辑电平的装置; 外部地址输入装置，用于选择存储体之一; 以及用于从地址输入装置接收锁存的逻辑电平和地址的装置，并且当逻辑电平处于第一逻辑电平时，将所述激活信号输出到所选择的存储体以在所述有效周期操作，并输出对未选择的存储体的非激活信号在预充电循环中进行操作。版权所有（C）2005，JPO＆NCIPI

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