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    • 3. 发明专利
    • Semiconductor device, and its manufacturing method
    • 半导体器件及其制造方法
    • JP2008021765A
    • 2008-01-31
    • JP2006191331
    • 2006-07-12
    • Renesas Technology Corp株式会社ルネサステクノロジ
    • SHIGENIWA MASAHIROMATSUZAKI NOZOMITAKEMURA RIICHIRO
    • H01L27/105H01L45/00
    • H01L45/144G11C11/5678G11C13/0004G11C2213/79H01L27/2436H01L27/2472H01L45/06H01L45/1233H01L45/1675
    • PROBLEM TO BE SOLVED: To achieve a semiconductor device easy to form a phase change film while achieving an increase in an integration at a time when utilizing the phase change film as a storage element, and to provide a manufacturing method for the semiconductor device.
      SOLUTION: Each source for MISFETs is adjoined while being insulated on the surface of a semiconductor substrate 1 between the two MISFETs of the MISFET in a region AR1 configuring one memory cell and the MISFET adjacent to the MISFET. The laminating structure of the phase change film 10 and a conductive film 11 having a resistivity lower than that of the phase change film 10 is formed astride over each source for both MISFETs, a plug 8, and the plug 7 in the plan view of the surface of the semiconductor substrate 1. The laminating structure functions as a wiring extending in parallel with the surface of the semiconductor substrate 1, and the conductive film 11 feeds a current in the direction parallel with the surface of the semiconductor substrate 1.
      COPYRIGHT: (C)2008,JPO&INPIT
    • 解决的问题:为了实现容易形成相变膜的半导体器件,同时在利用相变膜作为存储元件的时候实现集成度的增加,并且提供半导体的制造方法 设备。 解决方案:在构成一个存储单元的区域AR1和与MISFET相邻的MISFET之间的MISFET的两个MISFET之间的半导体衬底1的表面上绝缘的每个MISFET的源极相邻。 在相位变化膜10的平面图中,相互切换膜10和电阻率低于相变膜10的导电膜11的层压结构横跨每个MISFET,插头8和插头7的源极跨越 表面。该层压结构用作与半导体衬底1的表面平行延伸的布线,并且导电膜11沿与半导体衬底1的表面平行的方向馈送电流。 版权所有(C)2008,JPO&INPIT
    • 4. 发明专利
    • Nonvolatile semiconductor memory device
    • 非易失性半导体存储器件
    • JP2006196643A
    • 2006-07-27
    • JP2005006081
    • 2005-01-13
    • Renesas Technology Corp株式会社ルネサステクノロジ
    • MINE TOSHIYUKIKUME HITOSHIMATSUZAKI NOZOMIYASUI KAN
    • H01L21/8247H01L27/115H01L29/788H01L29/792
    • PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device improved in the deterioration of Gm accompanying erasing operation.
      SOLUTION: The nonvolatile semiconductor memory device comprises a selective MOS transistor where a nonvolatile memory includes a gate insulating film 102 and a selective gate electrode 103; a capacitance insulating film including a lower layer potential barrier film 104, a first charge holding film 105, and a second charge holding film 106; and a memory MOS transistor including a memory gate electrode 107. An Si nitride film containing stoichiometrically excessive Si is used for the first charge holding film 105, and an Si oxide nitride film is used for the second charge holding film.
      COPYRIGHT: (C)2006,JPO&NCIPI
    • 要解决的问题:提供一种随着擦除操作而改善Gm劣化的非易失性半导体存储器件。 解决方案:非易失性半导体存储器件包括选择性MOS晶体管,其中非易失性存储器包括栅极绝缘膜102和选择栅电极103; 包括下层势垒膜104,第一电荷保持膜105和第二电荷保持膜106的电容绝缘膜; 以及包括存储器栅电极107的存储器MOS晶体管。对于第一电荷保持膜105使用包含化学计量过量的Si的氮化硅膜,并且使用Si氧化物氮化物膜作为第二电荷保持膜。 版权所有(C)2006,JPO&NCIPI
    • 6. 发明专利
    • Semiconductor device
    • JP2004247633A
    • 2004-09-02
    • JP2003037755
    • 2003-02-17
    • Renesas Technology Corp株式会社ルネサステクノロジ
    • MATSUZAKI NOZOMIHISAMOTO MASARUKIMURA SHINICHIRO
    • H01L27/10H01L21/8247H01L27/115H01L29/788H01L29/792
    • PROBLEM TO BE SOLVED: To reduce structural steps generated in manufacturing for consolidating a nonvolatile memory cell in a semiconductor device using a fine MOS type transistor and to prevent short circuit defect inside a nonvolatile memory cell in silicide formation which is essential for a logical semiconductor device.
      SOLUTION: A gate insulating film formation process of a plurality of standard film thicknesses which requires multistage cleaning is carried out before shallow groove isolation structure formation for preventing generation of structural level difference. Either a storing MOS tyep transistor or a memory cell selecting MOS type transistor constituting a nonvolatile memory cell is formed to a sidewall spacer shape for preventing generation of structural steps. In order to prevent generation of short circuit defect due to silicide, if a gate electrode of the storing MOS type transistor is sidewall spacer-like in the storing MOS type transistor and the memory cell selecting MOS type transistor constituting the nonvolatile memory cell, the electrode is not turned to silicide. When a gate electrode of the memory cell selecting MOS type transistor is sidewall spacer-like, only the memory cell selecting MOS type transistor is turned to silicide.
      COPYRIGHT: (C)2004,JPO&NCIPI
    • 7. 发明专利
    • Non-volatile semiconductor storage device
    • 非挥发性半导体存储器件
    • JP2010062594A
    • 2010-03-18
    • JP2009287046
    • 2009-12-18
    • Renesas Technology Corp株式会社ルネサステクノロジ
    • HISAMOTO MASARUKIMURA SHINICHIROYASUI KANMATSUZAKI NOZOMI
    • H01L21/8247H01L27/10H01L27/115H01L29/788H01L29/792
    • PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor storage device having sophisticated write-erase characteristics.
      SOLUTION: A selection gate 18 is formed on a gate insulating film 6 on a p-well 2 of a semiconductor substrate, and a memory gate 17 is formed on a stacked film 15 consisting of a silicon oxide film 15a, a silicon nitride film 15b and a silicon oxide film 15c on the p-well 2. The memory gate 17 adjoins the selection gate 18 through the stacked film 15. In both side areas of the p-well 2 on the selection gate 18 side and the memory gate 17 side, n-type impurity diffusion layers 20 and 21 are formed as source and drain, respectively. In the channel area between the impurity diffusion layers 20 and 21, charge densities of an area 51 which can be controlled by the selection gate 18 and an area 52 which can be controlled by the memory gate 17 are different from each other.
      COPYRIGHT: (C)2010,JPO&INPIT
    • 要解决的问题:提供具有复杂的写擦除特性的非易失性半导体存储装置。 解决方案:选择栅极18形成在半导体衬底的p阱2上的栅极绝缘膜6上,并且存储栅极17形成在由氧化硅膜15a,硅 氮化物膜15b和p阱2上的氧化硅膜15c。存储器栅极17通过堆叠膜15邻接选择栅极18.在选择栅极18侧的p阱2的两个侧面区域和存储器 栅极17侧,n型杂质扩散层20和21分别形成为源极和漏极。 在杂质扩散层20和21之间的沟道区域中,可以由选择栅极18控制的区域51的电荷密度和可由存储器栅极17控制的区域52彼此不同。 版权所有(C)2010,JPO&INPIT
    • 8. 发明专利
    • Semiconductor integrated circuit device
    • 半导体集成电路设备
    • JP2008085348A
    • 2008-04-10
    • JP2007257415
    • 2007-10-01
    • Renesas Technology Corp株式会社ルネサステクノロジ
    • MATSUZAKI NOZOMIMIZUNO HIROYUKIHORIGUCHI SHINJI
    • H01L21/8234H01L21/8238H01L21/8242H01L21/8244H01L21/8246H01L27/088H01L27/092H01L27/108H01L27/11H01L27/112H03K19/00H03K19/0948
    • PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device capable of reducing power consumption during standby periods without sacrificing circuit operation speed. SOLUTION: The semiconductor integrated circuit device includes plural kinds of MOS transistors different in magnitude of tunnel current flowing at least between the source and gate or between the drain and gate thereof on a same silicon substrate. The semiconductor integrated circuit device comprises a main circuit which is composed of at least one MOS transistor having large tunnel current out of the plural kinds of MOS transistors, and a control circuit which is composed of at least one MOS transistor having small tunnel current. The control circuit is interposed between the main circuit and at least one of two power supplies, and controls permission/prohibition of the current flowing between the source and gate or between the drain and gate of the MOS transistor that constitutes the main circuit with a control signal supplied to the control circuit. A switch is provided at IN or OUT of the main circuit to prevent flowing of leakage current between IN and OUT of the main circuit when the logic levels of IN and OUT are different during standby periods. COPYRIGHT: (C)2008,JPO&INPIT
    • 要解决的问题:提供一种半导体集成电路器件,能够在不牺牲电路运行速度的情况下在待机期间降低功耗。 解决方案:半导体集成电路器件包括在同一硅衬底上至少在源极和栅极之间或其漏极和栅极之间流动的隧道电流的大小不同的多种MOS晶体管。 半导体集成电路器件包括由多个MOS晶体管中的至少一个具有大的隧道电流的MOS晶体管构成的主电路和由具有小的隧道电流的至少一个MOS晶体管组成的控制电路。 控制电路插在主电路和两个电源中的至少一个之间,并且控制允许/禁止在构成主电路的源极和栅极之间或在构成主电路的漏极和栅极之间的电流的控制 信号提供给控制电路。 在主电路的IN或OUT处提供开关,以防止在待机期间IN和OUT的逻辑电平不同时主电路的IN和OUT之间的漏电流的流动。 版权所有(C)2008,JPO&INPIT