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1. 发明专利

JP2010055751A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2010055751A
公开(公告)日：2010-03-11
申请号：JP2009281364
申请日：2009-12-11
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： SEKIGUCHI TOMONORI , TAKEMURA RIICHIRO , SAKATA TAKESHI , AYUKAWA KAZUSHIGE , KAWAHARA TAKAYUKI
IPC分类号： G11C11/401 , G11C11/4097
摘要： PROBLEM TO BE SOLVED: To solve the problem that when data to be written into a memory array are coded after the data are serially input in order to reduce a decrease of an operating margin in a DRAM using one intersection cell, long time is required for coding and memory access time is increased.
SOLUTION: A semiconductor device includes: a first memory array having a first word line, a plurality of first bit lines intersecting the first word line, and a plurality of first memory cells disposed at the intersections between the first word line and the plurality of first bit lines; a coding circuit connected to the plurality of first bit lines; and a plurality of data registers connected to the coding circuit. When a first command is input, the coding circuit decodes the coded data held in the plurality of first memory cells, and outputs the decoded data to the plurality of data registers, and outputs the decoded data stored in the plurality of data registers, according to a second command input after the first command.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题为了解决在数据被串行输入之后要写入存储器阵列的数据被编码以便减少使用一个交点单元的DRAM中的操作余量的减少的问题，长时间是编码需要的，并且存储器访问时间增加。解决方案：半导体器件包括：第一存储器阵列，其具有第一字线，与第一字线相交的多个第一位线，以及多个第一存储单元，设置在第一字线和第一字线之间的交点处多个第一位线; 连接到所述多个第一位线的编码电路; 以及连接到编码电路的多个数据寄存器。当输入第一命令时，编码电路对保存在多个第一存储单元中的编码数据进行解码，并将解码数据输出到多个数据寄存器，并根据存储在多个数据寄存器中的解码数据输出在第一个命令之后输入第二个命令。版权所有（C）2010，JPO＆INPIT

2. 发明专利

JP2010055748A Data storage device 审中-公开
标题翻译：数据存储设备
公开(公告)号：JP2010055748A
公开(公告)日：2010-03-11
申请号：JP2009279114
申请日：2009-12-09
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： KAWAHARA TAKAYUKI , SATO HIROSHI , NOZOE ATSUSHI , YOSHIDA KEIICHI , NODA TOSHIFUMI , KUBONO SHOJI , KOTANI HIROAKI , KIMURA KATSUTAKA
IPC分类号： G11C16/02
摘要： PROBLEM TO BE SOLVED: To accelerate a write operation for a nonvolatile memory cell. SOLUTION: A semiconductor integrated circuit includes a plurality of nonvolatile memory cells being electrically erasable and writable, and the circuit includes a control means for giving pulse state voltage to the nonvolatile memory cell until threshold voltage of the nonvolatile memory cell having first threshold voltage is changed to the second threshold voltage. At the time, the control means controls the second threshold voltage to be voltage in a range being lower than power source voltage and half of power source voltage or more. Thus, the semiconductor integrated circuit can have only coarse write as a write mode. The coarse write mode is required for fewer pulses to change the threshhold voltage of the memory cell, thereby accelerating the write operation. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：加速非易失性存储单元的写入操作。解决方案：半导体集成电路包括电可擦除和可写入的多个非易失性存储单元，并且该电路包括用于向非易失性存储单元提供脉冲状态电压的控制装置，直到具有第一阈值的非易失性存储单元的阈值电压电压变为第二阈值电压。此时，控制装置将第二阈值电压控制在低于电源电压和电源电压的一半以上的范围内的电压。因此，半导体集成电路可以仅具有粗写作为写模式。需要较少的脉冲来改变存储单元的阈值电压的粗略写入模式，从而加速写入操作。版权所有（C）2010，JPO＆INPIT

3. 发明专利

JP2010033711A Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：JP2010033711A
公开(公告)日：2010-02-12
申请号：JP2009260615
申请日：2009-11-16
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： KAWAHARA TAKAYUKI , SATO HIROSHI , NOZOE ATSUSHI , YOSHIDA KEIICHI , NODA TOSHIFUMI , KUBONO SHOJI , KOTANI HIROAKI , KIMURA KATSUTAKA
IPC分类号： G11C16/02
摘要： PROBLEM TO BE SOLVED: To achieve a high speed for a writing operation to a nonvolatile memory cell. SOLUTION: The semiconductor integrated circuit includes a plurality of electrically erasable and writable nonvolatile memory cells, and a control means for applying a pulse voltage to the nonvolatile memory cells until the threshold voltage of the nonvolatile memory cell having a first threshold voltage is changed to a second threshold voltage. In this case, the control means controls the second threshold voltage to a voltage of a range lower than a power supply voltage and equal to or more than half of the power supply voltage. Thus, the semiconductor integrated circuit has only rough writing as a write mode. The number of pulses necessary for changing the threshold voltage of the memory cell is smaller in the rough write mode, and thus a high speed is achieved for a writing operation. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了实现对非易失性存储单元的写入操作的高速度。解决方案：半导体集成电路包括多个电可擦除和可写非易失性存储单元，以及用于向非易失性存储单元施加脉冲电压直至具有第一阈值电压的非易失存储单元的阈值电压为止改为第二阈值电压。在这种情况下，控制装置将第二阈值电压控制在比电源电压低的范围内的电压，等于或大于电源电压的一半。因此，半导体集成电路只有粗写作为写模式。在粗写入模式中，改变存储单元的阈值电压所需的脉冲数较少，因此在写入操作时实现高速。版权所有（C）2010，JPO＆INPIT

4. 发明专利

JP2007200545A Nonvolatile semiconductor memory device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2007200545A
公开(公告)日：2007-08-09
申请号：JP2007096613
申请日：2007-04-02
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： KURATA HIDEAKI , KOBAYASHI NAOKI , SAEKI SHUNICHI , KOBAYASHI TAKASHI , KAWAHARA TAKAYUKI , TAKASE KENJUN , YOSHIDA KEIICHI , KANEMITSU MICHITARO , KUBONO SHOJI , NOZOE ATSUSHI
IPC分类号： G11C16/02 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To achieve high speed writing by reducing a variation in the write performance of a nonvolatile semiconductor memory device. SOLUTION: At the write operation of the nonvolatile semiconductor memory device, an electric charge is accumulated in a certain capacity provided at each write-in cell and the write is carried out by injecting hot electrons generated when the charge is discharged via a memory cell into a floating gate. Thus, the variation in the write performance of the nonvolatile semiconductor memory device is reduced, thereby the high speed writing is achieved. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：通过减少非易失性半导体存储器件的写入性能的变化来实现高速写入。解决方案：在非易失性半导体存储器件的写入操作中，以每个写入单元提供的特定容量累积电荷，并且通过注入通过经由存储单元进入浮动门。因此，降低了非易失性半导体存储器件的写入性能的变化，从而实现了高速写入。版权所有（C）2007，JPO＆INPIT

5. 发明专利

JP2006318513A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2006318513A
公开(公告)日：2006-11-24
申请号：JP2006239176
申请日：2006-09-04
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： KAWAHARA TAKAYUKI , SHIMIZU TATEHISA , ARAKAWA FUMIO , MIZUNO HIROYUKI , WATABE TAKAO , ISHIBASHI KOICHIRO
IPC分类号： G06F1/32
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device with prediction type power control capable of constituting a low-powered system LSI with high scalability at possible design man-hours. SOLUTION: A prediction type power-supply cutoff circuit composed of a prediction circuit P and a power condition control circuit D is added to a functional logic circuit block K. The prediction circuit P controls the power condition of the circuit block K by the circuit D on the basis of information of input I to the circuit block K. For example, the circuit D shifts the power condition of the circuit block K to the low-powered condition when there is no input for more than a predetermined period. The system LSI formed by connecting a plurality of circuit blocks K added with the prediction circuit P and the power condition control circuit D can be shifted to the low-powered condition by self- distribution manner according to the condition of the input I independently of a calculating device wherein each circuit block K controls the whole system. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够在可能的设计时间下构建具有高可扩展性的低功率系统LSI的预测型功率控制的半导体器件。解决方案：将由预测电路P和功率条件控制电路D构成的预测型电源切断电路加到功能逻辑电路块K.预测电路P通过以下方式控制电路块K的功率状态电路D基于对电路块K的输入I的信息。例如，当没有输入超过预定周期时，电路D将电路块K的功率条件移动到低功率状态。通过将与预测电路P相加的多个电路块K与电力状态控制电路D相连接而形成的系统LSI，可以根据输入I的条件，以独立于计算装置，其中每个电路块K控制整个系统。版权所有（C）2007，JPO＆INPIT

6. 发明专利

JP2005323402A Electronic device 有权
标题翻译：电子设备
公开(公告)号：JP2005323402A
公开(公告)日：2005-11-17
申请号：JP2005208795
申请日：2005-07-19
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： HORIGUCHI SHINJI , UCHIYAMA KUNIO , ITO KIYOO , SAKATA TAKESHI , AOKI MASAKAZU , KAWAHARA TAKAYUKI
IPC分类号： H03K19/00
摘要： PROBLEM TO BE SOLVED: To reduce current consumption in an electronic apparatus that performs low-voltage operation, such as battery-driven operation. SOLUTION: A battery-driven electronic apparatus includes a processing unit (601), a memory (606) for storing a program to be executed by the processing unit and data to be processed, a control unit (605), a first bus (651) connecting the processing unit and the control unit, and a second bus (652) connecting the memory and the control unit. The program or the data are read in response to an access request supplied from the control unit to the memory via the second bus, and sent to the processing unit via the first bus, and there are two kinds of threshold voltages for a plurality of MOS transistors comprising the processing unit, although they are the same conductive type. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了降低电池驱动操作等低电压运行的电子设备的电流消耗。电池驱动的电子设备包括处理单元（601），用于存储由处理单元执行的程序和要处理的数据的存储器（606），控制单元（605），第一连接处理单元和控制单元的总线（651）以及连接存储器和控制单元的第二总线（652）。响应于从控制单元通过第二总线向存储器提供的访问请求读取程序或数据，并通过第一总线发送到处理单元，并且存在两种用于多个MOS的阈值电压包括处理单元的晶体管虽然是相同的导电类型。版权所有（C）2006，JPO＆NCIPI

7. 发明专利

JP2005303111A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2005303111A
公开(公告)日：2005-10-27
申请号：JP2004118709
申请日：2004-04-14
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： KAWAHARA TAKAYUKI , OSADA KENICHI , MIKI HIROSHI
IPC分类号： G11C11/412 , G11C11/41 , H01L21/8238 , H01L21/8244 , H01L27/092 , H01L27/11
摘要： PROBLEM TO BE SOLVED: To solve problems of a conventional 4-transistor SRAM that causes a high leakage current and has difficulty of applying the SRAM to mixed use of various transistors although the SRAM is small in size.
SOLUTION: A high dielectric film is employed for gate insulation films of parts of transistors among MOS transistors configuring the 4-transistor SRAM, and the V-I characteristic of the parts of the transistors is configured to have a history. Thus, the reduction in the leakage current can be resulted from the information storage capability of the high dielectric film itself.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：为了解决导致高漏电流的传统4晶体管SRAM的问题，并且难以将SRAM应用于各种晶体管的混合使用，尽管SRAM的尺寸小。解决方案：构成4晶体管SRAM的MOS晶体管中的晶体管部分的栅极绝缘膜采用高介电膜，并且晶体管部分的V-I特性被配置为具有历史。因此，漏电流的降低可以由高介电膜本身的信息存储能力引起。版权所有（C）2006，JPO＆NCIPI

8. 发明专利

JP2005267837A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2005267837A
公开(公告)日：2005-09-29
申请号：JP2005001979
申请日：2005-01-07
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： OSADA KENICHI , TAKEMURA RIICHIRO , TAKAURA NORIKATSU , MATSUZAKI NOZOMI , KAWAHARA TAKAYUKI
IPC分类号： G11C13/00 , G06F13/00 , G11C11/00 , G11C16/02 , G11C16/10 , G11C16/26 , G11C16/34 , G11C19/08 , H01L27/10 , H01L27/105
CPC分类号： G11C13/0004 , G11C13/0033 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C16/3454 , G11C2013/0092 , G11C2213/82
摘要： PROBLEM TO BE SOLVED: To realize a stable operation at a low voltage in a semiconductor device, a semiconductor memory device, especially a nonvolatile memory, and a system LSI (microcomputer) on which the novolatile memory is mounted. SOLUTION: This semiconductor device includes: a plurality of memory cells; a central processing unit; a timer circuit for measuring RESET time; and a timer circuit for measuring SET time. A RESET operation is easily carried out by setting the threshold value of an NMOS transistor used for the memory cells lower than that of a peripheral circuit. Further, the direction of a current flowing through the RESET and the SET is changed, and a bit line is driven at a high speed to prevent an erroneous operation. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：在半导体器件，半导体存储器件，特别是非易失性存储器以及安装有非易失性存储器的系统LSI（微计算机）中实现低电压的稳定操作。解决方案：该半导体器件包括：多个存储单元; 中央处理单元; 定时器电路，用于测量复位时间; 以及用于测量SET时间的定时器电路。通过将用于存储单元的NMOS晶体管的阈值设置为低于外围电路的阈值，可以容易地进行复位操作。此外，流经RESET和SET的电流的方向改变，并且高速驱动位线以防止错误操作。版权所有（C）2005，JPO＆NCIPI

9. 发明专利

JP2007173385A Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路设备
公开(公告)号：JP2007173385A
公开(公告)日：2007-07-05
申请号：JP2005366784
申请日：2005-12-20
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： YAMAOKA MASANAO , KAWAHARA TAKAYUKI
IPC分类号： H01L21/8234 , G11C11/41 , H01L21/8244 , H01L27/088 , H01L27/10 , H01L27/11 , H01L29/786
CPC分类号： H03K19/0016 , G11C11/413
摘要： PROBLEM TO BE SOLVED: To provide a technology for reducing a leak current of the circuit for driving a circuit that requires to be fixed at a potential in standby. SOLUTION: A double-gate transistor is used of which thickness of gate oxide film is different. A gate of the transistor having a thin oxide film is turned off while the gate of thick oxide film is turned on, to drive a node of which potential does not change. So a leak current is reduced in a circuit itself for reducing the leak current of a circuit block as well as a leak current of the circuit block. COPYRIGHT: (C)2007,JPO&INPIT

10. 发明专利

JP2007103629A Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：JP2007103629A
公开(公告)日：2007-04-19
申请号：JP2005290889
申请日：2005-10-04
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： YAMAOKA MASANAO , KAWAHARA TAKAYUKI
IPC分类号： H01L21/8244 , G11C11/412 , H01L27/10 , H01L27/11 , H01L29/786
CPC分类号： G11C11/412
摘要： PROBLEM TO BE SOLVED: To reduce power consumption in a whole LSI circuit by reducing a leak current and a sub-threshold leak current flowing from a drain electrode to a substrate electrode in a low power consumption SRAM using miniaturized transistors, to raise the stability of an operation in writing and reading a memory cell, to suppress the increase of the memory cells due to the increase of the number of the transistors, etc., and to suppress the increase of a chip area. SOLUTION: A semiconductor memory device attains the stable operation of the memory cells by controlling well potential under the BOX layers of the driving transistors so as to control the threshold value voltage of the transistors, and to increase an electric current concerning the SRAM memory cells which are composed of the SOI or FD-SOI transistors having a BOX layer. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题为了通过在使用小型化的晶体管的低功耗SRAM中减少从漏极到衬底电极的漏电流和亚阈值漏电流来降低整个LSI电路中的功耗，提高写入和读取存储单元的操作的稳定性，以抑制由于晶体管数量的增加而引起的存储单元的增加，并且抑制了芯片面积的增加。解决方案：半导体存储器件通过控制驱动晶体管的BOX层下的阱电位来实现存储单元的稳定操作，从而控制晶体管的阈值电压，并增加与SRAM相关的电流由具有BOX层的SOI或FD-SOI晶体管组成的存储单元。版权所有（C）2007，JPO＆INPIT

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