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1. 发明专利

JP2008153678A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2008153678A
公开(公告)日：2008-07-03
申请号：JP2008000095
申请日：2008-01-04
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： HISAMOTO MASARU , YASUI KAN , ISHIMARU TETSUYA , KIMURA SHINICHIRO , OKADA DAISUKE
IPC分类号： H01L21/8247 , G11C16/02 , G11C16/04 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide an operating method for operating stably a semiconductor nonvolatile memory device. SOLUTION: When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without considering any variations with time. Also, writing or writing/erasure is conducted by applying pulse voltage or multi-step voltage to a gate section a plurality of times. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于稳定地操作半导体非易失性存储器件的操作方法。解决方案：当在分裂栅极结构的半导体非易失性存储器件中进行热空穴注入时，使用不随时间变化的交叉点来验证热孔注入。因此，可以在不考虑随时间的任何变化的情况下验证擦除状态。此外，通过将多个脉冲电压或多级电压施加到栅极部分来进行写入或写入/擦除。版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2007281506A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2007281506A
公开(公告)日：2007-10-25
申请号：JP2007154689
申请日：2007-06-12
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： OKAZAKI TSUTOMU , OKADA DAISUKE , NITTA KYOYA , TANAKA TOSHIHIRO , KATO AKIRA , MATSUI SHUNICHI , ISHII YASUYUKI , HISAMOTO MASARU , YASUI KAN
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To improve performance of a semiconductor device and to improve manufacturing yield. SOLUTION: Memory cells 30 are arranged in the shape of plural arrays, and selector gate electrodes 8 of the memory cells 30 which are lined up in the X direction are connected by selector gate lines 9. Memory gate electrodes 13 are connected by memory gate lines 14. Memory gate lines 14 connected to the memory gate electrodes 13 of the adjacent memory cells 30 through a source region are not electrically connected, respectively. The selector gate line 9 has a first part 9a extending in the X direction, and a second part 9b extending in the Y direction whose one end is connected with the first part 9a. The memory gate line 14 is formed on a side wall of the selector gate line 9 through an insulating film, is provided with a contact 14a extending in the X direction from the second part 9b of the selector gate line 9 to an element isolation region, and is connected to a wiring through a plug burying a contact hole 23d formed on the contact part 14a. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提高半导体器件的性能并提高制造成品率。存储单元30以多个阵列的形状排列，并且通过选择栅极线9连接在X方向排列的存储单元30的选择栅电极8.存储栅电极13通过存储栅极线14.通过源极区域连接到相邻存储单元30的存储栅电极13的存储栅极线14分别不电连接。选择栅极线9具有沿X方向延伸的第一部分9a和沿着Y方向延伸的第二部分9b，其一端与第一部分9a连接。存储栅极线14通过绝缘膜形成在选择栅极线9的侧壁上，设置有从X选择栅极线9的第二部分9b延伸到元件隔离区的触点14a，并且通过埋入形成在接触部14a上的接触孔23d的插头连接到布线。版权所有（C）2008，JPO＆INPIT

3. 发明专利

JP2006302985A Method of manufacturing nonvolatile semiconductor device 审中-公开
标题翻译：制造非易失性半导体器件的方法
公开(公告)号：JP2006302985A
公开(公告)日：2006-11-02
申请号：JP2005119282
申请日：2005-04-18
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： YASUI KAN , KIMURA SHINICHIRO , HISAMOTO MASARU , ISHIMARU TETSUYA
IPC分类号： H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/792 , G11C16/0425 , G11C16/0466 , H01L21/28282 , H01L27/105 , H01L27/11568 , H01L29/42344 , H01L29/66833
摘要： PROBLEM TO BE SOLVED: To suppress the variation in gate length of a memory transistor which is formed in a side wall structure.
SOLUTION: After forming a first insulation film on the principal plane of a semiconductor substrate, a first conductive film is formed on the first insulation film and then the front face of the first conductive film is flattened by CMP method (processes S10-S40). Then, the first conductive film and the first insulation film are etched to form a selection gate containing a first gate electrode and a first gate insulation film (process S50). After a second insulation film is formed on the side wall and principal plane of the first gate electrode, a second conductive film is formed on the second insulation film, and then the second conductive film is etched to form a memory gate containing a second gate electrode and a second gate insulation film (processes S60-S80).
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：抑制形成在侧壁结构中的存储晶体管的栅极长度的变化。解决方案：在半导体衬底的主平面上形成第一绝缘膜之后，在第一绝缘膜上形成第一导电膜，然后通过CMP方法将第一导电膜的前表面平坦化（工序S10- S40）。然后，蚀刻第一导电膜和第一绝缘膜，以形成包含第一栅极电极和第一栅极绝缘膜的选择栅极（工艺S50）。在第一栅电极的侧壁和主平面上形成第二绝缘膜之后，在第二绝缘膜上形成第二导电膜，然后蚀刻第二导电膜以形成包含第二栅电极的存储栅和第二栅极绝缘膜（处理S60-S80）。版权所有（C）2007，JPO＆INPIT

4. 发明专利

JP2006196643A Nonvolatile semiconductor memory device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2006196643A
公开(公告)日：2006-07-27
申请号：JP2005006081
申请日：2005-01-13
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： MINE TOSHIYUKI , KUME HITOSHI , MATSUZAKI NOZOMI , YASUI KAN
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device improved in the deterioration of Gm accompanying erasing operation.
SOLUTION: The nonvolatile semiconductor memory device comprises a selective MOS transistor where a nonvolatile memory includes a gate insulating film 102 and a selective gate electrode 103; a capacitance insulating film including a lower layer potential barrier film 104, a first charge holding film 105, and a second charge holding film 106; and a memory MOS transistor including a memory gate electrode 107. An Si nitride film containing stoichiometrically excessive Si is used for the first charge holding film 105, and an Si oxide nitride film is used for the second charge holding film.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种随着擦除操作而改善Gm劣化的非易失性半导体存储器件。解决方案：非易失性半导体存储器件包括选择性MOS晶体管，其中非易失性存储器包括栅极绝缘膜102和选择栅电极103; 包括下层势垒膜104，第一电荷保持膜105和第二电荷保持膜106的电容绝缘膜; 以及包括存储器栅电极107的存储器MOS晶体管。对于第一电荷保持膜105使用包含化学计量过量的Si的氮化硅膜，并且使用Si氧化物氮化物膜作为第二电荷保持膜。版权所有（C）2006，JPO＆NCIPI

5. 发明专利

JP2006054292A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2006054292A
公开(公告)日：2006-02-23
申请号：JP2004234335
申请日：2004-08-11
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： YASUI KAN , HISAMOTO MASARU , ISHIMARU TETSUYA
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/792 , G11C16/0466 , H01L27/115 , H01L27/11519 , H01L27/11568 , H01L29/42344
摘要： PROBLEM TO BE SOLVED: To shorten a period of manufacture and reduce a cost by reducing the number of sheets of additional masks needed to subject a nonvolatile memory to a standard CMOS logic process.
SOLUTION: In a split gate type memory cell utilizing a side wall structure with a silicided gate electrode, an isolated auxiliary pattern 22 is disposed adjacently to a selection gate electrode 12. Polysilicon of the side wall gate is filled in a gap between the selection gate electrode and the isolated auxiliary pattern, and a contact 21 is provided for a wiring part 23 formed in a self alignment manner. The contact 21 may be overlapped on the auxiliary pattern 22 and an element isolation region, whereby a design is optimized taking an occupation area into consideration. Assuming a distance between the contact and the selection gate electrode 12 to be x, a deposition thickness of an ONO film t, and a deposition thickness of the polysilicon film d, the auxiliary pattern 22 may be disposed while separating by the distance x satisfying a relation: x
摘要翻译：要解决的问题：通过减少使非易失性存储器进行标准CMOS逻辑处理所需的附加掩模的片数来缩短制造周期并降低成本。解决方案：在利用具有硅化物栅电极的侧壁结构的分裂栅型存储单元中，隔离辅助图案22邻近于选择栅电极12设置。侧壁栅极的多晶硅填充在选择栅极电极和隔离辅助图案，以及以自对准方式形成的布线部分23提供接触件21。触点21可以重叠在辅助图案22和元件隔离区域上，从而考虑到占用区域来优化设计。假设接触和选择栅电极12之间的距离为x，ONO膜t的沉积厚度以及多晶硅膜d的沉积厚度，辅助图案22可以分开一段距离x，关系：x <2×（t + d）。版权所有（C）2006，JPO＆NCIPI

6. 发明专利

JP2005353159A Nonvolatile semiconductor memory and its writing method 有权
标题翻译：非线性半导体存储器及其写入方法
公开(公告)号：JP2005353159A
公开(公告)日：2005-12-22
申请号：JP2004172078
申请日：2004-06-10
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： YASUI KAN , HISAMOTO MASARU , TANAKA TOSHIHIRO , YAMAKI TAKASHI
IPC分类号： G11C16/02 , G11C16/04 , G11C16/34 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： G11C16/3418 , G11C16/0466 , G11C16/3427 , H01L27/115 , H01L29/4232 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To prevent sequence disturbance which occurs dependent upon a path where biases in a standby state and a write state shift and in which a different memory cell on one and the same wordline is erroneously written or erased in a nonvolatile semiconductor memory device that uses a charge storage film. SOLUTION: In a procedure, a diffusion layer voltage Vs on a memory transistor side is changed and the gate voltage Vmg of the memory transistor is changed after the Vs exceeds the specified value Vsx of an intermediate stage regarding the rise and fall of a wordline bias. Alternatively, in a procedure, the gate voltage Vmg of the memory transistor is changed and the diffusion layer voltage Vs on the memory transistor side is changed after the Vmg exceeds the specified value Vmgx of an intermediate stage. The values Vsx and Vmgx are determined on the basis of the level of a gate insulating film electric field that does not cause FN electron injection which brings about a change in threshold voltage and the level of a potential barrier to a hole where a BTBT hot-hole injection does not occur. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了防止发生的序列干扰取决于在待机状态和写状态偏移处的偏差的路径，并且在一个和同一个字线上的不同存储器单元被错误地写入或擦除在非易失性存储器中的路径使用电荷存储膜的半导体存储器件。解决方案：在一个过程中，存储晶体管侧的扩散层电压Vs改变，并且在Vs超过关于上升和下降的中间阶段的规定值Vsx之后，存储晶体管的栅极电压Vmg改变字幕偏见或者，在程序中，在Vmg超过中间阶段的规定值Vmgx之后，存储晶体管的栅极电压Vmg改变，并且存储晶体管侧的扩散层电压Vs发生变化。基于不引起FN电子注入的栅极绝缘膜电场的电平来确定值Vsx和Vmgx，其导致阈值电压的变化和BTBT热敏电阻的孔的势垒的电平，空穴注入不会发生。版权所有（C）2006，JPO＆NCIPI

7. 发明专利

JP2009054687A Nonvolatile semiconductor device and its manufacturing method 有权
标题翻译：非线性半导体器件及其制造方法
公开(公告)号：JP2009054687A
公开(公告)日：2009-03-12
申请号：JP2007218147
申请日：2007-08-24
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： AKITA KENICHI , OKADA DAISUKE , KUWAHARA KEISUKE , MORIMOTO YASUSHI , SHIMAMOTO YASUHIRO , YASUI KAN , ARIKANE TAKESHI , ISHIMARU TETSUYA
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/66833 , H01L27/115 , H01L27/11563 , H01L27/11568 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a technique capable of raising a data holding characteristic in a nonvolatile memory which stores electric charges in an insulator. SOLUTION: An overlapped amount (Lono) of a charge storage layer CSL and a source region Srm is set to less than 40 nm by forming the charge storage layer CSL interposed between a memory gate electrode MG and a semiconductor substrate 1 shorter than a gate length of the memory gate electrode MG or lengths of insulating films 6t, 6b. Thereby, in a write status, holes stored in the charge storage layer CSL on the source region Srm, which is generated by repeated rewriting decrease, and horizontal movements of electrons and holes localizing in the charge storage layer CSL decrease. Consequently, a fluctuation of a threshold voltage at the time of storage at an elevated temperature can be made small. Moreover, if an effective channel length is set to 30 nm or less, since the number of apparent holes deciding the threshold voltage decreases and the combination of the electrons and holes in the charge storage layer CSL decreases, thus the fluctuation of the threshold voltage at the time of storage at a room temperature can be made small. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够提高在绝缘体中存储电荷的非易失性存储器中的数据保持特性的技术。解决方案：将电荷存储层CSL和源极区Srm的重叠量（Lono）设定为小于40nm，形成介于存储栅电极MG和半导体衬底1之间的电荷存储层CSL，存储栅电极MG的栅极长度或绝缘膜6t，6b的长度。因此，在写入状态下，存储在源区域Srm上的电荷存储层CSL中存储的反复重写产生的空穴减少，并且电荷存储层CSL中的电子和空穴的水平移动减小。因此，可以使在升高的温度下储存时的阈值电压的变动小。此外，如果将有效沟道长度设定为30nm以下，则由于决定阈值电压的表观空穴数减少，电荷存储层CSL中的电子和空穴的组合减少，所以阈值电压的波动在可以使室温下的储存时间变小。版权所有（C）2009，JPO＆INPIT

8. 发明专利

JP2008270343A Non-volatile semiconductor storage device 审中-公开
标题翻译：非挥发性半导体存储器件
公开(公告)号：JP2008270343A
公开(公告)日：2008-11-06
申请号：JP2007108145
申请日：2007-04-17
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： ISHIMARU TETSUYA , SHIMAMOTO YASUHIRO , YASUI KAN
IPC分类号： H01L21/8247 , G11C16/02 , G11C16/04 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/792 , G11C16/14 , H01L21/28282 , H01L29/42344 , H01L29/66833
摘要： PROBLEM TO BE SOLVED: To reduce an erasing current of a non-volatile semiconductor storage device. SOLUTION: A memory cell of the non-volatile semiconductor storage device includes a source region and a drain region formed on a semiconductor substrate. A select gate electrode is formed on a semiconductor substrate provided between the source region and drain region via a gate insulating film. At the side wall of the select gate electrode, a memory gate electrode is formed via a lower oxide silicon film and a silicon oxynitride film working as a charge accumulating film. Erasing operation is executed as explained below in the memory cell constituted as explained as above. Holes are injected to the silicon oxynitride film from the memory gate electrode by applying a positive voltage to the memory gate electrode in order to lower the threshold voltage up to a predetermined constant level from a threshold voltage in a write state. Thereafter, the erasing operation is ended by injecting hot holes generated by a tunneling phenomenon between bands to the silicon oxynitride film. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：减少非易失性半导体存储装置的擦除电流。解决方案：非易失性半导体存储器件的存储单元包括形成在半导体衬底上的源极区域和漏极区域。选择栅电极经由栅极绝缘膜形成在设置在源区和漏区之间的半导体衬底上。在选择栅电极的侧壁，通过作为电荷累积膜的低氧化硅膜和氧氮化硅膜形成存储栅电极。按照如上所述构成的存储单元，如下所述执行擦除操作。通过向存储栅电极施加正电压，将孔从存储栅电极注入到氧氮化硅膜中，以便从写入状态的阈值电压将阈值电压降低到预定的恒定电平。此后，通过将由带之间的隧道现象产生的热空穴注射到氮氧化硅膜上来结束擦除操作。版权所有（C）2009，JPO＆INPIT

9. 发明专利

JP2007243095A Semiconductor device and method of manufacturing same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2007243095A
公开(公告)日：2007-09-20
申请号：JP2006067088
申请日：2006-03-13
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： HISAMOTO MASARU , YASUI KAN , KIMURA SHINICHIRO , OKADA DAISUKE
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/792 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/42344 , H01L29/66833
摘要： PROBLEM TO BE SOLVED: To improve the reliability of a MONOS type nonvolatile memory.
SOLUTION: A memory cell is provided with a selection gate 6 and a memory gate 8 arranged on one side face of it. One part of the memory gate 8 is formed on one side face of the selection gate 6 and the other part is electrically separated from the selection gate 6 and a p-type well 2 through an ONO film 7 formed at the lower part of the memory gate 8. A sidewall-like silicon oxide film 12 is formed on the side face of the selection gate 6, and the sidewall-like silicon oxide film 9 and silicon oxide film 12 are formed on the side face of the memory gate. The ONO film 7 formed at the lower part of the memory gate 8 is terminated at the lower part of the silicon oxide film 9 and a low destruction pressure resistant region is prevented from being generated in the silicon oxide film 12 near the end of the memory gate 8 when the silicon oxide film 12 is deposited.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提高MONOS型非易失性存储器的可靠性。解决方案：存储单元设置有选择门6和布置在其的一个侧面上的存储器门8。存储栅极8的一部分形成在选择栅极6的一个侧面上，另一部分通过形成在存储器的下部的ONO膜7与选择栅极6和p型阱2电隔离在选择栅极6的侧面上形成侧壁状的氧化硅膜12，并且在存储栅极的侧面上形成侧壁状氧化硅膜9和氧化硅膜12。形成在存储栅极8的下部的ONO膜7终止在氧化硅膜9的下部，并且防止在靠近存储器端部的氧化硅膜12中产生低的耐破坏压力区域沉积氧化硅膜12时的栅极8。版权所有（C）2007，JPO＆INPIT

10. 发明专利

JP2006041354A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2006041354A
公开(公告)日：2006-02-09
申请号：JP2004221764
申请日：2004-07-29
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： HISAMOTO MASARU , YASUI KAN , KIMURA SHINICHIRO , ISHIMARU TETSUYA
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11568 , G11C16/0433 , H01L21/2815 , H01L21/28273 , H01L21/28282 , H01L21/84 , H01L27/115 , H01L27/11521 , H01L27/1203 , H01L29/66825 , H01L29/66833 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device having a superior readout current driving force even when a memory call is reduced.
SOLUTION: In the nonvolatile semiconductor memory device having a split gate structure, a memory gate is formed on a protruding type substrate, and its side surface is used as a channel.
COPYRIGHT: (C)2006,JPO&NCIPI

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