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1. 发明专利

JP2006318513A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2006318513A
公开(公告)日：2006-11-24
申请号：JP2006239176
申请日：2006-09-04
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： KAWAHARA TAKAYUKI , SHIMIZU TATEHISA , ARAKAWA FUMIO , MIZUNO HIROYUKI , WATABE TAKAO , ISHIBASHI KOICHIRO
IPC分类号： G06F1/32
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device with prediction type power control capable of constituting a low-powered system LSI with high scalability at possible design man-hours. SOLUTION: A prediction type power-supply cutoff circuit composed of a prediction circuit P and a power condition control circuit D is added to a functional logic circuit block K. The prediction circuit P controls the power condition of the circuit block K by the circuit D on the basis of information of input I to the circuit block K. For example, the circuit D shifts the power condition of the circuit block K to the low-powered condition when there is no input for more than a predetermined period. The system LSI formed by connecting a plurality of circuit blocks K added with the prediction circuit P and the power condition control circuit D can be shifted to the low-powered condition by self- distribution manner according to the condition of the input I independently of a calculating device wherein each circuit block K controls the whole system. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够在可能的设计时间下构建具有高可扩展性的低功率系统LSI的预测型功率控制的半导体器件。解决方案：将由预测电路P和功率条件控制电路D构成的预测型电源切断电路加到功能逻辑电路块K.预测电路P通过以下方式控制电路块K的功率状态电路D基于对电路块K的输入I的信息。例如，当没有输入超过预定周期时，电路D将电路块K的功率条件移动到低功率状态。通过将与预测电路P相加的多个电路块K与电力状态控制电路D相连接而形成的系统LSI，可以根据输入I的条件，以独立于计算装置，其中每个电路块K控制整个系统。版权所有（C）2007，JPO＆INPIT

2. 发明专利

JP2006079769A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2006079769A
公开(公告)日：2006-03-23
申请号：JP2004264780
申请日：2004-09-13
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： WATABE TAKAO , KOTABE AKIRA
IPC分类号： G11C11/412 , G11C11/41 , H01L21/8244 , H01L27/11
摘要： PROBLEM TO BE SOLVED: To achieve information holding without refresh, stable reading operation and low standby power requirement in a semiconductor device using a memory cell consisting of four transistors. SOLUTION: Capacitors C1 and C2 are provided to the storage nodes N1 and N2 of a memory cell MC to carry out rewriting after destructive read in the case of information reading and to hold the potential of the storage nodes N1 and N2 by leakage current flowing through transistors MP1 and MP2 by keeping bit lines BL and /BL to have a fixed potential in the case of information holding. In the case, impedance in the off state of transistors MN1 and MN2 is designated to be larger than the impedance in the off state of transistors MP1 and MP2. Moreover, by using a TFT transistor whose channel part is about 5 nm, the leakage current is reduced. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：在使用由四个晶体管组成的存储单元的半导体器件中实现不刷新的信息保持，稳定的读取操作和低待机功率要求。解决方案：在信息读取的情况下，将电容器C1和C2提供给存储单元MC的存储节点N1和N2以在破坏性读取之后进行重写，并且通过泄漏来保持存储节点N1和N2的电位在信息保持的情况下，通过使位线BL和/ BL保持固定电位，流过晶体管MP1和MP2的电流。在这种情况下，晶体管MN1，MN2的截止状态下的阻抗被指定为大于晶体管MP1，MP2的截止状态下的阻抗。此外，通过使用沟道部分为约5nm的TFT晶体管，泄漏电流降低。版权所有（C）2006，JPO＆NCIPI

3. 发明专利

JP2006018935A Semiconductor storage device 审中-公开
标题翻译：半导体存储设备
公开(公告)号：JP2006018935A
公开(公告)日：2006-01-19
申请号：JP2004196267
申请日：2004-07-02
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： KOTABE AKIRA , WATABE TAKAO , TAKEMURA RIICHIRO , KITAI NAOKI
IPC分类号： G11C11/412 , H01L21/8244 , H01L27/11
摘要： PROBLEM TO BE SOLVED: To provide a technology of securing the output signal of a memory cell constituted of four MOS transistors (two selection MOS transistors and two load MOS transistors) and two capacitative elements when reading in a semiconductor storage device having the memory cell . SOLUTION: Switch circuits (SWC0, and SWC1) for controlling the voltages of the sources of load MOS transistors (T0, and T1) are provided, and the switch circuits (SWC0, and SWC1) are respectively controlled by the voltages of word lines (WL0, and WL1). Thus, the currents of the load MOS transistors T0, and T1 which become problems during reading are suppressed, and the output signal of a memory cell (MC) is secured. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种确保由四个MOS晶体管（两个选择MOS晶体管和两个负载MOS晶体管）构成的存储单元的输出信号和两个电容元件的技术，当读取具有记忆单元
解决方案：提供用于控制负载MOS晶体管源（T0和T1）的电压的开关电路（SWC0和SWC1），并且开关电路（SWC0和SWC1）分别由字线（WL0和WL1）。因此，抑制了在读取期间成为问题的负载MOS晶体管T0和T1的电流，并且确保了存储单元（MC）的输出信号。版权所有（C）2006，JPO＆NCIPI

4. 发明专利

JP2005050514A Semiconductor integrated circuit 审中-公开
标题翻译：半导体集成电路
公开(公告)号：JP2005050514A
公开(公告)日：2005-02-24
申请号：JP2004249069
申请日：2004-08-27
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： KAWAHARA TAKAYUKI , KAWAJIRI YOSHIKI , AKIBA TAKESADA , HORIGUCHI SHINJI , WATABE TAKAO , KITSUKAWA GORO , KAWASE YASUSHI , TACHIBANA RIICHI , AOKI MASAKAZU
IPC分类号： H01L27/04 , G11C11/407 , H01L21/822 , H01L21/8234 , H01L27/088 , H03K19/00
摘要： PROBLEM TO BE SOLVED: To reduce current consumption during standing-by in a semiconductor integrated circuit using a fine MOS transistor.
SOLUTION: A voltage between the gate and source of the first MOS transistor in case both first and second MOS transistors are held off (T1=VC and I1=VC) is made into the polarity inverse from the polarity of a voltage between the gate and source of the first MOS transistor in case the first MOS transistor is on and the first MOS transistor is changed from off to on after the second MOS transistor is changed from off to on.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了减少使用精细MOS晶体管的半导体集成电路中的待机时的电流消耗。解决方案：在第一和第二MOS晶体管两者的情况下（T1 = VC和I1 = VC）的情况下，第一MOS晶体管的栅极和源极之间的电压从第二MOS晶体管的栅极和源极之间的电压变为极性，在第一MOS晶体管导通的情况下第一MOS晶体管的栅极和源极以及在第二MOS晶体管从截止状态变为导通之后第一MOS晶体管从截止状态变为导通状态。版权所有（C）2005，JPO＆NCIPI

5. 发明专利

JP2009123298A Semiconductor integrated circuit device 审中-公开
标题翻译：半导体集成电路设备
公开(公告)号：JP2009123298A
公开(公告)日：2009-06-04
申请号：JP2007297479
申请日：2007-11-16
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： KAJIYAMA SHINYA , SHINAGAWA YUTAKA , MIZUNO MAKOTO , KASAI HIDEO , WATABE TAKAO , TAKEMURA RIICHIRO , SEKIGUCHI TOMONORI
IPC分类号： G11C16/02 , G06F12/00 , G11C16/04
CPC分类号： G11C7/1039 , G11C7/1075 , G11C16/26
摘要： PROBLEM TO BE SOLVED: To achieve access with low latency even when there is contention of access requests from a plurality of CPUs. SOLUTION: A first latch circuit 104 capable of holding an output-signal of an X decoder 121 and transmitting it to a word driver 106 is arranged at a post stage of the X decoder 121. A second latch circuit 105 capable of holding an output signal of a Y decoder 122 and transmitting it to a Y selection circuit is arranged at a post stage of the Y decoder 122. A third latch circuit 110 capable of holding an output signal of a sense amplifier 108 and transmitting it to output circuit 111, 112 is arranged at a post stage of the sense amplifier 108. Thus, a series of processing in the readout of storage data of a nonvolatile semiconductor memory is pipelined, and the access with low latency is allowed even when there is the contention of access requests from the plurality of CPUs. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：即使当存在来自多个CPU的访问请求的争用时，也可以以低延迟实现访问。解决方案：能够保持X解码器121的输出信号并将其发送到字驱动器106的第一锁存电路104被布置在X解码器121的后级。能够保持的第二锁存电路105 Y解码器122的输出信号并将其发送到Y选择电路被布置在Y解码器122的后级。第三锁存电路110能够保持读出放大器108的输出信号并将其发送到输出电路 111,112被布置在读出放大器108的后级。因此，在非易失性半导体存储器的存储数据的读出中的一系列处理被流水线化，并且即使在存在争用的情况下也允许具有低等待时间的访问来自多个CPU的访问请求。版权所有（C）2009，JPO＆INPIT

6. 发明专利

JP2006190402A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2006190402A
公开(公告)日：2006-07-20
申请号：JP2005002024
申请日：2005-01-07
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： ATWOOD BRYAN , WATABE TAKAO
IPC分类号： G11C11/401 , G06F12/08 , G06F12/12
CPC分类号： G11C7/1075 , G11C11/4076 , G11C2207/2245
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which can make high speed access and incorporate a large capacity memory. SOLUTION: This semiconductor device requires cycles twice the reading cycles when writing, and has memory banks (Bank) 0-3 each having its own write and read ports and two cache data banks CD0, CD1 each having a memory as large as one of the above memory banks based on the above doubled cycle. When instructed from the outside to write series of cycles, for example, it can not write back the data of the memory bank 2 stored on row 2 in the CD1 in cycles #2 since the memory bank 2 is busy by cycles #1, but instead, can write back the data of the memory bank 0 stored on row 2 in the CD0. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种可以进行高速存取并结合大容量存储器的半导体器件。
解决方案：这种半导体器件在写入时需要读取周期的两倍周期，并且具有各自具有自己的写入和读取端口的存储体（存储体）0-3和两个高速缓存数据组CD0，CD1，每个具有大于上述记忆库之一基于上述两倍的周期。例如，当从外部指示写入一系列循环时，由于存储器组2由循环＃1而忙，所以不能在循环＃2中将存储在存储器2中的存储器组2的数据写回到CD1中，而是可以将CD0中存储在行2上的存储体0的数据写回来。版权所有（C）2006，JPO＆NCIPI

7. 发明专利

JP2007066517A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2007066517A
公开(公告)日：2007-03-15
申请号：JP2006304652
申请日：2006-11-10
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： MIZUNO HIROYUKI , WATABE TAKAO , SUGANO YUSUKE
IPC分类号： G11C11/408 , G11C11/401
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device equipped with a memory circuit of which the pipeline packing density is increased when a read and write are coexistent. SOLUTION: The semiconductor device comprises the memory circuit including: a plurality of dynamic memory cells arranged at respective crossed positions of bit lines and a plurality of word lines; row decoders connected to the plurality of word lines; and row address latch circuits latching read and write row addresses at a transition point of a clock signal and having operation to supply the addresses to the row decoders. The data are read out from the dynamic memories by a read-out of destruction. The row address latch circuits include write-in delaying circuits having the operation to delay the supply of the write row addresses (where, they are not the read row addresses) to the row decoders by the clock signal having at least the prescribed number of cycles. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种配备有当读取和写入共存时管道堆积密度增加的存储器电路的半导体器件。解决方案：半导体器件包括存储器电路，其包括：布置在位线和多个字线的各个交叉位置处的多个动态存储器单元; 连接到所述多个字线的行解码器; 和行地址锁存电路在时钟信号的转换点处锁存读和写行地址，并具有将地址提供给行解码器的操作。数据通过读出的破坏从动态存储器中读出。行地址锁存电路包括写入延迟电路，其具有通过具有至少规定次数的周期的时钟信号来延迟向行解码器提供写入行地址（其中它们不是读取行地址）的操作的操作。版权所有（C）2007，JPO＆INPIT

8. 发明专利

JP2005079360A Semiconductor integrated circuit 审中-公开
标题翻译：半导体集成电路
公开(公告)号：JP2005079360A
公开(公告)日：2005-03-24
申请号：JP2003308326
申请日：2003-09-01
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： WATABE TAKAO , TAKAHASHI YASUHIKO , SAKATA TAKESHI , YANAGISAWA KAZUMASA
IPC分类号： H01L27/108 , H01L21/8242 , H01L27/04 , H01L29/78 , H01L29/786 , H03K3/356
摘要： PROBLEM TO BE SOLVED: To solve the following problems: when a state of a logic circuit in a latch circuit is held at the time of power switch-off, a leakage of a current cannot be completely decreased or a long time holding is difficult to consume the power required for a refleshing by the conventional technology. SOLUTION: A typical circuit is provided by a field effect transistor composed of a polycrystal thin film having a channel region of not more than 5 nm, and a dynamic latch composed of a CMOS circuit with the transistor connected to its gate input terminal. This holds the state of the logic circuit at the time of a shut-off of the power switch. Further, the power switch is provided at every circuit block. When a failure is found in the information holding means at the time of a test, the power switch of the function block is kept conductive even the block is not used. Further, the power switch is tuned off and the state of the logic circuit can be held in the dynamic latch in an unused circuit block even at the time of operation of the whole semiconductor integrated circuit. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：解决以下问题：为了解决以下问题：当在断电时保持锁存电路中的逻辑电路的状态时，电流的泄漏不能完全降低或长时间保持难以消耗由传统技术引起的反射所需的功率。解决方案：典型的电路由具有沟道区不大于5nm的多晶薄膜构成的场效应晶体管和由晶体管连接到其栅极输入端的CMOS电路构成的动态锁存器。这保持在电源开关切断时逻辑电路的状态。此外，在每个电路块处提供电源开关。当在测试时在信息保持装置中发现故障时，即使不使用块，功能块的电源开关也保持导通。此外，即使在整个半导体集成电路的操作时，电源开关被关闭，并且逻辑电路的状态也可以保持在未使用的电路块中的动态锁存器中。版权所有（C）2005，JPO＆NCIPI

9. 发明专利

JP2004362765A Semiconductor device 有权
公开(公告)号：JP2004362765A
公开(公告)日：2004-12-24
申请号：JP2004208733
申请日：2004-07-15
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： AYUKAWA KAZUSHIGE , WATABE TAKAO , NAKAGOME YOSHINOBU
IPC分类号： G06F12/00 , G11C11/401 , G11C11/409
摘要： PROBLEM TO BE SOLVED: To facilitate an access from the outside in a semiconductor integrated circuit in which a high integration memory and a plurality of arithmetic circuits are integrated on one chip.
SOLUTION: This device is provided with a first serial access memory performing delivery and receipt of data with the memory cell array and a second serial access memory performing delivery and receipt of data with the plurality of arithmetic circuit 40 in addition to a memory cell array 10 holding data and a plurality of arithmetic circuit 40 performing receiving operation.
COPYRIGHT: (C)2005,JPO&NCIPI

10. 发明专利

JP2008084529A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2008084529A
公开(公告)日：2008-04-10
申请号：JP2007287140
申请日：2007-11-05
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： MIZUNO HIROYUKI , SAKATA TAKESHI , OHIRA NOBUHIRO , WATABE TAKAO , SUGANO YUSUKE
IPC分类号： G11C11/4091 , G11C11/4096
摘要： PROBLEM TO BE SOLVED: To provide a sense circuit for DRAM memory cells that deals with the problems that as the source-supply voltage is lowered more and more, the sense time becomes considerably longer, that the sense time for lower voltage is shorter at high temperature, that the sense time greatly varies with process variation, etc. SOLUTION: Typical means for solution is as follows. A switch means is provided between memory-cell-connected bit lines BL and local bit lines LBL to allow separation and connection, the BL being VDL/2 precharged, the LBL being VDL precharged. The VDL is a maximum amplitude voltage in the bit lines BL. SA includes a first circuit including differential MOS pairs for gate support connected to BL and a second circuit connected to LBL for full amplitude amplification and data retention. When it is desired to capacitance-connect BL and LBL through a capacitor, it is preferable that SA is a latch type SA connected to LBL. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了提供用于DRAM存储单元的感测电路，其处理随着源电压降低越来越多的问题，感测时间变得更长，低电压的感测时间是在高温下较短，感应时间随工艺变化等而变化很大。解决方案：解决方案的典型手段如下。在存储单元连接的位线BL和局部位线LBL之间提供开关装置以允许分离和连接，BL为VDL / 2预充电，LBL为VDL预充电。 VDL是位线BL中的最大幅度电压。 SA包括包括连接到BL的门支持的差分MOS对的第一电路和连接到LBL的用于全幅幅放大和数据保持的第二电路。当希望通过电容器将BL和LBL电容连接时，优选地，SA是连接到LBL的闩锁型SA。版权所有（C）2008，JPO＆INPIT

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