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1. 发明专利

JP2007250186A Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2007250186A
公开(公告)日：2007-09-27
申请号：JP2007179246
申请日：2007-07-09
申请人： Hitachi Ulsi Systems Co Ltd , Renesas Technology Corp , 株式会社ルネサステクノロジ , 株式会社日立超エル・エス・アイ・システムズ
发明人： TAKASE KENJUN , KURATA HIDEAKI , YOSHIDA KEIICHI , MATSUBARA KEN , KANEMITSU MICHITARO , YUASA SHINJI
IPC分类号： G11C16/02 , G11C16/04
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device in which increasing erasing operation speed can be achieved by optimizing erasing operation in memory array constitution in which a plurality of pages are connected respectively to respective word lines of a plurality of word lines. SOLUTION: The erasing operation is an erasing system in which a plurality of pages selected arbitrarily are erased in block in a flash memory, in a two page erasing mode, page erasing, page pre-erasing verify, page rewriting processing, page pre-rewriting-verify, and page upper edge discrimination processing are performed in this order, especially, [1] variation of erasing properties is considered, the number of times of erasing-verify can be suppressed by performing erasing-verify only for arbitrary one page of even number page or odd number page out of erasing object pages, [2] erasing upper edge defect can be prevented by performing continuously rewriting processing one page by one page of even number page and odd number page as a memory cell of object of rewriting is not required to set for each rewriting-verify. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决的问题：提供一种非易失性半导体存储器件，其中可以通过优化多个页面分别连接到多个字的各个字线的存储器阵列结构中的擦除操作来实现增加擦除操作速度线。解决方案：擦除操作是一种擦除系统，其中任意选择的多个页面在闪速存储器中以块擦除模式，页面擦除，页面预擦除验证，页面重写处理，页面特别是考虑了擦除特性的变化，可以通过仅对任意一个执行擦除验证来抑制擦除验证的次数通过连续重写一页一页偶数页和奇数页作为对象的存储单元，可以防止擦除对象页的偶数页或奇数页的页面，[2]擦除上边缘缺陷不需要为每次重写验证设置重写。版权所有（C）2007，JPO＆INPIT

2. 发明专利

JP2003338183A Nonvolatile memory 审中-公开
标题翻译：非易失性存储器
公开(公告)号：JP2003338183A
公开(公告)日：2003-11-28
申请号：JP2002146987
申请日：2002-05-22
申请人： Hitachi Ulsi Systems Co Ltd , Renesas Technology Corp , 株式会社ルネサステクノロジ , 株式会社日立超エル・エス・アイ・システムズ
发明人： YUASA SHINJI , KANEMITSU MICHITARO , TAKASE KENJUN , KURATA HIDEAKI
IPC分类号： G11C16/02 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a multi-value nonvolatile memory in which highly accurate and high speed write operation can be performed with a simple constitution. SOLUTION: In write operation for a memory array in which memory cells provided with a third gate controlling a write current flowing among a floating gate, a control gate, a source of a memory cell, and a drain are arranged in a lattice, a highly accurate and high speed write operation is realized with simple constitution by setting voltage given to the third gate out of a plurality of voltage given to the memory array to the prescribed voltage after variation of the other voltage is finished. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供一种能够以简单的结构执行高精度和高速写入操作的多值非易失性存储器。解决方案：在存储器阵列的写入操作中，其中设置有控制在浮动栅极，控制栅极，存储器单元的源极和漏极之间流动的写入电流的第三栅极的存储器单元布置在晶格中通过在另一个电压的变化完成之后，通过将给予存储器阵列的多个电压中施加给第三栅极的电压设置为规定电压，以简单的结构实现高精度和高速写入操作。版权所有（C）2004，JPO

3. 发明专利

JP2007200545A Nonvolatile semiconductor memory device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2007200545A
公开(公告)日：2007-08-09
申请号：JP2007096613
申请日：2007-04-02
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： KURATA HIDEAKI , KOBAYASHI NAOKI , SAEKI SHUNICHI , KOBAYASHI TAKASHI , KAWAHARA TAKAYUKI , TAKASE KENJUN , YOSHIDA KEIICHI , KANEMITSU MICHITARO , KUBONO SHOJI , NOZOE ATSUSHI
IPC分类号： G11C16/02 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To achieve high speed writing by reducing a variation in the write performance of a nonvolatile semiconductor memory device. SOLUTION: At the write operation of the nonvolatile semiconductor memory device, an electric charge is accumulated in a certain capacity provided at each write-in cell and the write is carried out by injecting hot electrons generated when the charge is discharged via a memory cell into a floating gate. Thus, the variation in the write performance of the nonvolatile semiconductor memory device is reduced, thereby the high speed writing is achieved. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：通过减少非易失性半导体存储器件的写入性能的变化来实现高速写入。解决方案：在非易失性半导体存储器件的写入操作中，以每个写入单元提供的特定容量累积电荷，并且通过注入通过经由存储单元进入浮动门。因此，降低了非易失性半导体存储器件的写入性能的变化，从而实现了高速写入。版权所有（C）2007，JPO＆INPIT

4. 发明专利

JP2006190488A Write-in method in semiconductor memory device 审中-公开
标题翻译：半导体存储器件中的写入方法
公开(公告)号：JP2006190488A
公开(公告)日：2006-07-20
申请号：JP2006110531
申请日：2006-04-13
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： KANEMITSU MICHITARO , TSUJIKAWA TETSUYA
IPC分类号： G11C16/02 , G11C16/06
摘要： PROBLEM TO BE SOLVED: To provide a write-in method in a semiconductor memory device capable of attaining high speed of write-in while controlling memory threshold voltages at the time of write-in with high accuracy. SOLUTION: In the write processing of a 265Mb-multivalue flash EEPROM, the write processing of , for example, "01" executes data latch processing for selecting an objective bit line after write-in (224) after all bits to be written are determined to be passed by data latch processing (221), write-in processing (222) and write-in verifying processing (223), and performs write-in verifying processing to an initial value (225). As a result, when even a bit which is determined to have passed verification by a certain cause in the course of the write-in processing of "01", if it is determined to be failed by this operation, a write-in voltage is applied again, and the bit can be made to have a prescribed threshold voltage. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种能够以高精度写入时在控制存储器阈值电压的同时实现高速写入的半导体存储器件中的写入方法。解决方案：在265Mb多值闪存EEPROM的写入处理中，例如“01”的写入处理执行用于在所有位之后的写入（224）之后选择目标位线的数据锁存处理写入被确定为通过数据锁存处理（221），写入处理（222）和写入验证处理（223）传递，并且对初始值（225）执行写入验证处理。结果，当在“01”的写入处理过程中甚至被确定已经通过某种原因的验证的位时，如果通过该操作被确定为失败，则写入电压为再次施加，并且可以使该位具有规定的阈值电压。版权所有（C）2006，JPO＆NCIPI

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