专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2009016039A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2009016039A
公开(公告)日：2009-01-22
申请号：JP2008269593
申请日：2008-10-20
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： YAMAOKA MASANAO , OSADA KENICHI , YANAGISAWA KAZUMASA
IPC分类号： G11C11/418 , G11C11/413
摘要： PROBLEM TO BE SOLVED: To solve the problem that power consumption is increased in an unoperated state while storing data caused by an increase in leakage current of a transistor which occurs when a threshold voltage of the transistor configured to operate a SRAM circuit at a low voltage is reduced. SOLUTION: The leakage current of a MOS transistor in a memory cell is reduced by controlling the potential of the source line ss1 of a driving MOS transistor in a SRAM memory cell MC. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了解决在未操作状态下功耗增加的问题，同时存储由配置为操作SRAM电路的晶体管的阈值电压引起的晶体管的漏电流增加引起的数据降低了低电压。解决方案：通过控制SRAM存储单元MC中的驱动MOS晶体管的源极线ss1的电位来减小存储单元中的MOS晶体管的漏电流。版权所有（C）2009，JPO＆INPIT

2. 发明专利

JP2008182004A Semiconductor integrated circuit 审中-公开
标题翻译：半导体集成电路
公开(公告)号：JP2008182004A
公开(公告)日：2008-08-07
申请号：JP2007013361
申请日：2007-01-24
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： OSADA KENICHI , YAMAOKA MASANAO , KOMATSU SHIGENOBU
IPC分类号： H01L21/8238 , H01L21/82 , H01L21/822 , H01L21/8234 , H01L27/04 , H01L27/06 , H01L27/08 , H01L27/092 , H01L29/786 , H03K19/0948
CPC分类号： H03K19/0008 , H03K2217/0018
摘要： PROBLEM TO BE SOLVED: To adopt a substrate bias technique in an active mode enabling a high yield on a manufacture while reducing the fluctuation of the operation consumption power and quantity of signal delay of signal processing in the active mode. SOLUTION: An additional PMOS Qp4 and an additional NMOS Qn4 for an additional capacity circuit CC1 are manufactured by the same manufacturing process as PMOSs and NMOSs for CMOS circuits STC1, 2 and 3. The gate capacity of the additional PMOS Qp4 is connected between a power-supply wiring Vdd - M and an N well N - Well, and the gate capacity of the additional NMOS Qn4 is connected between a ground wiring Vss - M and a P well P - Well. The noises of the power-supply wiring Vdd - M are transmitted to the N well N - Well through the gate capacity Cqp04, and the noises of the ground wiring Vss - M are transmitted to the P well P - Well through the gate capacity Cqn04. The noise fluctuations of substrate bias voltages between sources and wells for the PMOSs and the NMOSs for the CMOS circuits STC1, 2 and 3 are reduced. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：采用主动模式的衬底偏置技术，能够在制造过程中实现高产率，同时减少工作消耗功率的波动和活动模式下信号处理的信号延迟量。解决方案：通过与CMOS电路STC1,2和3的PMOS和NMOS相同的制造工艺制造用于附加电容电路CC1的附加PMOS Qp4和附加NMOS Qn4。附加PMOS Qp4的栅极电容连接在电源布线Vdd - M和N阱N 之间，并且附加NMOS Qn4的栅极电容连接在接地布线Vss - ＆lt; / SB＆gt; M和P井P - 井。电源布线Vdd - M的噪声通过栅极容量Cqp04传输到N阱N 阱，并且接地布线Vss - M通过栅极容量Cqn04传输到P阱P - 。用于PMOS和用于CMOS电路STC1,2和3的NMOS的源极和阱之间的衬底偏置电压的噪声波动被减小。版权所有（C）2008，JPO＆INPIT

3. 发明专利

JP2005235280A Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：JP2005235280A
公开(公告)日：2005-09-02
申请号：JP2004042217
申请日：2004-02-19
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： ISODA MASANORI , YAMAOKA MASANAO
IPC分类号： G11C11/413 , G11C5/14 , G11C11/00 , G11C11/412
CPC分类号： G11C5/147 , G11C11/412
摘要： PROBLEM TO BE SOLVED: To suppress damaging data of static memory cells due to variation in an operating power source by suppressing a sub-threshold leak current. SOLUTION: This semiconductor integrated circuit comprises a pair of power source wiring (10, 11), a plurality of static memory cells (18), a voltage control circuit (20) for controlling an operation voltage to be applied to the static memory cells from the power source wiring, a monitor circuit (21) for monitoring the voltage of the power source wiring, and a mode control circuit (5) for controlling an operation mode. The monitor circuit can detect variation of reducing a potential difference between the pair of power source wiring. The voltage control circuit can control to decrease the potential difference between a pair of power source nodes of the static memory cells in response to the instruction of a low power consumption mode by the mode control circuit, and can control to increase the potential difference between a pair of power source nodes of the static memory cells in response to the instruction of the detection of reduction in the potential difference between the pair of power source wiring by the monitor circuit. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：通过抑制次阈值泄漏电流来抑制由于工作电源的变化而引起的静态存储单元的损坏数据。解决方案：该半导体集成电路包括一对电源布线（10,11），多个静态存储单元（18），用于控制要施加到静态的操作电压的电压控制电路（20）来自电源布线的存储单元，用于监视电源布线的电压的监视电路（21）以及用于控制操作模式的模式控制电路（5）。监控电路可以检测减小一对电源线之间的电位差的变化。电压控制电路可以通过模式控制电路来控制降低静态存储单元的一对电源节点之间的电位差，并且可以控制增加一个电位差响应于监测电路对一对电源布线之间的电位差检测的指令，静态存储单元的一对电源节点。版权所有（C）2005，JPO＆NCIPI

4. 发明专利

JP2010067343A Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：JP2010067343A
公开(公告)日：2010-03-25
申请号：JP2009288879
申请日：2009-12-21
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： ISODA MASANORI , YAMAOKA MASANAO
IPC分类号： G11C11/413
摘要： PROBLEM TO BE SOLVED: To suppress data corruption of static memory cells due to variation in an operating power source by suppressing a sub-threshold leak current. SOLUTION: The semiconductor integrated circuit includes: a pair of power source wirings (10, 11), a plurality of static memory cells (18), a voltage control circuit (20) for controlling an operation voltage to be applied to the static memory cells from the power source wiring, a monitor circuit (21) for monitoring the voltage of the power source wiring, and a mode control circuit (5) for controlling an operation mode. The monitor circuit detects variation of reducing a potential difference between the pair of power source wirings. The voltage control circuit decreases the potential difference between a pair of power source nodes of the static memory cells in response to an instruction of a low power consumption mode by the mode control circuit, and increases the potential difference between a pair of power source nodes of the static memory cells in response to the detection of reduction in the potential difference between the pair of power source wirings by the monitor circuit. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：通过抑制子阈值泄漏电流来抑制由于工作电源的变化而引起的静态存储单元的数据损坏。解决方案：半导体集成电路包括：一对电源布线（10,11），多个静态存储单元（18），用于控制施加到所述电源线的操作电压的电压控制电路（20）来自电源布线的静态存储单元，用于监视电源布线的电压的监视电路（21）以及用于控制运行模式的模式控制电路（5）。监视器电路检测减小一对电源布线之间的电位差的变化。电压控制电路响应于模式控制电路的低功耗模式的指令而减小静态存储单元的一对电源节点之间的电位差，并且增加一对电源节点之间的电位差静态存储单元响应于监测电路检测一对电源布线之间的电位差的检测。版权所有（C）2010，JPO＆INPIT

5. 发明专利

JP2009004087A Semiconductor integrated circuit device 审中-公开
标题翻译：半导体集成电路设备
公开(公告)号：JP2009004087A
公开(公告)日：2009-01-08
申请号：JP2008214165
申请日：2008-08-22
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： ISHIBASHI KOICHIRO , YADORI SHOJI , YANAGISAWA KAZUMASA , NISHIMOTO JUNICHI , YAMAOKA MASANAO , AOKI MASAKAZU
IPC分类号： G11C29/04 , G11C11/413 , G11C16/02 , G11C16/06 , G11C29/12 , G11C29/44
CPC分类号： H01L2924/14
摘要： PROBLEM TO BE SOLVED: To reduce a circuit area of a program bit when a multi-bit configuration is employed. SOLUTION: A semiconductor integrated circuit device includes first and second non-volatile memory cells (224 to 226) having a first conductivity type first semiconductor region and a second conductivity type second semiconductor region, a second conductivity type source region and drain region formed in the first semiconductor region, and a gate electrode formed separated from the first semiconductor region and the second conductivity region via an insulating film, and a control circuit (220) for generating a control signal for writing or reading the first and second non-volatile memory cells. The control circuit is provided adjacent to the first non-volatile memory cell in a first direction. A signal line for applying the control signal to the non-volatile cell is extended in the first direction from the control circuit. Thereby, the area of a program bit in the multi-bit configuration is reduced. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：当采用多位配置时，减少程序位的电路面积。解决方案：半导体集成电路器件包括具有第一导电类型的第一半导体区域和第二导电型第二半导体区域的第一和第二非易失性存储单元（224至226），第二导电类型源极区域和漏极区域形成在第一半导体区域中的栅极电极和经由绝缘膜与第一半导体区域和第二导电区域分离形成的栅电极，以及用于产生用于写入或读取第一和第二非易失性存储器的控制信号的控制电路，易失性记忆体。控制电路在第一方向上与第一非易失性存储单元相邻设置。用于将控制信号施加到非易失性单元的信号线在控制电路的第一方向上延伸。因此，减少了多位配置中的程序位的区域。版权所有（C）2009，JPO＆INPIT

6. 发明专利

JP2008135169A Semiconductor storage device 审中-公开
标题翻译：半导体存储设备
公开(公告)号：JP2008135169A
公开(公告)日：2008-06-12
申请号：JP2007330233
申请日：2007-12-21
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： YAMAOKA MASANAO , OSADA KENICHI , ISHIBASHI KOICHIRO
IPC分类号： G11C11/413 , G11C11/412 , H01L21/8244 , H01L27/10 , H01L27/11
摘要： PROBLEM TO BE SOLVED: To overcome the problem in a conventional SRAM memory cell for low-voltage operation that a static noise margin, which is an operation margin for a memory cell, decreases when a threshold of an MOS transistor configuring the memory cell is lowered.
SOLUTION: A configuration is adopted where a power supply voltage Vdd', which is higher than a power supply voltage Vdd of a peripheral circuit power line 2, is supplied to a memory cell array 30 from a memory cell power line 4 as a power supply voltage of the memory cell. A conductance of a drive MOS transistor increases, so that the threshold of the MOS transistor can be lowered without decreasing the static noise margin, and the ratio of a gate width between the drive MOS transistor and a transfer MOS transistor can be set 1. Consequently it is possible to reduce a memory cell area.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题为了克服用于低电压操作的常规SRAM存储单元中的问题，当构成存储器的MOS晶体管的阈值时，作为存储单元的操作余量的静态噪声容限减小细胞降低解决方案：采用一种配置，其中高于外围电路电力线2的电源电压Vdd的电源电压Vdd'从存储单元电力线4提供给存储单元阵列30，存储单元的电源电压。驱动MOS晶体管的电导增加，从而可以降低MOS晶体管的阈值而不降低静态噪声容限，并且可以将驱动MOS晶体管和转移MOS晶体管之间的栅极宽度的比率设置为1。可以减少存储单元面积。版权所有（C）2008，JPO＆INPIT

7. 发明专利

JP2008004218A Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路设备
公开(公告)号：JP2008004218A
公开(公告)日：2008-01-10
申请号：JP2006174725
申请日：2006-06-26
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： KOMATSU SHIGENOBU , YAMAOKA MASANAO
IPC分类号： G11C11/41
CPC分类号： G11C8/08 , G11C8/18 , G11C11/412
摘要： PROBLEM TO BE SOLVED: To provide technology for reducing area of a semiconductor integrated circuit device, on which a time division multi-port memory and the like are mounted.
SOLUTION: The device is composed of: a single port memory 1PRAM; data latch circuit LIN_1 to 3, LOUT_1 to 3 for multiple ports, a selector SELECT selecting a port connected to the single port memory 1PRAM; a time division control signal generating circuit PCONT; and the like. An operation finish signal ack (a word line falling signal, a sense amplifier drive signal for reading out data, or the like) are inputted into a time division control signal generating circuit PCONT, and a port switching control signal s_0 tp 3 and an operation control signal ck_mem of the single port memory 1PRAM are generated, so that a new clock generating circuit for time-division control is not required, thetreby obtaing the small-area time division multi-port memory.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种减少其上安装有时分多端口存储器等的半导体集成电路器件的面积的技术。
解决方案：设备由单端口存储器1PRAM组成; 数据锁存电路LIN_1至3，多个端口的LOUT_1至3，选择器SELECT选择连接到单端口存储器1PRAM的端口; 时分控制信号发生电路PCONT; 等等。操作完成信号ack（字线下降信号，用于读出数据的读出放大器驱动信号等）被输入到时分控制信号发生电路PCONT，以及端口切换控制信号s_0 tp 3和操作生成单端口存储器1PRAM的控制信号ck_mem，从而不需要用于时分控制的新的时钟发生电路，因此遵循小区域时分多端口存储器。版权所有（C）2008，JPO＆INPIT

8. 发明专利

JP2007157324A Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路设备
公开(公告)号：JP2007157324A
公开(公告)日：2007-06-21
申请号：JP2007029971
申请日：2007-02-09
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： ISHIBASHI KOICHIRO , YADORI SHOJI , YANAGISAWA KAZUMASA , NISHIMOTO JUNICHI , YAMAOKA MASANAO , AOKI MASAKAZU
IPC分类号： G11C29/04 , G11C11/413 , G11C16/06
CPC分类号： H01L2924/14
摘要： PROBLEM TO BE SOLVED: To prevent stored information from being destructed by voltage long period impression in a nonvolatile memory for storing relief address information or trimming information. SOLUTION: Read voltage for reading the relief address information or the trimming information, stored in the nonvolatile memory, from the memory cell of the nonvolatile memory, is impressed responding to power-on/reset for a semiconductor integrated circuit. The nonvolatile memory cell has a first semiconductor area of a first conductive type and a second semiconductor area of a second conductive type, a source area and a drain area of the second conductive type formed in the first semiconductor area, and a gate electrode formed in the first semiconductor area and the second semiconductor area via an insulation film, respectively. Writing and reading are made possible by impressing designated voltage to the source area and the drain area, and the second semiconductor area. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了防止存储的信息在用于存储释放地址信息或修剪信息的非易失性存储器中被电压长时间印象破坏。解决方案：响应于半导体集成电路的上电/复位，读出从非易失性存储器的存储单元读取存储在非易失性存储器中的浮动地址信息或修整信息的读取电压。非易失性存储单元具有第一导电类型的第一半导体区域和形成在第一半导体区域中的第二导电类型的第二半导体区域，第二导电类型的源极区域和漏极区域以及形成在第一半导体区域中的栅电极第一半导体区域和第二半导体区域分别经由绝缘膜。通过向源极区域和漏极区域以及第二半导体区域施加指定的电压来进行写入和读取。版权所有（C）2007，JPO＆INPIT

9. 发明专利

JP2006085786A Semiconductor integrated circuit apparatus 有权
标题翻译：半导体集成电路设备
公开(公告)号：JP2006085786A
公开(公告)日：2006-03-30
申请号：JP2004267645
申请日：2004-09-15
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： MAEDA NORIAKI , SHINOZAKI YOSHIHIRO , YAMAOKA MASANAO , SHIMAZAKI YASUHISA , ISODA MASANORI , ARAI KOJI
IPC分类号： G11C11/413 , G11C11/41 , H01L21/8244 , H01L27/11
CPC分类号： G11C11/412 , G11C5/063 , G11C5/14 , G11C11/419 , H01L27/11 , H01L27/1104
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit apparatus provided with a static type RAM in which both SNM and margin can be realized even in low power source voltage.
SOLUTION: This apparatus is provided with a plurality of static type memory cells provided corresponding to a plurality of word lines and a plurality of complementary bit lines, a plurality of memory cell power source lines supplying operation voltage for each of the plurality of memory cells connected respectively to the plurality of complementary bit lines are provided, a plurality of power source supply circuit consisting of a resistance means supplying respectively power source voltage corresponding to these memory cell power source lines are provided, a pre-charge circuit supplying pre-charge voltage corresponding to the power source voltage to the complementary bit lines is provided, the memory cell power source line has coupling capacity to which a write-in signal of the corresponding complementary bit line is transmitted.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种具有静态RAM的半导体集成电路装置，其中即使在低电源电压下也可以实现SNM和余量。解决方案：该装置具有与多个字线和多个互补位线对应地设置的多个静态型存储单元，多个存储单元电源线为多个字线中的每一个提供工作电压提供分别连接到多个互补位线的存储单元，提供由分别提供与这些存储单元电源线相对应的电源电压的电阻装置组成的多个电源电源电路，提供与互补位线的电源电压对应的充电电压，存储单元电源线具有发送对应的互补位线的写入信号的耦合电容。版权所有（C）2006，JPO＆NCIPI

10. 发明专利

JP2006085785A Semiconductor integrated circuit apparatus 审中-公开
标题翻译：半导体集成电路设备
公开(公告)号：JP2006085785A
公开(公告)日：2006-03-30
申请号：JP2004267643
申请日：2004-09-15
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： MAEDA NORIAKI , SHINOZAKI YOSHIHIRO , YAMAOKA MASANAO , SHIMAZAKI YASUHISA , ISODA MASANORI , ARAI KOJI
IPC分类号： G11C11/418
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit apparatus provided with a memory circuit having a word line selecting circuit in which a leak current is reduced.
SOLUTION: This apparatus is provided with a plurality of memory cells corresponding to a plurality of word lines and a plurality of bit lines, first and second MOSFETs of a first conduction type connected between first voltage and an output terminal in series, and a third MOSFET are used as the word line selecting circuit selecting one of the plurality of word lines, a first signal is supplied to gates of the first MOSFET and the third MOSFET, a second signal is supplied to gates of the second MOSFET and a fourth MOSFET, the output terminal is connected to corresponding one out of the plurality of word lines, the first and the second MOSFETs are made an ON-state corresponding to the first signal and the second signal at the time of selecting the word line, the third and the fourth MOSFETs are made an OFF-state, the output terminal is is set to a selection level corresponding to the first voltage.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：提供一种具有存储电路的半导体集成电路装置，该存储电路具有漏电流减小的字线选择电路。解决方案：该装置设置有多个对应于多个字线和多个位线的存储单元，第一和第二导体类型的第一和第二MOSFET串联连接在第一电压和输出端之间，以及使用第三MOSFET作为选择多条字线之一的字线选择电路，第一信号被提供给第一MOSFET和第三MOSFET的栅极，第二信号被提供给第二MOSFET的栅极和第四MOSFET MOSFET，输出端子连接到多个字线中的对应的一个，在选择字线时，第一和第二MOSFET被形成对应于第一信号和第二信号的导通状态，第三使第四MOSFET成为截止状态，将输出端子设定为与第一电压对应的选择电平。版权所有（C）2006，JPO＆NCIPI

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式