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1. 发明专利

JP2013150013A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2013150013A
公开(公告)日：2013-08-01
申请号：JP2013091206
申请日：2013-04-24
申请人： Nec Corp , 日本電気株式会社 , Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： KIKUCHI MASARU , YAMAMICHI SHINTARO , MURAI HIDEYA , FUNAYA TAKUO , MORI KENTARO , MAEDA TAKEHIKO , HONDA HIROKAZU , OGAWA KENTA , TSUKANO JUN
IPC分类号： H01L23/12 , H05K3/22 , H05K3/46
CPC分类号： H05K3/205 , H01L21/4857 , H01L21/486 , H01L21/563 , H01L23/498 , H01L23/49822 , H01L23/49827 , H01L24/45 , H01L24/48 , H01L24/73 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/48472 , H01L2224/73203 , H01L2224/73204 , H01L2224/73265 , H01L2224/92247 , H01L2924/00014 , H01L2924/01019 , H01L2924/01046 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/09701 , H01L2924/12044 , H01L2924/181 , H01L2924/19041 , H05K3/244 , H05K3/423 , H05K2201/0338 , H05K2201/098 , H05K2201/09845 , H05K2203/0376 , H05K2203/0384 , H05K2203/0733 , H05K2203/1476 , H01L2924/00 , H01L2924/00012 , H01L2224/05599 , H01L2224/45015 , H01L2924/207
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device achieving high reliability.SOLUTION: A semiconductor device has a wiring board 102 and a semiconductor chip disposed on the wiring board and electrically connecting with the wiring board. The wiring board comprises: an insulation layer 11; multiple wiring layers 14 formed on the insulation layer so as to be insulated from each other; and multiple vias 16 formed in the insulation layer and connecting the wiring layers with each other. A surface wiring layer 14 formed on one surface of the insulation layer 11, from among the wiring layers, has a first metal film 12 exposed on the one surface and contacting with the insulation layer on at least a part of its side surface; and a second metal film 13 embedded in the insulation layer and laminated on the first metal film. An end part of the first metal film extends to the outer side in a surface direction of the second metal film relative to an end part of the second metal film. A surface of the first metal film lies at a position recessed from the one surface of the insulation layer. Side surfaces of a recess of the insulation layer, where the first metal film is formed, match with positions of the end parts of the first metal film. The first metal film and the second metal film are made of the same material.
摘要翻译：要解决的问题：提供一种实现高可靠性的半导体器件。解决方案：半导体器件具有布线板102和配置在布线板上并与布线板电连接的半导体芯片。布线板包括：绝缘层11; 形成在绝缘层上以便彼此绝缘的多个布线层14; 以及形成在绝缘层中并且将布线层彼此连接的多个通孔16。在布线层之间形成在绝缘层11的一个表面上的表面布线层14具有在一个表面上露出并在其侧表面的至少一部分上与绝缘层接触的第一金属膜12; 以及嵌入在绝缘层中并层压在第一金属膜上的第二金属膜13。第一金属膜的端部相对于第二金属膜的端部在第二金属膜的表面方向上延伸到外侧。第一金属膜的表面位于从绝缘层的一个表面凹陷的位置。绝缘层的形成有第一金属膜的凹部的侧面与第一金属膜的端部的位置一致。第一金属膜和第二金属膜由相同的材料制成。

2. 发明专利

JP2011238755A Semiconductor device manufacturing method 审中-公开
标题翻译：半导体器件制造方法
公开(公告)号：JP2011238755A
公开(公告)日：2011-11-24
申请号：JP2010108447
申请日：2010-05-10
申请人： Nec Corp , Renesas Electronics Corp , ルネサスエレクトロニクス株式会社 , 日本電気株式会社
发明人： MURAI HIDEYA , YAMAMICHI SHINTARO , MORI KENTARO , KIKUCHI KATSUMI , NAKAJIMA YOSHIKI , KOMURO MASAHIRO , MIZUSHIMA KAZUYUKI
IPC分类号： H01L23/12
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method that is excellent in productivity and manufactures semiconductor devices easily and with high yield.SOLUTION: A semiconductor manufacturing method comprises a step of mounting plural semiconductor chips 2 on support plates 1, a step of integrating two support plates 1 while surfaces of the support plates on which no semiconductor chip is mounted face each other, thereby forming a composite plate, a step of forming insulating layers and wires on both the surfaces of the composite plate, and a step of separating the composite plate into the two support plates 1 to achieve two chip-arranged substrates on which the semiconductor chips 2, the insulating layer and the wires are provided. When the composite plate is formed, the semiconductor chips 2 are mounted on the respective support plates 1 so that the mount positions of the semiconductor chips 2 on one of the support plate 1 are displaced from the mount positions of the corresponding semiconductor chips 2 on the other support plate 1.
摘要翻译：要解决的问题：提供一种生产率优异并且容易且高产率地制造半导体器件的半导体器件制造方法。解决方案：半导体制造方法包括将多个半导体芯片2安装在支撑板1上的步骤，在两个支撑板1之间集成的步骤，而其上没有安装半导体芯片的支撑板的表面彼此面对，从而形成复合板，在复合板的两个表面上形成绝缘层和电线的步骤以及将复合板分离成两个支撑板1以实现两个芯片布置的基板的步骤，半导体芯片2，绝缘层和导线。当形成复合板时，将半导体芯片2安装在各个支撑板1上，使得支撑板1中的一个上的半导体芯片2的安装位置从相应的半导体芯片2的安装位置移位到其他支撑板1.版权所有（C）2012，JPO＆INPIT

3. 发明专利

JP2011187473A Wiring substrate with built-in semiconductor element 审中-公开
标题翻译：具有内置半导体元件的接线衬底
公开(公告)号：JP2011187473A
公开(公告)日：2011-09-22
申请号：JP2010047862
申请日：2010-03-04
申请人： Nec Corp , Renesas Electronics Corp , ルネサスエレクトロニクス株式会社 , 日本電気株式会社
发明人： YAMAMICHI SHINTARO , MURAI HIDEYA , MORI KENTARO , KIKUCHI KATSU , NAKAJIMA YOSHIKI , KAWANO MASAYA , KOMURO MASAHIRO
IPC分类号： H01L23/12 , H05K3/46
CPC分类号： H01L23/522 , H01L24/19 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/32225 , H01L2224/73267 , H01L2924/13091 , H01L2924/1461 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a thin and highly reliable wiring substrate having a highly dense semiconductor element built in the substrate. SOLUTION: In a wiring substrate having a built-in semiconductor element 117, the wiring substrate includes a supporting substrate 101, a semiconductor element provided on the supporting substrate, a peripheral insulating layer 113 for covering an outer circumferential side surface of the semiconductor element, and an upper surface-side wiring on the upper surface side of the wiring substrate. The semiconductor element includes a semiconductor substrate 103, a first wiring-structure layer including a first wiring and a first insulating layer alternately formed on the semiconductor substrate, and a second wiring-structure layer including second wiring and a second insulating layer alternately formed on the first wiring-structure layer. The upper surface-side wiring includes a fan-out wiring led out from immediately above the semiconductor element to a peripheral region external to an outer edge of the semiconductor element. The fan-out wiring is electrically connected to the first wiring through the second wiring. The second wiring is thicker than the first wiring but thinner than the upper surface-side wiring. The second insulating layer is formed of a resin material and is thicker than the first insulating layer. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种薄且高度可靠的布线基板，其具有内置在基板中的高密度半导体元件。解决方案：在具有内置半导体元件117的布线基板中，布线基板包括支撑基板101，设置在支撑基板上的半导体元件，用于覆盖支撑基板101的外周侧表面的外围绝缘层113 半导体元件和布线基板的上表面侧的上表面侧配线。半导体元件包括半导体衬底103，包括交替形成在半导体衬底上的第一布线和第一绝缘层的第一布线结构层，以及包括第二布线和第二绝缘层的第二布线结构层，第一布线结构层。上表面侧布线包括从半导体元件的正上方引出到半导体元件的外边缘外围的周边区域的扇出布线。扇出布线通过第二布线电连接到第一布线。第二布线比第一布线厚，但比上表面布线薄。第二绝缘层由树脂材料形成，并且比第一绝缘层厚。版权所有（C）2011，JPO＆INPIT

4. 发明专利

JP2014096506A Semiconductor device and method for manufacturing semiconductor device 审中-公开
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：JP2014096506A
公开(公告)日：2014-05-22
申请号：JP2012247848
申请日：2012-11-09
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： MORI KENTARO , MOTOHASHI NORIKAZU , NISHIYAMA TOMOHIRO , KIDA TAKESHI , YAMAUCHI AYA
IPC分类号： H01L23/12 , H01L23/32 , H05K3/46
CPC分类号： H01L2224/16225 , H01L2924/15311
摘要： PROBLEM TO BE SOLVED: To allow for wiring body check before mounting a semiconductor chip.SOLUTION: A first terminal TER1 is located on a first surface SFC1 of a wiring body ITP, and connected to a solder bump BMP. A second terminal TER2 is located on a second surface SFC2 of the wiring body ITP, and connected to the first terminal TER1 via a first connection path CNC1. The first connection path CNC1 is provided in the wiring body ITP. A third terminal TER3 is located on the first surface SFC1 of the wiring body ITP, and electrically connected to the second terminal TER2. In the embodiment shown in Fig., the third terminal TER3 is connected to the second terminal TER2 via a second connection path CNC2. The second connection path CNC2 is provided in the wiring body ITP. The third terminal TER3 is not connected to the solder bump BMP. The third terminal TER3 is covered by an underfill resin UFR.
摘要翻译：要解决的问题：在安装半导体芯片之前允许布线体检查。解决方案：第一端子TER1位于布线体ITP的第一表面SFC1上，并连接到焊料凸块BMP。第二端子TER2位于布线体ITP的第二表面SFC2上，并经由第一连接路径CNC1与第一端子TER1连接。第一连接路径CNC1设置在配线体ITP中。第三端子TER3位于布线体ITP的第一面SFC1上，与第二端子TER2电连接。在图中所示的实施例中，第三终端TER3经由第二连接路径CNC2连接到第二终端TER2。第二连接路径CNC2设置在配线体ITP中。第三端子TER3未连接到焊料凸块BMP。第三终端TER3由底部填充树脂UFR覆盖。

5. 发明专利

JP2012227379A Semiconductor device and manufacturing method of the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2012227379A
公开(公告)日：2012-11-15
申请号：JP2011094068
申请日：2011-04-20
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： YAMAMICHI SHINTARO , TAKAHASHI NOBUAKI , MORI KENTARO , WATANABE TAKAHITO
IPC分类号： H01L21/60 , H01L21/3205 , H01L21/768 , H01L23/522 , H01L23/532
CPC分类号： H01L24/05 , H01L24/03 , H01L24/73 , H01L2224/02166 , H01L2224/04042 , H01L2224/05093 , H01L2224/05624 , H01L2224/05647 , H01L2224/05676 , H01L2224/32225 , H01L2224/32245 , H01L2224/45015 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/45664 , H01L2224/48 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/48453 , H01L2224/48463 , H01L2224/48465 , H01L2224/48471 , H01L2224/48479 , H01L2224/48599 , H01L2224/48799 , H01L2224/73265 , H01L2924/00011 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/13091 , H01L2924/15311 , H01L2924/181 , H01L2224/48227 , H01L2924/00012 , H01L2924/00 , H01L2924/00014 , H01L2924/01005 , H01L2924/01004 , H01L2924/00015 , H01L2924/01033
摘要： PROBLEM TO BE SOLVED: To suppress metal splashes caused by an impact occurring during bonding even though a wire is a Cu wire.SOLUTION: A semiconductor device includes: a semiconductor chip having an electrode pad 103; and a wire (for example, a Cu wire 105) bonded to an electrode pad 103. In the electrode pad 103, at least a surface layer of a region where the wire is bonded is formed by ruthenium or ruthenium oxide, and the film thickness of the surface layer is 20 nm or thicker.
摘要翻译：要解决的问题：为了抑制在接合期间发生的冲击引起的金属飞溅，即使线是Cu线。解决方案：半导体器件包括：具有电极焊盘103的半导体芯片; 以及与电极焊盘103接合的导线（例如Cu线105）。在电极焊盘103中，通过钌或氧化钌形成至少接合线的区域的表面层，膜厚的表层为20nm以上。版权所有（C）2013，JPO＆INPIT

6. 发明专利

JP2012099860A Wiring board with metal post, semiconductor device and semiconductor device module 审中-公开
标题翻译：带金属接线的接线板，半导体器件和半导体器件模块
公开(公告)号：JP2012099860A
公开(公告)日：2012-05-24
申请号：JP2012023552
申请日：2012-02-06
申请人： Nec Corp , 日本電気株式会社
发明人： MORI KENTARO , KIKUCHI MASARU , YAMAMICHI SHINTARO
IPC分类号： H01L23/12 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L2224/13018 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/01322 , H01L2924/15311 , H01L2924/15331 , H01L2924/00012 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a wiring board exhibiting high adhesion to a resin mold and having metal posts ensuring high long term reliability, and to provide a semiconductor device using the wiring board having metal posts, a semiconductor device module and manufacturing methods therefor.SOLUTION: A wiring board 101 comprises a substrate 10 consisting of at least one wiring layer and at least one insulating layer, and a plurality of metal posts 11 provided on one surface of the substrate 10. At least one metal post 11 is an irregular shape post having at least one convex portion in the shape of longitudinal section, and having at least one concave portion or convex portion in the cross-sectional shape and at at least a part of the metal post 11 in the height direction.
摘要翻译：要解决的问题：提供一种对树脂模具具有高粘附性并具有确保高长期可靠性的金属柱的布线板，并且提供使用具有金属柱的接线板的半导体器件，半导体器件模块和制造方法。解决方案：布线板101包括由至少一个布线层和至少一个绝缘层构成的基板10和设置在基板10的一个表面上的多个金属柱11.至少一个金属柱11是具有至少一个呈纵向截面形状的凸起部分的不规则形状的支柱，并且具有截面形状的至少一个凹部或凸部以及金属柱11的高度方向的至少一部分。版权所有（C）2012，JPO＆INPIT

7. 发明专利

JP2010245269A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2010245269A
公开(公告)日：2010-10-28
申请号：JP2009092110
申请日：2009-04-06
申请人： Nec Corp , 日本電気株式会社
发明人： OSHIMA DAISUKE , KIKUCHI KATSU , MORI KENTARO , NAKAJIMA YOSHIKI , YAMAMICHI SHINTARO
IPC分类号： H01L25/065 , H01L23/12 , H01L25/07 , H01L25/18
CPC分类号： H01L2224/16225 , H01L2224/73253 , H01L2924/15311
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that is improved in noise resistance while including a support for suppressing warpage of a substrate.
SOLUTION: The semiconductor device includes a first carrier substrate (printed wiring board 5a) mounted with a first semiconductor chip (LSI chip 1), a first electrode (support 3a) supporting the first carrier substrate and covering the first semiconductor chip, a dielectric layer 4 provided on the first electrode, a second electrode (ground plane 11) opposed to the first electrode with the dielectric layer 4 interposed, a second carrier substrate (printed wiring board 5b) arranged on the second electrode and mounted with a second semiconductor chip (LSI chip 2), and a third electrode (support 3b) supporting the second carrier substrate and covering the second semiconductor chip, wherein the first electrode or the second electrode is electrically connected to a power supply terminal of the second semiconductor chip and a predetermined voltage is applied between the first electrode and the second electrode.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种提高耐噪声性的半导体器件，同时包括用于抑制基板翘曲的支撑。解决方案：半导体器件包括安装有第一半导体芯片（LSI芯片1）的第一载体衬底（印刷线路板5a），支撑第一载体衬底并覆盖第一半导体芯片的第一电极（支撑体3a）设置在第一电极上的电介质层4，与介电层4插入的与第一电极相对的第二电极（接地平面11），布置在第二电极上的第二载体基板（印刷线路板5b）半导体芯片（LSI芯片2）和支撑第二载体基板并覆盖第二半导体芯片的第三电极（支撑体3b），其中第一电极或第二电极电连接到第二半导体芯片的电源端子，以及在第一电极和第二电极之间施加预定电压。版权所有（C）2011，JPO＆INPIT

8. 发明专利

JP2008306071A Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2008306071A
公开(公告)日：2008-12-18
申请号：JP2007153293
申请日：2007-06-08
申请人： Nec Corp , Nec Electronics Corp , Necエレクトロニクス株式会社 , 日本電気株式会社
发明人： MORI KENTARO , YAMAMICHI SHINTARO , MURAI HIDEYA , FUNAYA TAKUO , KAWANO MASAYA , MAEDA TAKEHIKO , SOEJIMA KOJI
IPC分类号： H01L23/12
CPC分类号： H01L21/6835 , H01L23/5389 , H01L23/544 , H01L24/19 , H01L24/24 , H01L2221/68345 , H01L2223/5442 , H01L2223/54426 , H01L2223/54473 , H01L2223/54486 , H01L2224/04105 , H01L2224/24226 , H01L2224/32225 , H01L2224/73267 , H01L2224/82039 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01038 , H01L2924/0104 , H01L2924/01041 , H01L2924/01046 , H01L2924/01047 , H01L2924/01056 , H01L2924/01057 , H01L2924/01073 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/12044 , H01L2924/15174 , H01L2924/15788 , H01L2924/181 , H01L2924/18162 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/3011 , Y10S438/977 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of achieving high density, thin shape and low cost, which achieves chip mounting with high precision, which needs no preparation of position marks on a base material at the time of chip mounting on the base material in a manufacturing process, and which can make removing of the base material easy, and a method for manufacturing the same. SOLUTION: A transparent substrate 23 is arranged on a support substrate 21 provided with position marks 22, and a lifting material 24 is provided thereon. On the lifting material 24, a semiconductor element 11 is arranged so that electrode elements 13 are upside, and, thereafter, the support substrate 21 is removed. Subsequently, after an insulating resin 12 is formed on the lifting material 24 so as to cover the semiconductor element 11, vias 14, a wiring layer 15, an insulating layer 16, external terminals 17 and a solder resist 18 are formed. Thereafter, the transparent substrate 23 is removed from the semiconductor device by the lifting material 24. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了提供能够实现高密度，薄形状和低成本的半导体器件，其实现了高精度的芯片安装，在芯片安装时不需要在基材上准备位置标记在制造工艺中的基材上，并且能够容易地除去基材，以及其制造方法。解决方案：在设置有位置标记22的支撑基板21上设置透明基板23，并且在其上设置提升材料24。在提升材料24上，配置半导体元件11，使得电极元件13是上侧，之后移除支撑基板21。随后，在提升材料24上形成绝缘树脂12以覆盖半导体元件11，通孔14之后，形成布线层15，绝缘层16，外部端子17和阻焊剂18。此后，透明基板23由提升材料24从半导体器件移除。版权所有（C）2009，JPO＆INPIT

9. 发明专利

JP2007335464A Wiring board provided with metal post, semiconductor device, semiconductor device module, and manufacturing method therefor 有权
标题翻译：配有金属引脚的接线板，半导体器件，半导体器件模块及其制造方法
公开(公告)号：JP2007335464A
公开(公告)日：2007-12-27
申请号：JP2006162601
申请日：2006-06-12
申请人： Nec Corp , 日本電気株式会社
发明人： MORI KENTARO , KIKUCHI KATSU , YAMAMICHI SHINTARO
IPC分类号： H01L23/12 , H01L25/065 , H01L25/07 , H01L25/18 , H05K1/14 , H05K3/36
CPC分类号： H01L2224/11436 , H01L2224/1161 , H01L2224/11901 , H01L2224/13015 , H01L2224/13017 , H01L2224/13018 , H01L2224/13566 , H01L2224/16225 , H01L2224/32225 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2924/01046 , H01L2924/01322 , H01L2924/15311 , H01L2924/15321 , H01L2924/15331 , H01L2924/00012 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a wiring board which is high in adhesiveness to resin mold and is provided with a metal post superior in long-term reliability, to provide a semiconductor device using the wiring board provided with the metal post, to provide a semiconductor device module, and to provide a manufacturing method therefor. SOLUTION: The wiring board 101 is provided with a base 10 which is comprised of at least one wiring layer and at least one insulation layer, and a plurality of metal posts 11 provided on one surface of the base 10. In this case, at least one metal post 11 is provided with at least one convex in longitudinally sectional shape, and it is an irregular post, which has at least one concave or one convex in laterally sectional shape at least in a part in the direction of its height. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决问题的方案为了提供一种与树脂模具的粘合性高并且设置有长期可靠性优良的金属柱的布线板，提供一种使用设置有金属柱的布线板的半导体装置，提供半导体器件模块，并提供其制造方法。解决方案：布线板101设置有由至少一个布线层和至少一个绝缘层构成的基座10和设置在基座10的一个表面上的多个金属柱11.在这种情况下至少一个金属柱11设置有纵向截面形状的至少一个凸起，并且其是不规则的柱，其具有沿其高度方向至少一部分的横截面形状中的至少一个凹入或一个凸起。版权所有（C）2008，JPO＆INPIT

10. 发明专利

JP2013236105A Coreless wiring board, semiconductor device, and manufacturing methods of coreless wiring board and semiconductor device 审中-公开
标题翻译：无线接线板，半导体器件及无线接线板和半导体器件的制造方法
公开(公告)号：JP2013236105A
公开(公告)日：2013-11-21
申请号：JP2013167339
申请日：2013-08-12
申请人： Nec Corp , 日本電気株式会社
发明人： MORI KENTARO , YAMAMICHI SHINTARO , SASAKI HIDEKI , OSHIMA DAISUKE
IPC分类号： H05K3/46 , H01L23/12
CPC分类号： H01L23/5389 , H01L24/24 , H01L24/82 , H01L2224/04105 , H01L2224/16225 , H01L2224/24051 , H01L2224/24226 , H01L2224/32225 , H01L2224/73204 , H01L2224/73267 , H01L2224/92244 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01056 , H01L2924/01058 , H01L2924/01073 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/09701 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H05K1/113 , H05K1/115 , H05K1/186 , H05K3/20 , H05K3/4602 , H05K3/4682 , H05K3/4688 , H05K2201/0352 , H05K2201/10674 , H05K2203/1469 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a coreless wiring board which achieves high yield and excellent reliability, and to provide a semiconductor device and a manufacturing method of the semiconductor device.SOLUTION: In a semiconductor device, a semiconductor element 13 is embedded in an insulation layer 15, and electrical continuity is made between an external connection terminal 23 and an electrode terminal 14 through at least one of wiring 17, 20, 23, 33 or vias 16, 19, 22, 30, 32. Insulation layers 15, 18, 21 and wiring layers 17, 20, 23, 33 are laminated on front and rear sides of the semiconductor element 13. At least one of the vias 16, 19, 22, 30, 32 or the wiring 17, 20, 23, 33 has a cross section shape different from those of the vias or the wiring which is provided on other insulation layers or other wiring layers. The semiconductor device has the insulation layers 15, 18, 21 of the multiple insulation layers 15, 18, 21, which are made of an insulation material different from those of the other insulation layers 15, 18, 21. The elastic modulus of the insulation layers 15, 18, 21 gradually gets higher from the closest layer of the electrode terminal 14 toward layers at the external connection terminal 23 side on the front and rear sides of the semiconductor device.
摘要翻译：要解决的问题：提供一种实现高产率和优异可靠性的无芯线路板，并提供半导体器件的半导体器件和制造方法。解决方案：在半导体器件中，将半导体元件13嵌入绝缘体层15，并且通过布线17,20,23,33或通孔16,19,22,30,32中的至少一个在外部连接端子23和电极端子14之间进行电连续性。绝缘层15,18， 21和布线层17,20,23,33层叠在半导体元件13的前侧和后侧。通孔16,19,22,30,32中的至少一个或布线17,20,23,33具有横截面形状不同于设置在其它绝缘层或其它布线层上的通孔或布线的截面形状。该半导体器件具有多个绝缘层15,18,21的绝缘层15,18,21，绝缘层15,18,21由与绝缘层15,18,21不同的绝缘材料制成。绝缘层的弹性模量层15,18,21从电极端子14的最靠近层朝向半导体器件的前后侧的外部连接端子23侧的层逐渐变高。

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