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1. 发明专利

JP2010245269A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2010245269A
公开(公告)日：2010-10-28
申请号：JP2009092110
申请日：2009-04-06
申请人： Nec Corp , 日本電気株式会社
发明人： OSHIMA DAISUKE , KIKUCHI KATSU , MORI KENTARO , NAKAJIMA YOSHIKI , YAMAMICHI SHINTARO
IPC分类号： H01L25/065 , H01L23/12 , H01L25/07 , H01L25/18
CPC分类号： H01L2224/16225 , H01L2224/73253 , H01L2924/15311
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that is improved in noise resistance while including a support for suppressing warpage of a substrate.
SOLUTION: The semiconductor device includes a first carrier substrate (printed wiring board 5a) mounted with a first semiconductor chip (LSI chip 1), a first electrode (support 3a) supporting the first carrier substrate and covering the first semiconductor chip, a dielectric layer 4 provided on the first electrode, a second electrode (ground plane 11) opposed to the first electrode with the dielectric layer 4 interposed, a second carrier substrate (printed wiring board 5b) arranged on the second electrode and mounted with a second semiconductor chip (LSI chip 2), and a third electrode (support 3b) supporting the second carrier substrate and covering the second semiconductor chip, wherein the first electrode or the second electrode is electrically connected to a power supply terminal of the second semiconductor chip and a predetermined voltage is applied between the first electrode and the second electrode.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种提高耐噪声性的半导体器件，同时包括用于抑制基板翘曲的支撑。解决方案：半导体器件包括安装有第一半导体芯片（LSI芯片1）的第一载体衬底（印刷线路板5a），支撑第一载体衬底并覆盖第一半导体芯片的第一电极（支撑体3a）设置在第一电极上的电介质层4，与介电层4插入的与第一电极相对的第二电极（接地平面11），布置在第二电极上的第二载体基板（印刷线路板5b）半导体芯片（LSI芯片2）和支撑第二载体基板并覆盖第二半导体芯片的第三电极（支撑体3b），其中第一电极或第二电极电连接到第二半导体芯片的电源端子，以及在第一电极和第二电极之间施加预定电压。版权所有（C）2011，JPO＆INPIT

2. 发明专利

JP2009016466A Wiring board complex, and manufacturing method of the wiring board complex, wiring board and semiconductor device 有权
标题翻译：接线板复合件及其制造方法，接线板和半导体器件
公开(公告)号：JP2009016466A
公开(公告)日：2009-01-22
申请号：JP2007174773
申请日：2007-07-03
申请人： Nec Corp , 日本電気株式会社
发明人： KIKUCHI KATSU , FUNATO SHINYA
IPC分类号： H05K1/02 , H01L23/12 , H05K3/00
摘要： PROBLEM TO BE SOLVED: To easily divide even a thin wiring board complex for taking many boards, and to easily form a wiring board in a desired shape. SOLUTION: The wiring board complex has a release layer 107 on a base 106 (a). An insulation layer 105 1 is formed, an insulation layer of a divided region 113 is removed, and a conductive post 103 is formed on the removed part (b). A conductive pattern 104 1 is formed (c). An insulation layer 105 2 is formed, an insulation layer on a via forming location and the divided region 113 is removed, a copper film is embedded on the part, and thereafter a conductive pattern 104 2 is formed (d). An insulation layer 105 3 , a copper film embedded in its aperture and a conductive pattern 104 3 are formed through a similar process (e). The base 106 is peeled off (f). A metallic pattern 113a is drawn out from the wiring board complex 111 and divided into individual wiring boards 112 (g). COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了容易地分割用于吸收许多板的薄的布线板复合体，并且容易地形成所需形状的布线板。解决方案：布线板复合体在基底106（a）上具有剥离层107。形成绝缘层105 <1> ，除去分割区域113的绝缘层，并且在去除部分（b）上形成导电柱103。形成导电图案104 1（c）。形成绝缘层105 ，通孔形成位置上的绝缘层，去除分割区域113，在该部件上嵌入铜膜，然后将导电图案104 <2> 形成（d）。通过类似的工艺（e）形成绝缘层105 <3>，嵌入其孔中的铜膜和导电图案104 <3> / SB>。基底106被剥离（f）。将金属图案113a从布线基板111拉出，分割为各个布线板112（g）。版权所有（C）2009，JPO＆INPIT

3. 发明专利

JP2008283226A Wiring board for mounting semiconductor device and its manufacturing method, and semiconductor package 审中-公开
标题翻译：用于安装半导体器件的接线板及其制造方法和半导体封装
公开(公告)号：JP2008283226A
公开(公告)日：2008-11-20
申请号：JP2008220626
申请日：2008-08-29
申请人： Nec Corp , 日本電気株式会社
发明人： ORITO NAONORI , KIKUCHI KATSU , MATSUI KOJI , BABA KAZUHIRO
IPC分类号： H01L23/12
摘要： PROBLEM TO BE SOLVED: To provide a wiring board for mounting semiconductor devices, which can achieve high density mounting and fine wiring, corresponding to the increase in the number of terminals and the narrowing of a pitch of a semiconductor device, achieve the narrow pitch of an external electrode corresponding to the miniaturization and increased density of a system, and has improved mounting reliability. SOLUTION: The wiring board for mounting semiconductor devices comprises: an insulating layer 6 composed of a single layer; wiring 8 formed on the upper surface of the insulating layer; electrodes 5 each of which is formed at the lower surface side of the insulating layer so that at least the circumferential side of the upper end of the electrode is in contact with the insulating layer and at least the circumferential side of the lower end of the electrode is not in contact with the insulating layer while protruding its lower end from the lower surface of the insulating layer; vias 7 each of which is formed on the upper surface of the electrode in the insulating layer so as to conduct between the electrode and the wiring; and a supporting member 16 arranged on the surface of the insulating layer. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了提供对应于端子数量的增加和半导体器件的间距变窄的可实现高密度安装和精细布线的半导体器件的布线板，实现了对应于系统的小型化和增加密度的外部电极的窄间距，并且具有改进的安装可靠性。解决方案：用于安装半导体器件的布线板包括：由单层组成的绝缘层6; 形成在绝缘层的上表面上的布线8; 每个电极5形成在绝缘层的下表面侧，使得至少电极的上端的周向侧与绝缘层接触，并且至少电极的下端的周向侧与绝缘层不接触，同时从绝缘层的下表面突出其下端; 通孔7形成在绝缘层中的电极的上表面上，以便在电极和布线之间传导; 以及布置在绝缘层的表面上的支撑构件16。版权所有（C）2009，JPO＆INPIT

4. 发明专利

JP2006190885A Substrate for layer formation, wiring substrate and its manufacturing method, and semiconductor device and its manufacturing method 有权
标题翻译：用于层形成的基板，布线基板及其制造方法及半导体器件及其制造方法
公开(公告)号：JP2006190885A
公开(公告)日：2006-07-20
申请号：JP2005002659
申请日：2005-01-07
申请人： Nec Corp , Nec Electronics Corp , Necエレクトロニクス株式会社 , 日本電気株式会社
发明人： MURAI HIDEYA , KIKUCHI KATSU , YAMAMICHI SHINTARO , ORITO NAONORI , NAKANO KAICHIRO , MAEDA KATSUMI , TANAKA DAISUKE , SOEJIMA KOJI , KURITA YOICHIRO
IPC分类号： H01L23/12 , H01L23/32
CPC分类号： H01L2224/16
摘要： PROBLEM TO BE SOLVED: To provide a substrate for layer formation capable of easily separating a wiring layer and stably forming a wiring layer, a wiring substrate and its manufacturing method, and to provide a semiconductor device and its manufacturing method. SOLUTION: There is formed an exfoliation layer composed of resin which contains an elastomer on a support substrate. After forming copper wiring 3 on the exfoliation layer, a via 5 is formed on the copper wiring 3 so that an insulating film 4 may be formed for covering portions other than the upper surface of the via 5. Furthermore, copper wiring 6 connected electrically to the copper wiring 3 through the via 5 is formed on the insulating film 4. Moreover, after forming a via 8 on the copper wiring 6 so that an insulating layer 7 may be formed for covering portions other than the upper surface of the via 8, copper wiring 9 connected electrically to the copper wiring 6 and the via 8 is formed on the insulating film 7. After the support board 1 wherein a wiring layer 11 and a wiring layer 12 are formed is carried out by plasma polymerization in gas containing a fluoridation carbon gas so as to reduce the adhesion power of the exfoliation layer, a wiring substrate 10 is obtained by separating the wiring layer 11 and the wiring layer 12. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种能够容易地分离布线层并稳定地形成布线层的层形成用基板，布线基板及其制造方法，提供半导体装置及其制造方法。解决方案：在支撑基板上形成包含弹性体的由树脂构成的剥离层。在剥离层上形成铜布线3之后，在铜布线3上形成通孔5，以形成绝缘膜4，以覆盖通孔5的上表面以外的部分。此外，铜布线6电连接到在绝缘膜4上形成通过通孔5的铜布线3.此外，在铜布线6上形成通孔8之后，可以形成用于覆盖通孔8的上表面以外的部分的绝缘层7，在绝缘膜7上形成有与铜布线6和通路8电连接的铜布线9.在其中形成布线层11和布线层12的支撑板1之后，通过在含氟化物的气体中进行等离子体聚合碳气体，以降低剥离层的附着力，通过分离布线层11和布线层12获得布线基板10.（C）2006，JPO＆NCIPI

5. 发明专利

JP2006179952A Manufacturing method of wiring board for mounting semiconductor, and manufacturing method of semiconductor apparatus 有权
标题翻译：用于安装半导体的接线板的制造方法和半导体器件的制造方法
公开(公告)号：JP2006179952A
公开(公告)日：2006-07-06
申请号：JP2006068413
申请日：2006-03-13
申请人： Nec Corp , Nec Electronics Corp , Necエレクトロニクス株式会社 , 日本電気株式会社
发明人： MURAI HIDEYA , ORITO NAONORI , FUNAYA TAKUO , KIKUCHI KATSU , YAMAMICHI SHINTARO , BABA KAZUHIRO , HONDA KOICHI , HO KEIICHIRO , MATSUI KOJI , MIYAZAKI SHINICHI
IPC分类号： H01L23/12
CPC分类号： H01L2224/48091 , H01L2224/48227 , H01L2924/15312 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To provide manufacturing methods of a wiring board for mounting a semiconductor and of a semiconductor apparatus which are effective for the increase in terminals and the fine-pitch of terminal gaps due to high-integration, high-speed, and multi-functionalization of semiconductor devices, can mount semiconductor devices especially on both surfaces of a board in a high density and with a high precesion, and is further excellent in reliability. SOLUTION: The wiring board 5 comprises at least an insulation film 1, wiring 2 formed in the insulation film 1, and a plurality of electrode pads 4 which are made mutually conductive by the wiring 2 and vias 3. The electrode pads 4 are disposed on the front and back surfaces of the insulation film 1 with the surfaces of the pads exposed and at least a part of the sides of the electrode pads embedded in the insulation film 1. The insulation film 1 is formed by forming respective electrode pads 4 on two metal sheets, stacking insulation layers and wiring on the electrode pads 4 and the metal plates, laminating, and integrating the insulation layers, and then removing the metal sheets. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提供用于安装半导体的布线板和半导体装置的制造方法，其对于增加端子和由于高集成度而导致的端子间隙的微细间距高效率和半导体器件的多功能化，可以以高密度和高密度安装半导体器件，特别是在板的两个表面上，并且其可靠性更好。解决方案：布线板5至少包括绝缘膜1，形成在绝缘膜1中的布线2和由布线2和通孔3相互导电的多个电极焊盘4.电极焊盘4 设置在绝缘膜1的前表面和后表面上，其中焊盘的表面暴露，并且电极焊盘的至少一部分侧面嵌入绝缘膜1中。绝缘膜1通过形成相应的电极焊盘 4的两个金属片，堆叠绝缘层和电极焊盘4和金属板上的布线，层压并整合绝缘层，然后去除金属片。版权所有（C）2006，JPO＆NCIPI

6. 发明专利

JP2006157065A Method for manufacturing semiconductor package substrate and method for manufacturing semiconductor device 有权
标题翻译：制造半导体封装基板的方法及制造半导体器件的方法
公开(公告)号：JP2006157065A
公开(公告)日：2006-06-15
申请号：JP2006068422
申请日：2006-03-13
申请人： Nec Corp , 日本電気株式会社
发明人： KIKUCHI KATSU , ORITO NAONORI , BABA KAZUHIRO , MATSUI KOJI
IPC分类号： H01L23/12
CPC分类号： H01L2224/19 , H01L2924/01013 , H01L2924/0105 , H01L2924/014 , H01L2924/15787 , H01L2924/19041 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor package substrate, which is easy to form many pins, easy to realize high density and miniaturization, having high reliability and no need for installing a stiffener, by improving a traditional semiconductor package substrate and enhancing a flatness of a multi-layer wiring structure film, and method for manufacturing a semiconductor device using the same. SOLUTION: In the method for manufacturing the semiconductor device, formation processes of insulation layers 13 and wiring layers 14 are repeated, and further metal pads 29 are formed. Thereby, on a metal base 11a, a multi-layer wiring structure film 15 is formed, which is composed of a metal pads 12, to insulation layers 13, the wiring layers 14 and the metal pads 29. Next, the metal base 11a is sliced and divided along a plane parallel to its front surface by a slicer, a water cutter, or the like. Thereby, the metal base 11a is divided into two sheets of metal bases 11, on whose sides, multi-layer wiring structure films 15 are formed. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决方案：提供一种容易形成许多销的半导体封装基板的制造方法，易于实现高密度和小型化，具有高可靠性并且不需要安装加强件，通过改进传统的半导体封装基板和提高多层布线结构膜的平坦度，以及使用其形成半导体器件的半导体器件的制造方法。解决方案：在制造半导体器件的方法中，重复绝缘层13和布线层14的形成过程，并且形成另外的金属焊盘29。由此，在金属基体11a上，形成有由金属焊盘12构成的多层布线结构膜15到绝缘层13，布线层14和金属焊盘29.接下来，金属基底11a 通过切片机，切割机等沿着平行于其前表面的平面切片分割。由此，金属基体11a被分成两层金属基体11，其两侧形成有多层布线结构膜15。版权所有（C）2006，JPO＆NCIPI

7. 发明专利

JP2003347459A Semiconductor device mounted substrate, method for manufacturing the same, method for checking the same and semiconductor package 有权
标题翻译：半导体器件安装衬底，其制造方法，用于检查其的方法和半导体封装
公开(公告)号：JP2003347459A
公开(公告)日：2003-12-05
申请号：JP2002151864
申请日：2002-05-27
申请人： Nec Corp , 日本電気株式会社
发明人： KIKUCHI KATSU , ORITO NAONORI , BABA KAZUHIRO
IPC分类号： H01L23/12 , H01L23/13 , H01L23/14 , H01L23/16 , H01L23/31 , H01L23/498
CPC分类号： H01L23/13 , H01L23/16 , H01L23/3121 , H01L23/49822 , H01L2221/68345 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2224/16235 , H01L2224/73204 , H01L2224/73253 , H01L2924/01019 , H01L2924/01046 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/19041
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device mounted substrate and a method for manufacturing it and a method for checking the substrate and a semiconductor package capable of realizing high density and micronization corresponding to pitch narrowing, and making mounting reliability excellent by improving a conventional wiring board. SOLUTION: This semiconductor device mounted substrate is provided with a wiring structural film constituted of an insulating layer and a wiring layer, a first electrode pattern formed on one face of the wiring structural film wherein at least the surrounding of the first electrode pattern side face is connected to the insulating layer, and at least the first electrode pattern lower face is not connected to the insulating layer, and the insulating layer face on which the first electrode pattern is formed and the first electrode pattern lower face are formed on the same plane, the second electrode pattern at the opposite side of the first electrode pattern, an insulator film having an opening pattern within the first electrode pattern, and a metallic supporting body formed on the insulator film surface. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供一种半导体器件安装的基板及其制造方法以及用于检查基板的方法和能够实现与间距变窄对应的高密度和微米化的半导体封装，并且通过以下方式使安装可靠性优异：改进传统的布线板。解决方案：该半导体器件安装基板设置有由绝缘层和布线层构成的布线结构膜，形成在布线结构膜的一个面上的第一电极图案，其中至少第一电极图案的周围侧面连接到绝缘层，并且至少第一电极图案下表面没有连接到绝缘层，并且在其上形成有第一电极图案的绝缘层面和第一电极图案下表面在第一电极图案的相对侧的第二电极图案，在第一电极图案内具有开口图案的绝缘膜，以及形成在绝缘膜表面上的金属支撑体。版权所有（C）2004，JPO

8. 发明专利

JP2012069863A Wiring board and manufacturing method therefor 有权
标题翻译：接线板及其制造方法
公开(公告)号：JP2012069863A
公开(公告)日：2012-04-05
申请号：JP2010215256
申请日：2010-09-27
申请人： Nec Corp , Nec Toppan Circuit Solutions Inc , 日本電気株式会社 , 株式会社トッパンNecサーキットソリューションズ
发明人： KIKUCHI KATSU , YAMAMICHI SHINTARO , MURAI HIDEYA , MORI KENTARO , NAKAJIMA YOSHIKI , OSHIMA DAISUKE , AKIMOTO YUTAKA , ISHIOKA TAKU
IPC分类号： H05K3/46 , H01L23/12
CPC分类号： H01L2224/04105 , H01L2224/18 , H01L2224/24195 , H01L2224/73267 , H01L2224/92244 , H01L2924/19105 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a thin wiring board excellent in rigidity, having an embedded electronic component.SOLUTION: The wiring board having the embedded electronic component includes: a base insulation layer; a pedestal pattern disposed on the upper face side of the base insulation layer; an electronic component on the pedestal pattern; a reinforcement insulation layer surrounding the outer circumference of the electronic component; a core wiring structure layer disposed on the reinforcement insulation layer and including a core insulation layer, having an opening having the electronic component disposed inside, upper face-side core wiring and lower face-side core wiring; an embedded insulation layer disposed on the core wiring structure layer in a manner to embed the electronic component; and first wiring on the substrate upper face side and second wiring on the substrate lower face side electrically connected to the electronic component. The outer edge of the pedestal is placed on the outer side than the outer edge of the electronic component. The reinforcement insulation layer includes a first reinforcement fiber, which is disposed from the peripheral area of the pedestal pattern outer than the outer edge to right above the outer edge of the pedestal pattern.
摘要翻译：要解决的问题：提供具有嵌入式电子部件的刚性优异的薄布线基板。解决方案：具有嵌入式电子部件的布线基板包括：基底绝缘层; 设置在所述基底绝缘层的上表面侧的基座图案; 基座图案上的电子部件; 围绕电子部件的外周的加强绝缘层; 芯线布线结构层，设置在所述加强绝缘层上并且包括芯绝缘层，具有设置在所述电子部件内部的开口，上表面侧芯线布线和下表面侧芯线布线; 嵌入绝缘层，以嵌入电子部件的方式设置在芯线布线结构层上; 并且在基板上表面侧的第一布线和与电子部件电连接的基板下表面侧的第二布线。基座的外边缘位于电子部件的外边缘的外侧。所述加强绝缘层包括第一加强纤维，所述第一加强纤维从所述基座图案的周边区域设置在所述基座图案的外边缘的外边缘的外侧。版权所有（C）2012，JPO＆INPIT

9. 发明专利

JP2012023237A Wiring substrate with built-in function element 有权
标题翻译：具有内置功能元件的接线基板
公开(公告)号：JP2012023237A
公开(公告)日：2012-02-02
申请号：JP2010160597
申请日：2010-07-15
申请人： Nec Corp , 日本電気株式会社
发明人： NAKAJIMA YOSHIKI , YAMAMICHI SHINTARO , KIKUCHI KATSU , MORI KENTARO , MURAI HIDEYA , OSHIMA DAISUKE
IPC分类号： H05K3/46
CPC分类号： H01L2224/04105 , H01L2224/73267
摘要： PROBLEM TO BE SOLVED: To provide a wiring substrate with a built-in function element in which local concentration of stress is relaxed and generation of stress can be reduced when a function element is built in an opening provided in a reinforcement layer.SOLUTION: The wiring substrate with a built-in function element comprises a function element having an electrode terminal; a reinforcement layer in which a function element is arranged and having an opening where a part facing a corner of the function element is curved; a filling resin arranged between the function element arranged in the opening and the reinforcement layer; a stress relax via formed in the filling resin; and a first wiring layer electrically connected with the electrode terminal on the surface side of the function element where the electrode terminal is arranged.
摘要翻译：要解决的问题：为了提供具有内置功能元件的布线基板，其中功能元件内置在设置在加强层中的开口中时，其中应力的局部浓度被松弛并且可以减小应力的产生。解决方案：具有内置功能元件的布线基板包括具有电极端子的功能元件; 功能元件布置在其中具有面向功能元件的角部的部分弯曲的开口的加强层; 布置在布置在开口中的功能元件和加强层之间的填充树脂; 通过在填充树脂中形成的应力松弛; 以及与设置有电极端子的功能元件的表面侧的电极端子电连接的第一布线层。版权所有（C）2012，JPO＆INPIT

10. 发明专利

JP2011187473A Wiring substrate with built-in semiconductor element 审中-公开
标题翻译：具有内置半导体元件的接线衬底
公开(公告)号：JP2011187473A
公开(公告)日：2011-09-22
申请号：JP2010047862
申请日：2010-03-04
申请人： Nec Corp , Renesas Electronics Corp , ルネサスエレクトロニクス株式会社 , 日本電気株式会社
发明人： YAMAMICHI SHINTARO , MURAI HIDEYA , MORI KENTARO , KIKUCHI KATSU , NAKAJIMA YOSHIKI , KAWANO MASAYA , KOMURO MASAHIRO
IPC分类号： H01L23/12 , H05K3/46
CPC分类号： H01L23/522 , H01L24/19 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/32225 , H01L2224/73267 , H01L2924/13091 , H01L2924/1461 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a thin and highly reliable wiring substrate having a highly dense semiconductor element built in the substrate. SOLUTION: In a wiring substrate having a built-in semiconductor element 117, the wiring substrate includes a supporting substrate 101, a semiconductor element provided on the supporting substrate, a peripheral insulating layer 113 for covering an outer circumferential side surface of the semiconductor element, and an upper surface-side wiring on the upper surface side of the wiring substrate. The semiconductor element includes a semiconductor substrate 103, a first wiring-structure layer including a first wiring and a first insulating layer alternately formed on the semiconductor substrate, and a second wiring-structure layer including second wiring and a second insulating layer alternately formed on the first wiring-structure layer. The upper surface-side wiring includes a fan-out wiring led out from immediately above the semiconductor element to a peripheral region external to an outer edge of the semiconductor element. The fan-out wiring is electrically connected to the first wiring through the second wiring. The second wiring is thicker than the first wiring but thinner than the upper surface-side wiring. The second insulating layer is formed of a resin material and is thicker than the first insulating layer. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种薄且高度可靠的布线基板，其具有内置在基板中的高密度半导体元件。解决方案：在具有内置半导体元件117的布线基板中，布线基板包括支撑基板101，设置在支撑基板上的半导体元件，用于覆盖支撑基板101的外周侧表面的外围绝缘层113 半导体元件和布线基板的上表面侧的上表面侧配线。半导体元件包括半导体衬底103，包括交替形成在半导体衬底上的第一布线和第一绝缘层的第一布线结构层，以及包括第二布线和第二绝缘层的第二布线结构层，第一布线结构层。上表面侧布线包括从半导体元件的正上方引出到半导体元件的外边缘外围的周边区域的扇出布线。扇出布线通过第二布线电连接到第一布线。第二布线比第一布线厚，但比上表面布线薄。第二绝缘层由树脂材料形成，并且比第一绝缘层厚。版权所有（C）2011，JPO＆INPIT

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