专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2011238755A Semiconductor device manufacturing method 审中-公开
标题翻译：半导体器件制造方法
公开(公告)号：JP2011238755A
公开(公告)日：2011-11-24
申请号：JP2010108447
申请日：2010-05-10
申请人： Nec Corp , Renesas Electronics Corp , ルネサスエレクトロニクス株式会社 , 日本電気株式会社
发明人： MURAI HIDEYA , YAMAMICHI SHINTARO , MORI KENTARO , KIKUCHI KATSUMI , NAKAJIMA YOSHIKI , KOMURO MASAHIRO , MIZUSHIMA KAZUYUKI
IPC分类号： H01L23/12
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method that is excellent in productivity and manufactures semiconductor devices easily and with high yield.SOLUTION: A semiconductor manufacturing method comprises a step of mounting plural semiconductor chips 2 on support plates 1, a step of integrating two support plates 1 while surfaces of the support plates on which no semiconductor chip is mounted face each other, thereby forming a composite plate, a step of forming insulating layers and wires on both the surfaces of the composite plate, and a step of separating the composite plate into the two support plates 1 to achieve two chip-arranged substrates on which the semiconductor chips 2, the insulating layer and the wires are provided. When the composite plate is formed, the semiconductor chips 2 are mounted on the respective support plates 1 so that the mount positions of the semiconductor chips 2 on one of the support plate 1 are displaced from the mount positions of the corresponding semiconductor chips 2 on the other support plate 1.
摘要翻译：要解决的问题：提供一种生产率优异并且容易且高产率地制造半导体器件的半导体器件制造方法。解决方案：半导体制造方法包括将多个半导体芯片2安装在支撑板1上的步骤，在两个支撑板1之间集成的步骤，而其上没有安装半导体芯片的支撑板的表面彼此面对，从而形成复合板，在复合板的两个表面上形成绝缘层和电线的步骤以及将复合板分离成两个支撑板1以实现两个芯片布置的基板的步骤，半导体芯片2，绝缘层和导线。当形成复合板时，将半导体芯片2安装在各个支撑板1上，使得支撑板1中的一个上的半导体芯片2的安装位置从相应的半导体芯片2的安装位置移位到其他支撑板1.版权所有（C）2012，JPO＆INPIT

2. 发明专利

JPH09213948A MOS TYPE FIELD-EFFECT TRANSISTOR AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH09213948A
公开(公告)日：1997-08-15
申请号：JP1382396
申请日：1996-01-30
申请人： NEC CORP
发明人： MIZUSHIMA KAZUYUKI
IPC分类号： H01L29/78 , H01L21/28 , H01L21/336 , H01L21/8234 , H01L29/49
摘要： PROBLEM TO BE SOLVED: To decrease field strength applied to a gate insulating film, to carry out operation at high speed and to easily conduct connection with a circuit having a different power-supply voltage. SOLUTION: In a MOS type field-effect transistor having LDD(lightly doped drain) structure, a continuous concentration gradient consisting of impurities having the same conductivity type as a source region and a drain region is formed into the polycrystalline silicon layer of a gate polycrystalline silicon electrode 13 so that effective concentration is minimized in the vicinity of an interface with a gate insulating film 12, and a depletion layer 21 is formed near the interface with the gate insulating film 12 in the gate polycrystalline silicon electrode 13 when a high electric field is applied.

3. 发明专利

JPH0982804A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH0982804A
公开(公告)日：1997-03-28
申请号：JP26245495
申请日：1995-09-14
申请人： NEC CORP
发明人： MIZUSHIMA KAZUYUKI
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/522
摘要： PROBLEM TO BE SOLVED: To prevent the generation of separation of a photoresist and a conductive film when a dot pattern is formed by a method wherein the upper end part of the first through hole, to be formed on the first interlayer insulating film, is projected from the first interlayer insulating film, and the height of the upper end part of the through hole is formed equal to the height of the upper surface of the second layer wiring. SOLUTION: The first interlayer insulating film 3 is formed in the thickness which is thicker than the intrinsic thickness and corresponding to the thickness of the second layer wiring 5. An aperture is formed on the first interlayer insulating film 3, and the first through hole 4 is formed by filling up the tungsten of conductive material. The first interlayer insulating film 3 is etched in the thickness corresponding to the film thickness of the second layer wiring 5, and the upper end part of the first through hole 4 is projected from the first interlayer insulating film 3. As a result, the height of the upper end part of the first through hole 4 can be made equal to the height of the upper surface of the second layer wiring 5, and a laminated through hole, for which a dot pattern is unnecessary, can be formed.

4. 发明专利

JPH08130253A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND FABRICATION THEREOF 失效
公开(公告)号：JPH08130253A
公开(公告)日：1996-05-21
申请号：JP29043294
申请日：1994-10-31
申请人： NEC CORP
发明人： MIZUSHIMA KAZUYUKI
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8238 , H01L27/092 , H01L29/78
摘要： PURPOSE: To fabricate a threshold voltage clamping system input protective circuit having characteristics compatible with those of inner circuit without increasing the fabrication process. CONSTITUTION: The gate oxide 21 of an MOSFET constituting an input protective circuit 2 is deposited thicker than the gate oxide 15 of an MOSFET constituting constituting an inner circuit but thinner than a field oxide 14 constituting an isolation region. The gate oxide 21 is deposited by arranging an anti- oxidation film for forming the field oxide 14 with ultrathin width at a micro interval in the gate region of an MOSFET in the input protective circuit 2 and then oxiding the surface of a semiconductor substrate 11 in the micro interval region.

5. 发明专利

JPH06216128A MANUFACTURE FOR SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH06216128A
公开(公告)日：1994-08-05
申请号：JP2193293
申请日：1993-01-14
申请人： NEC CORP
发明人： MIZUSHIMA KAZUYUKI
IPC分类号： H01L21/283 , H01L21/3205
摘要： PURPOSE:To manufacture the structure of a perfectly flat layer insulating film without complicating the manufacturing process and without sacrificing the electric characteristics. CONSTITUTION:A feeding metal layer 13 is formed on the entire surface of a semiconductor substrate 11 through an insulating film 12. With a first photoresist film 14 as a mask, a wiring conductor 15 is formed by electrolytic plating. Then, a second photoresist film 16 is formed on the entire surface. The film 16 is etched back, and the surface of the first photoresist film 14 is exposed. Thereafter, the first photoresist film 14 is removed. The exposed feeding metal layer 13 is etched. An LPD film 17 is selectively formed by the liquid-phase growth of silicon oxide by using (super) saturated aqueous solution, which is obtained by dissolving silicon oxide into hydrosilicofluoric acid. Then, the second photoresist film 16 is removed, and a CVD oxide film 18 is formed on the entire surface.

6. 发明专利

JPH0230137A METHOD FORMING WIRING OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0230137A
公开(公告)日：1990-01-31
申请号：JP18100888
申请日：1988-07-19
申请人： NEC CORP
发明人： MIZUSHIMA KAZUYUKI
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/522
摘要： PURPOSE:To realize multilayered wiring having well covering upper-layer wiring and a high-yield and high-reliability upper- and lower-wiring connecting section by forming the lower-layer wiring after forming only a pedestal at the part proposed for forming the lower- and upper-layer wiring connecting section and forming a film of glass or organic compound of silicon as an inter-layer insulating film by an applying method. CONSTITUTION:After forming only a pedestal 102 at the part proposed for forming a lower- and upper-layer wiring connecting section on a semiconductor substrate 101 on which a semiconductor element is formed, the 2nd conductor is formed on the entire surface of the substrate followed by the formation of lower-layer wiring 103 formed by photoetching. After forming the wiring 103, a film of glass or an organic compound of silicon is formed as an inter-layer insulating film A 106 by an applying method and a through hole 108 is dug by photoetching at the part proposed to the lower- and upper-wiring layer connecting section. Then the 3rd conductor is formed and upper-layer wiring 109 is formed from the 3rd conductor by photoetching. The seat 104 for the through hole 108 is formed, for example, simultaneously with the formation of the lower wiring layer 103. In addition, the 2nd and 1st inter-layer insulating films 107 and 105 of silicon nitridized or silicon oxidized films are provided by an applying method on and below the inter-layer insulating film A 106.

7. 发明专利

JPS5783042A Manufacture of semiconductor device 失效
标题翻译：半导体器件的制造
公开(公告)号：JPS5783042A
公开(公告)日：1982-05-24
申请号：JP15900380
申请日：1980-11-12
申请人： Nec Corp
发明人： YOSHINO TETSUO , YAMAMURA SHIGEHARU , TOGASHI KOUICHI , MIZUSHIMA KAZUYUKI
IPC分类号： H01L21/306 , H01L21/31 , H01L21/762
CPC分类号： H01L21/76297
摘要： PURPOSE:To obtain an optimum substrate having the elements of different withstand voltages by a method wherein, in the substrate forming process using a dielectric isolation method, a single crystal island region is epitaxially formed, and single crystal island regions having different depths are provided. CONSTITUTION:An anisotropic etching is selectively performed on the substrate with (100) face by providing an oxide film mask, for example, a V-groove having the necessary depth is formed on the low withstand voltage elements, and after an oxide film 24, for example, has been formed in the V-groove, the substrate surface of the high withstand voltage element forming section (bottom surface is to be widened) is exposed. Then, an Si is epitaxially grown on the whole surface , and after a single crystal layer 29 has been formed on the single crystal and a polycrystalline layer 27 has also been formed on the transition region 28 and the oxide film, an oxide film 29 is formed on a single crystal layer 26. Then, using the film 29 as a mask, a layer 27 and a region 28 are removed, the exposed surface 31 of the single crystal is oxidized, and after a polycrystalline Si has been deposited in the desired thickness, the substrate crystal is ground down to the V-groove. Through these procedures, the optimized depth of the island 35 of the low withstand section and the island 36 of the high withstand section can be formed independently and the V-groove part of the high withstand section can also be narrowed, thereby enabling to miniaturize the device.
摘要翻译：目的：通过以下方法获得具有不同耐受电压的元件的最佳基板，其中在使用电介质隔离方法的基板形成工艺中，外延形成单晶岛区域，并且提供具有不同深度的单晶岛区域。构成：通过提供氧化膜掩模，在具有（100）面的基板上选择性地进行各向异性蚀刻，例如，在低耐压元件上形成具有必要深度的V形槽，在氧化膜24之后，例如，已经形成在V形槽中，高耐压元件形成部的基板表面（底面加宽）被露出。然后，在整个表面上外延生长Si，在单晶上形成单晶层29之后，在过渡区28和氧化膜上也形成多晶层27，氧化膜29为然后，使用膜29作为掩模，去除层27和区域28，单晶的暴露表面31被氧化，并且在多晶Si沉积在所需的位置之后衬底晶体被研磨到V形槽。通过这些程序，可以独立地形成低耐受部分的岛35和高耐受部分的岛36的优化深度，并且高耐压部分的V形槽部分也可以变窄，从而能够使设备。

8. 发明专利

JPH11214692A MOS-TYPE FIELD EFFECT TRANSISTOR AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH11214692A
公开(公告)日：1999-08-06
申请号：JP31217098
申请日：1998-11-02
申请人： NEC CORP
发明人： MIZUSHIMA KAZUYUKI
IPC分类号： H01L29/78 , H01L21/336
摘要： PROBLEM TO BE SOLVED: To provide a MOS-type field effect transistor that relaxes an electric field strength which is applied to a gate insulation film, fast operation is made possible, and that can be easily connected to a circuit with a differing power supply voltages. SOLUTION: In a MOS-type field effect transistor in an lightly doped drain(LDD) structure, a continuous inclination consisting of an impurity with the same conductivity type as that of source and drain regions is formed in the polycrystalline silicon layer of a gate polycrystalline silicon electrode 13, so that effective concentration is minimized near the interface with a gate insulation film 12, and a depleted layer 21 is formed near the interface with the gate insulation film 12 in the gate polycrystalline silicon electrode 13, when high electric field is applied.

9. 发明专利

JPH07122644A SEMICONDUCTOR DEVICE AND FABRICATION THEREOF 失效
公开(公告)号：JPH07122644A
公开(公告)日：1995-05-12
申请号：JP29006093
申请日：1993-10-26
申请人： NEC CORP
发明人： MIZUSHIMA KAZUYUKI
IPC分类号： C23C18/16 , C23C16/08 , H01L21/768 , H01L23/522 , H05K1/02
摘要： PURPOSE:To allow good filling of a deep hole with a conductor. CONSTITUTION:Through holes 107, 108 having different depth are made through a plurality of lower layer wirings 103, 105 having different height. A first conductor 109 is then grown in each through hole up to the height of the through hole (shallow through hole) 108 made through the lower wiring layer having higher height. A second conductor 111 is then grown on the first conductor 109 in the through hole (deep through hole) 107 made through the lower wiring having lower height. The aspect ratio of the second conductor is decreased at the time of embedding by filling the deep through hole 108 with first and second conductors 109, 131 thus realizing a god embedment.

10. 发明专利

JPH03101229A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH03101229A
公开(公告)日：1991-04-26
申请号：JP23850789
申请日：1989-09-14
申请人： NEC CORP
发明人： MIZUSHIMA KAZUYUKI
IPC分类号： H01L21/3213 , H01L21/3205
摘要： PURPOSE:To obtain fine wiring with reduced side etch and no unnecessary increase of wiring capacity and without increase of irregularity on the surface by etching the wiring metal with a photoresist pattern, wherein a pseudo wiring pattern is inserted into a place loose in wiring other than indispensable patterns, as a mask, and then removing the pseudo wiring pattern. CONSTITUTION:An insulating film 2 is formed on a semiconductor substrate 1, and is coated with wiring metal 3, and then photoresist 10 is processed into a desired shape. At this time, to get desired integrated circuit operation, a pseudo wiring photoresist pattern 5 is formed also at a place, where wiring interval is wide, in addition to necessary wiring photoresist patterns 4. Next, with the indispensable photopattern and the pseudo-wiring photoresist pattern 5 as masks, the wiring metal 3 is processed by RIE. Next, a photoresist 6 is formed so that it may cover only the indispensable wiring region, and with this as a mask, the pseudo wiring metal 7 is removed, and then the photoresist 8 is removed.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式